Searched refs:vrs (Results 1 – 13 of 13) sorted by relevance
| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_pass.c | 319 const VkFragmentShadingRateAttachmentInfoKHR *vrs = in radv_num_subpass_attachments2() local
326 (vrs && vrs->pFragmentShadingRateAttachment); in radv_num_subpass_attachments2()
466 const VkFragmentShadingRateAttachmentInfoKHR *vrs = in radv_CreateRenderPass2() local
469 if (vrs && vrs->pFragmentShadingRateAttachment) { in radv_CreateRenderPass2()
473 .attachment = vrs->pFragmentShadingRateAttachment->attachment, in radv_CreateRenderPass2()
474 .layout = vrs->pFragmentShadingRateAttachment->layout, in radv_CreateRenderPass2()
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| D | radv_device.c | 3124 device->vrs.image = radv_image_from_handle(image); in radv_device_init_vrs_state()
3125 device->vrs.buffer = radv_buffer_from_handle(buffer); in radv_device_init_vrs_state()
3126 device->vrs.mem = radv_device_memory_from_handle(mem); in radv_device_init_vrs_state()
3143 if (!device->vrs.image) in radv_device_finish_vrs_image()
3146 radv_FreeMemory(radv_device_to_handle(device), radv_device_memory_to_handle(device->vrs.mem), in radv_device_finish_vrs_image()
3148 radv_DestroyBuffer(radv_device_to_handle(device), radv_buffer_to_handle(device->vrs.buffer), in radv_device_finish_vrs_image()
3150 radv_DestroyImage(radv_device_to_handle(device), radv_image_to_handle(device->vrs.image), in radv_device_finish_vrs_image()
3356 const VkPhysicalDeviceFragmentShadingRateFeaturesKHR *vrs = (const void *)ext; in radv_CreateDevice() local
3357 attachment_vrs_enabled = vrs->attachmentFragmentShadingRate; in radv_CreateDevice()
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| D | radv_private.h | 909 } vrs; member
2145 struct radv_vrs_state vrs; member
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| D | radv_cmd_buffer.c | 1869 uint32_t pa_cl_vrs_cntl = pipeline->vrs.pa_cl_vrs_cntl; in radv_emit_fragment_shading_rate()
2730 if (!device->vrs.image) { in radv_cmd_buffer_get_vrs_image()
2741 return device->vrs.image; in radv_cmd_buffer_get_vrs_image()
2825 struct radv_buffer *htile_buffer = cmd_buffer->device->vrs.buffer; in radv_emit_framebuffer_state()
2826 struct radv_image *image = cmd_buffer->device->vrs.image; in radv_emit_framebuffer_state()
6440 struct radv_buffer *htile_buffer = cmd_buffer->device->vrs.buffer; in radv_cmd_buffer_begin_subpass()
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| D | radv_pipeline.c | 1191 struct radv_vrs_state *vrs = &pipeline->vrs; in gfx103_pipeline_init_vrs_state() local
1203 vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_VRS_COMB_MODE_OVERRIDE); in gfx103_pipeline_init_vrs_state()
1213 vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_VRS_COMB_MODE_PASSTHRU); in gfx103_pipeline_init_vrs_state()
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| /third_party/mesa3d/src/gallium/drivers/virgl/ |
| D | virgl_context.c | 460 struct virgl_rasterizer_state *vrs = CALLOC_STRUCT(virgl_rasterizer_state); in virgl_create_rasterizer_state() local
462 if (!vrs) in virgl_create_rasterizer_state()
464 vrs->rs = *rs_state; in virgl_create_rasterizer_state()
465 vrs->handle = virgl_object_assign_handle(); in virgl_create_rasterizer_state()
470 virgl_encode_rasterizer_state(vctx, vrs->handle, rs_state); in virgl_create_rasterizer_state()
471 return (void *)vrs; in virgl_create_rasterizer_state()
480 struct virgl_rasterizer_state *vrs = rs_state; in virgl_bind_rasterizer_state() local
481 vctx->rs_state = *vrs; in virgl_bind_rasterizer_state()
482 handle = vrs->handle; in virgl_bind_rasterizer_state()
491 struct virgl_rasterizer_state *vrs = rs_state; in virgl_delete_rasterizer_state() local
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| /third_party/node/deps/v8/src/execution/ppc/ |
| D | simulator-ppc.cc | 4156 DECODE_VX_INSTRUCTION(vrs, ra, rb, S) in ExecuteGeneric()
4158 __int128 vrs_val = bit_cast<__int128>(get_simd_register(vrs).int8); in ExecuteGeneric()
4187 DECODE_VX_INSTRUCTION(vrs, ra, rb, S) in ExecuteGeneric()
4190 __int128 vrs_val = bit_cast<__int128>(get_simd_register(vrs).int8); in ExecuteGeneric()
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| /third_party/skia/third_party/externals/icu/source/data/misc/ |
| D | supplementalData.txt | 7069 "vrs~t",
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| /third_party/icu/icu4c/source/data/misc/ |
| D | supplementalData.txt | 7178 "vrs~t",
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| /third_party/astc-encoder/Test/Images/HDRIHaven/HDR-RGB/ |
| D | hdr-rgb-eveningroad.hdr | 957 …�����j������¹�������������������}|~����}}{���������zy|�������������������{vrs|}~wsqsuwwxi�������…
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| D | hdr-rgb-canarywharf.hdr | 731 …dhjjhga^\YYXW�V(XX��Q\cN|[Z[\\Uii}����γ�������£�Ѧ������qrt}�}�{u�����qlgx�vrs�e���٩�ryt��lyc��֪��…
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| /third_party/openh264/res/ |
| D | Cisco_Absolute_Power_1280x720_30fps.yuv | 2311 …" !&,6Qgotuvvxzzyusojha\WRRSSOGCB=9520/.=y���������������������������yx~��vrs��������rillklkedil…
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| /third_party/NuttX/ |
| D | ReleaseNotes | 14864 documentation for the STM32F7 that limits DMA on 1 bit vrs 4 bit
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