| /third_party/openh264/codec/common/arm/ |
| D | deblocking_neon.S | 303 vswp d1, d2 define
304 vswp d3, d4 define
305 vswp d1, d4 define
306 vswp d7, d8 define
307 vswp d9, d10 define
308 vswp d7, d10 define
357 vswp q2, q3
358 vswp d3, d6 define
359 vswp d5, d8 define
426 vswp d17, d24
[all …]
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| D | mc_neon.S | 513 vswp q0, q8
514 vswp q0, q2
568 vswp q0, q2
569 vswp q1, q2
708 vswp q0, q8
709 vswp q0, q2
763 vswp q0, q2
764 vswp q1, q2
903 vswp q0, q8
904 vswp q0, q2
[all …]
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| /third_party/ffmpeg/libavcodec/arm/ |
| D | neon.S | 44 vswp \r0, \r4
45 vswp \r1, \r5
46 vswp \r2, \r6
47 vswp \r3, \r7
|
| D | vp9lpf_16bpp_neon.S | 24 vswp \r1, \r8 @ vtrn.64 \rq0, \rq4
25 vswp \r3, \r10 @ vtrn.64 \rq1, \rq5
26 vswp \r5, \r12 @ vtrn.64 \rq2, \rq6
27 vswp \r7, \r14 @ vtrn.64 \rq3, \rq7
|
| D | vc1dsp_neon.S | 145 vswp d4, d5 @ q2 = src[48]|src[16] define
162 vswp d2, d3 @ q1 = src[40]|src[8] define
164 vswp d6, d7 @ q3 = src[56]|src[24] define
167 vswp d3, d6 @ q1 = src[40]|src[56], q3 = src[8]|src[24] define
172 vswp d6, d7 @ q3 = src[24]|src[8] define
173 vswp d2, d3 @ q1 = src[56]|src[40] define
184 vswp d22, d23 @ q11 = t7|t8
|
| D | fft_neon.S | 141 vswp d25, d26 @ q12{r8,i8,i10,r11} q13{r9,i9,i11,r10}
143 vswp d29, d30 @ q14{r12,i12,i14,r15} q15{r13,i13,i15,r14}
152 vswp d1, d26 @ q0{t1,t2,t3,t4} q13{t6,t5,t7,t8} define
153 vswp d3, d30 @ q1{t1a,t2a,t3a,t4a} q15{t6a,t5a,t7a,t8a} define
159 vswp d25, d28 @ q12{r8,i8,r12,i12} q14{r9,i9,r13,i13}
165 vswp d27, d30 @ q13{r10,i10,r14,i14} q15{r11,i11,r15,i15}
220 vswp d21, d22
248 vswp d21, d22
|
| D | h264idct_neon.S | 28 vswp d1, d2 define
46 vswp d1, d3 define
206 vswp d21, d4
208 vswp d17, d24
210 vswp d19, d26
212 vswp d23, d30
|
| D | sbrdsp_neon.S | 95 vswp d0, d1 define
101 vswp d18, d19
111 vswp d0, d1 define
114 vswp d4, d5 define
131 vswp d2, d3 define
139 vswp d6, d7 define
|
| D | vp3dsp_neon.S | 255 vswp d17, d24
256 vswp d19, d26
258 vswp d21, d28
260 vswp d23, d30
|
| D | rv34dsp_neon.S | 47 vswp d3, d6 define
48 vswp d5, d16 define
|
| D | rv40dsp_neon.S | 293 vswp d0, d1 define
392 vswp d0, d1 define
531 vswp d0, d1 define
629 vswp d0, d1 define
842 vswp d3, d6 @ q1q2, p1p0 define
912 vswp d4, d5 define
|
| D | sbcdsp_neon.S | 547 vswp d5, d20 define
566 vswp d5, d20 define
660 vswp q3, q10
683 vswp q3, q10
|
| D | hpeldsp_neon.S | 231 vswp d1, d2 define
|
| D | vp9itxfm_16bpp_neon.S | 848 vswp d27, d29 @ d27 = t12, d29 = t13a
849 vswp d28, d27 @ d28 = t12, d27 = t11
|
| /third_party/openh264/codec/encoder/core/arm/ |
| D | reconstruct_neon.S | 290 vswp d1, d2 define
331 vswp d1, d2 define
332 vswp d5, d6 define
333 vswp q1, q2
355 vswp d1, d2 define
356 vswp d5, d6 define
357 vswp q1, q2
522 vswp d1, d4 //[0 4 2 6]+[8 12 10 14]-->[0 4 8 12]+[2 6 10 14] define
523 vswp d3, d6 //[1 5 3 7]+[9 13 11 15]-->[1 5 9 13]+[3 7 11 15] define
720 vswp d1, d4 define
[all …]
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| D | intra_pred_sad_3_opt_neon.S | 54 vswp d1, d2 define
|
| D | pixel_neon.S | 854 vswp d27, d24
|
| /third_party/openh264/codec/decoder/core/arm/ |
| D | block_add_neon.S | 79 vswp d1, d4 //[0 4 2 6]+[8 12 10 14]-->[0 4 8 12]+[2 6 10 14] define
80 vswp d3, d6 //[1 5 3 7]+[9 13 11 15]-->[1 5 9 13]+[3 7 11 15] define
|
| /third_party/ffmpeg/libavutil/arm/ |
| D | float_dsp_neon.S | 182 vswp d22, d23
191 vswp d22, d23
|
| /third_party/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 6075 void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm);
6076 void vswp(DataType dt, DRegister rd, DRegister rm) { vswp(al, dt, rd, rm); } in vswp() function
6077 void vswp(DRegister rd, DRegister rm) { in vswp() function
6078 vswp(al, kDataTypeValueNone, rd, rm); in vswp()
6080 void vswp(Condition cond, DRegister rd, DRegister rm) { in vswp() function
6081 vswp(cond, kDataTypeValueNone, rd, rm); in vswp()
6084 void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm);
6085 void vswp(DataType dt, QRegister rd, QRegister rm) { vswp(al, dt, rd, rm); } in vswp() function
6086 void vswp(QRegister rd, QRegister rm) { in vswp() function
6087 vswp(al, kDataTypeValueNone, rd, rm); in vswp()
[all …]
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| D | disasm-aarch32.h | 2601 void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm);
2603 void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm);
|
| /third_party/node/deps/v8/src/codegen/arm/ |
| D | assembler-arm.h | 881 void vswp(DwVfpRegister dst, DwVfpRegister src);
882 void vswp(QwNeonRegister dst, QwNeonRegister src);
|
| D | macro-assembler-arm.cc | 527 vswp(srcdst0, srcdst1); in Swap()
539 vswp(srcdst0, srcdst1); in Swap()
|
| D | assembler-arm.cc | 4175 void Assembler::vswp(DwVfpRegister dst, DwVfpRegister src) { in vswp() function in v8::internal::Assembler
4183 void Assembler::vswp(QwNeonRegister dst, QwNeonRegister src) { in vswp() function in v8::internal::Assembler
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 1190 Mnemonic = "vswp";
9957 "bw\004vswp\004vtbl\004vtbx\004vtrn\004vtst\005vudot\004vuzp\004vzip\003"
15030 …{ 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_Has…
15031 …{ 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_Has…
15032 …{ 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_Has…
15033 …{ 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_Has…
15034 …{ 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_Has…
15035 …{ 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_Has…
15036 …{ 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_Has…
15037 …{ 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_Has…
[all …]
|