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Searched refs:zsa (Results 1 – 25 of 68) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/freedreno/
Dfreedreno_state.h36 return ctx->zsa && ctx->zsa->depth_enabled; in fd_depth_enabled()
42 return ctx->zsa && ctx->zsa->depth_writemask; in fd_depth_write_enabled()
48 return ctx->zsa && ctx->zsa->stencil[0].enabled; in fd_stencil_enabled()
/third_party/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_state.h37 return ctx->zsa && ctx->zsa->depth_enabled; in etna_depth_enabled()
43 return ctx->zsa && ctx->zsa->stencil[0].enabled; in etna_stencil_enabled()
Detnaviv_state.c515 ctx->zsa = zs; in etna_zsa_state_bind()
713 struct pipe_depth_stencil_alpha_state *zsa_state = ctx->zsa; in etna_update_zsa()
714 struct etna_zsa_state *zsa = etna_zsa_state(zsa_state); in etna_update_zsa() local
734 if (zsa->z_write_enabled) { in etna_update_zsa()
737 !zsa->stencil_enabled && in etna_update_zsa()
746 if (zsa->z_test_enabled) { in etna_update_zsa()
748 !zsa->stencil_modified && in etna_update_zsa()
755 new_pe_depth = VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(zsa->z_test_enabled ? in etna_update_zsa()
758 COND(zsa->z_write_enabled, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) | in etna_update_zsa()
760 COND(!late_z_write && !late_z_test && !zsa->stencil_enabled, in etna_update_zsa()
[all …]
Detnaviv_zsa.h51 etna_zsa_state(struct pipe_depth_stencil_alpha_state *zsa) in etna_zsa_state() argument
53 return (struct etna_zsa_state *)zsa; in etna_zsa_state()
Detnaviv_emit.c417 /*00E08*/ EMIT_STATE(RA_EARLY_DEPTH, etna_zsa_state(ctx->zsa)->RA_DEPTH_CONFIG); in etna_emit_state()
433 /*01400*/ EMIT_STATE(PE_DEPTH_CONFIG, (etna_zsa_state(ctx->zsa)->PE_DEPTH_CONFIG | in etna_emit_state()
451 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP[ccw]; in etna_emit_state()
455 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG[ccw]; in etna_emit_state()
459 uint32_t val = etna_zsa_state(ctx->zsa)->PE_ALPHA_OP; in etna_emit_state()
494 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT; in etna_emit_state()
513 …/*014B8*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT2, etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT2[ccw]… in etna_emit_state()
/third_party/mesa3d/src/microsoft/vulkan/
Ddzn_pipeline.c1225 (pipeline->zsa.stencil_test.dynamic_compare_mask || in translate_stencil_test()
1231 (pipeline->zsa.stencil_test.dynamic_compare_mask || in translate_stencil_test()
1234 if (front_test_uses_ref && pipeline->zsa.stencil_test.dynamic_compare_mask) in translate_stencil_test()
1235 pipeline->zsa.stencil_test.front.compare_mask = UINT32_MAX; in translate_stencil_test()
1237 pipeline->zsa.stencil_test.front.compare_mask = in_zsa->front.compareMask; in translate_stencil_test()
1239 pipeline->zsa.stencil_test.front.compare_mask = 0; in translate_stencil_test()
1241 if (back_test_uses_ref && pipeline->zsa.stencil_test.dynamic_compare_mask) in translate_stencil_test()
1242 pipeline->zsa.stencil_test.back.compare_mask = UINT32_MAX; in translate_stencil_test()
1244 pipeline->zsa.stencil_test.back.compare_mask = in_zsa->back.compareMask; in translate_stencil_test()
1246 pipeline->zsa.stencil_test.back.compare_mask = 0; in translate_stencil_test()
[all …]
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_zsa.h59 fd6_zsa_stateobj(struct pipe_depth_stencil_alpha_state *zsa) in fd6_zsa_stateobj() argument
61 return (struct fd6_zsa_stateobj *)zsa; in fd6_zsa_stateobj()
72 return fd6_zsa_stateobj(ctx->zsa)->stateobj[variant]; in fd6_zsa_state()
Dfd6_emit.c598 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa); in compute_ztest_mode() local
604 if (fs->no_earlyz || fs->writes_pos || !zsa->base.depth_enabled || in compute_ztest_mode()
607 } else if ((fs->has_kill || zsa->alpha_test) && in compute_ztest_mode()
608 (zsa->writes_zs || !pfb->zsbuf)) { in compute_ztest_mode()
643 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa); in compute_lrz_state() local
646 lrz = zsa->lrz; in compute_lrz_state()
661 if (zsa->base.depth_enabled && (rsc->lrz_direction != FD_LRZ_UNKNOWN) && in compute_lrz_state()
666 if (zsa->invalidate_lrz || !rsc->lrz_valid) { in compute_lrz_state()
691 if (zsa->base.depth_writemask) { in compute_lrz_state()
/third_party/mesa3d/src/gallium/drivers/panfrost/
Dpan_helpers.c222 struct pipe_depth_stencil_alpha_state *zsa = (void *) ctx->depth_stencil; in panfrost_set_batch_masks_zs() local
225 if (zsa->depth_enabled) in panfrost_set_batch_masks_zs()
228 if (zsa->depth_writemask) in panfrost_set_batch_masks_zs()
231 if (zsa->stencil[0].enabled) { in panfrost_set_batch_masks_zs()
Dpan_cmdstream.c259 const struct panfrost_zsa_state *zsa) in panfrost_fs_required() argument
270 if (PAN_ARCH <= 5 && zsa->base.alpha_func != PIPE_FUNC_ALWAYS) in panfrost_fs_required()
519 const struct panfrost_zsa_state *zsa = ctx->depth_stencil; in panfrost_prepare_fs_state() local
535 if (panfrost_fs_required(fs, so, &ctx->pipe_framebuffer, zsa)) { in panfrost_prepare_fs_state()
552 ((enum mali_func) zsa->base.alpha_func == MALI_FUNC_ALWAYS); in panfrost_prepare_fs_state()
562 bool force_ez_with_discard = !zsa->enabled && !has_oq; in panfrost_prepare_fs_state()
634 bool back_enab = zsa->base.stencil[1].enabled; in panfrost_prepare_fs_state()
640 cfg.alpha_reference = zsa->base.alpha_ref_value; in panfrost_prepare_fs_state()
650 const struct panfrost_zsa_state *zsa = ctx->depth_stencil; in panfrost_emit_frag_shader() local
670 if (panfrost_fs_required(fs, ctx->blend, &ctx->pipe_framebuffer, zsa)) { in panfrost_emit_frag_shader()
[all …]
/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/
Dfd2_zsa.h45 fd2_zsa_stateobj(struct pipe_depth_stencil_alpha_state *zsa) in fd2_zsa_stateobj() argument
47 return (struct fd2_zsa_stateobj *)zsa; in fd2_zsa_stateobj()
Dfd2_emit.c238 struct fd2_zsa_stateobj *zsa = fd2_zsa_stateobj(ctx->zsa); in fd2_emit_state() local
257 uint32_t val = zsa->rb_depthcontrol; in fd2_emit_state()
268 OUT_RING(ring, zsa->rb_stencilrefmask_bf | in fd2_emit_state()
270 OUT_RING(ring, zsa->rb_stencilrefmask | in fd2_emit_state()
272 OUT_RING(ring, zsa->rb_alpha_ref); in fd2_emit_state()
375 OUT_RING(ring, zsa->rb_colorcontrol | blend->rb_colorcontrol); in fd2_emit_state()
/third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/
Dfd3_zsa.h46 fd3_zsa_stateobj(struct pipe_depth_stencil_alpha_state *zsa) in fd3_zsa_stateobj() argument
48 return (struct fd3_zsa_stateobj *)zsa; in fd3_zsa_stateobj()
Dfd3_emit.c524 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control | in fd3_emit_state()
544 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa); in fd3_emit_state() local
548 OUT_RING(ring, zsa->rb_alpha_ref); in fd3_emit_state()
551 OUT_RING(ring, zsa->rb_stencil_control); in fd3_emit_state()
554 OUT_RING(ring, zsa->rb_stencilrefmask | in fd3_emit_state()
556 OUT_RING(ring, zsa->rb_stencilrefmask_bf | in fd3_emit_state()
561 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control; in fd3_emit_state()
/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_zsa.h48 fd5_zsa_stateobj(struct pipe_depth_stencil_alpha_state *zsa) in fd5_zsa_stateobj() argument
50 return (struct fd5_zsa_stateobj *)zsa; in fd5_zsa_stateobj()
Dfd5_emit.c554 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); in fd5_emit_state() local
555 uint32_t rb_alpha_control = zsa->rb_alpha_control; in fd5_emit_state()
564 OUT_RING(ring, zsa->rb_stencil_control); in fd5_emit_state()
569 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); in fd5_emit_state() local
573 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl; in fd5_emit_state()
577 else if (emit->binning_pass && blend->lrz_write && zsa->lrz_write) in fd5_emit_state()
586 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); in fd5_emit_state() local
590 OUT_RING(ring, zsa->rb_stencilrefmask | in fd5_emit_state()
592 OUT_RING(ring, zsa->rb_stencilrefmask_bf | in fd5_emit_state()
597 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); in fd5_emit_state() local
[all …]
/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_zsa.h47 fd4_zsa_stateobj(struct pipe_depth_stencil_alpha_state *zsa) in fd4_zsa_stateobj() argument
49 return (struct fd4_zsa_stateobj *)zsa; in fd4_zsa_stateobj()
Dfd4_emit.c684 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa); in fd4_emit_state() local
686 uint32_t rb_alpha_control = zsa->rb_alpha_control; in fd4_emit_state()
695 OUT_RING(ring, zsa->rb_stencil_control); in fd4_emit_state()
696 OUT_RING(ring, zsa->rb_stencil_control2); in fd4_emit_state()
700 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa); in fd4_emit_state() local
704 OUT_RING(ring, zsa->rb_stencilrefmask | in fd4_emit_state()
706 OUT_RING(ring, zsa->rb_stencilrefmask_bf | in fd4_emit_state()
711 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa); in fd4_emit_state() local
717 OUT_RING(ring, zsa->rb_depth_control | in fd4_emit_state()
727 OUT_RING(ring, zsa->gras_alpha_control | in fd4_emit_state()
/third_party/rust/crates/bindgen/bindgen-tests/tests/expectations/tests/
Dzero-sized-array.rs74 pub zsa: ZeroSizedArray, field
92 unsafe { ::std::ptr::addr_of!((*ptr).zsa) as usize - ptr as usize }, in bindgen_test_layout_ContainsZeroSizedArray()
98 stringify!(zsa) in bindgen_test_layout_ContainsZeroSizedArray()
/third_party/mesa3d/src/gallium/drivers/vc4/
Dvc4_emit.c107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state()
110 vc4->zsa->config_bits[1]); in vc4_emit_state()
113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
/third_party/rust/crates/bindgen/bindgen-tests/tests/expectations/tests/libclang-9/
Dzero-sized-array.rs74 pub zsa: ZeroSizedArray, field
92 unsafe { ::std::ptr::addr_of!((*ptr).zsa) as usize - ptr as usize }, in bindgen_test_layout_ContainsZeroSizedArray()
98 stringify!(zsa) in bindgen_test_layout_ContainsZeroSizedArray()
/third_party/mesa3d/src/gallium/drivers/v3d/
Dv3dx_emit.c519 if (v3d->zsa->base.depth_enabled) { in v3dX()
521 v3d->zsa->base.depth_writemask; in v3dX()
525 v3d->zsa->base.depth_func; in v3dX()
531 v3d->zsa->base.stencil[0].enabled; in v3dX()
673 struct pipe_stencil_state *front = &v3d->zsa->base.stencil[0]; in v3dX()
674 struct pipe_stencil_state *back = &v3d->zsa->base.stencil[1]; in v3dX()
678 v3d->zsa->stencil_front, config) { in v3dX()
686 v3d->zsa->stencil_back, config) { in v3dX()
/third_party/mesa3d/src/gallium/auxiliary/util/
Du_inlines.h887 util_writes_depth_stencil(const struct pipe_depth_stencil_alpha_state *zsa) in util_writes_depth_stencil() argument
889 if (zsa->depth_enabled && zsa->depth_writemask && in util_writes_depth_stencil()
890 (zsa->depth_func != PIPE_FUNC_NEVER)) in util_writes_depth_stencil()
893 return util_writes_stencil(&zsa->stencil[0]) || in util_writes_depth_stencil()
894 util_writes_stencil(&zsa->stencil[1]); in util_writes_depth_stencil()
/third_party/mesa3d/src/gallium/drivers/lima/
Dlima_draw.c621 render->depth_test = lima_calculate_depth_test(&ctx->zsa->base, rst); in lima_pack_render_state()
642 struct pipe_stencil_state *stencil = ctx->zsa->base.stencil; in lima_pack_render_state()
698 if (ctx->zsa->base.alpha_enabled) { in lima_pack_render_state()
699 render->multi_sample |= ctx->zsa->base.alpha_func; in lima_pack_render_state()
700 render->stencil_test |= float_to_ubyte(ctx->zsa->base.alpha_ref_value) << 16; in lima_pack_render_state()
723 ctx->zsa->base.alpha_enabled || in lima_pack_render_state()
1024 if (ctx->zsa->base.depth_enabled) in lima_draw_vbo_update()
1026 if (ctx->zsa->base.stencil[0].enabled || in lima_draw_vbo_update()
1027 ctx->zsa->base.stencil[1].enabled) in lima_draw_vbo_update()
/third_party/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_state_validate.c342 if (nv50->zsa && nv50->zsa->pipe.alpha_enabled && in nv50_validate_derived_2()
398 PUSH_SPACE(push, nv50->zsa->size); in nv50_validate_zsa()
399 PUSH_DATAp(push, nv50->zsa->state, nv50->zsa->size); in nv50_validate_zsa()
483 if (!ctx_to->zsa) in nv50_switch_pipe_context()

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