| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_lower_to_hw_instr.cpp | 200 PhysReg vtmp_reg, ReduceOp op, unsigned dpp_ctrl, unsigned row_mask, in emit_int64_dpp_op() argument
215 bld.vop1_dpp(aco_opcode::v_mov_b32, vtmp_def[0], src0[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
220 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
223 Operand(vcc, bld.lm), dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
225 bld.vop2_dpp(aco_opcode::v_and_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
227 bld.vop2_dpp(aco_opcode::v_and_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
230 bld.vop2_dpp(aco_opcode::v_or_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
232 bld.vop2_dpp(aco_opcode::v_or_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
235 bld.vop2_dpp(aco_opcode::v_xor_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
237 bld.vop2_dpp(aco_opcode::v_xor_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
[all …]
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| D | aco_opt_value_numbering.cpp | 182 aDPP.bank_mask == bDPP.bank_mask && aDPP.row_mask == bDPP.row_mask && in operator ()()
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| D | aco_print_ir.cpp | 603 if (dpp.row_mask != 0xf) in print_instr_format_specific()
604 fprintf(output, " row_mask:0x%.1x", dpp.row_mask); in print_instr_format_specific()
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| D | aco_optimizer_postRA.cpp | 442 assert(mov->dpp16().row_mask == 0xf && mov->dpp16().bank_mask == 0xf); in try_combine_dpp()
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| D | aco_ir.cpp | 381 dpp->row_mask = 0xf; in convert_to_DPP()
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| D | aco_assembler.cpp | 683 uint32_t encoding = (0xF & dpp.row_mask) << 28; in emit_instruction()
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| D | aco_ir.h | 1446 uint8_t row_mask : 4; member
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| D | aco_optimizer.cpp | 1752 assert(instr->dpp16().row_mask == 0xf && instr->dpp16().bank_mask == 0xf); in label_instruction()
2445 new_dpp->row_mask = cmp_dpp.row_mask; in combine_inverse_comparison()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | VOP1Instructions.td | 290 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
838 (i32 (int_amdgcn_mov_dpp i32:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,
841 (as_i32imm $row_mask), (as_i32imm $bank_mask),
846 (i32 (int_amdgcn_update_dpp i32:$old, i32:$src, timm:$dpp_ctrl, timm:$row_mask,
849 (as_i32imm $row_mask), (as_i32imm $bank_mask),
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| D | GCNDPPCombine.cpp | 251 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask)); in createDPPInst()
370 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in combineDPPMov()
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| D | VOP2Instructions.td | 293 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
348 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
362 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
381 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
397 let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
417 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
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| D | SIInstrInfo.td | 1083 def row_mask : NamedOperandU32<"RowMask", NamedMatchClass<"RowMask">>;
1748 (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1754 Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1759 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1768 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1774 row_mask:$row_mask, bank_mask:$bank_mask,
1970 string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
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| D | VOPInstructions.td | 579 bits<4> row_mask;
591 let Inst{63-60} = row_mask;
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| D | SIInstructions.td | 1876 (i64 (int_amdgcn_mov_dpp i64:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,
1879 (as_i32imm $row_mask), (as_i32imm $bank_mask),
1884 (i64 (int_amdgcn_update_dpp i64:$old, i64:$src, timm:$dpp_ctrl, timm:$row_mask,
1887 (as_i32imm $row_mask), (as_i32imm $bank_mask),
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 1525 // llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
1532 // llvm.amdgcn.update.dpp.i32 <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
1535 // v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
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| /third_party/mesa3d/src/amd/llvm/ |
| D | ac_llvm_build.c | 3283 enum dpp_ctrl dpp_ctrl, unsigned row_mask, unsigned bank_mask, in _ac_build_dpp() argument
3295 LLVMConstInt(ctx->i32, row_mask, 0), LLVMConstInt(ctx->i32, bank_mask, 0), in _ac_build_dpp()
3303 enum dpp_ctrl dpp_ctrl, unsigned row_mask, unsigned bank_mask, in ac_build_dpp() argument
3321 _ac_build_dpp(ctx, old, src, dpp_ctrl, row_mask, bank_mask, bound_ctrl); in ac_build_dpp()
3326 ret = _ac_build_dpp(ctx, old, src, dpp_ctrl, row_mask, bank_mask, bound_ctrl); in ac_build_dpp()
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| /third_party/skia/third_party/externals/libpng/ |
| D | pngrutil.c | 3365 static const png_uint_32 row_mask[2/*PACKSWAP*/][3/*depth*/][6] = in png_combine_row() local
3386 row_mask[png][DEPTH_INDEX(depth)][pass]) in png_combine_row()
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