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Searched refs:sdwa (Results 1 – 19 of 19) sorted by relevance

/third_party/mesa3d/src/amd/compiler/tests/
Dtest_sdwa.cpp29 BEGIN_TEST(validate.sdwa.allow)
37 …SDWA_instruction *sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]).… variable
38 sdwa->neg[0] = sdwa->neg[1] = sdwa->abs[0] = sdwa->abs[1] = true;
40 … sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1b), inputs[0], inputs[1]).instr->sdwa();
42 sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]).instr->sdwa();
43 sdwa->sel[0] = SubdwordSel::sbyte2;
44 sdwa->sel[1] = SubdwordSel::uword1;
50 BEGIN_TEST(validate.sdwa.support)
66 BEGIN_TEST(validate.sdwa.operands)
95 BEGIN_TEST(validate.sdwa.vopc)
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/third_party/mesa3d/src/amd/compiler/
Daco_validate.cpp159 SDWA_instruction& sdwa = instr->sdwa(); in validate_ir() local
160 check(sdwa.omod == 0 || program->gfx_level >= GFX9, "SDWA omod only supported on GFX9+", in validate_ir()
163 check(sdwa.clamp == false || program->gfx_level == GFX8, in validate_ir()
172 check(def.bytes() >= sdwa.dst_sel.size() + sdwa.dst_sel.offset(), in validate_ir()
175 sdwa.dst_sel.size() == 1 || sdwa.dst_sel.size() == 2 || sdwa.dst_sel.size() == 4, in validate_ir()
177 check(sdwa.dst_sel.offset() % sdwa.dst_sel.size() == 0, "Invalid selection offset", in validate_ir()
179 check(def.bytes() == 4 || def.bytes() == sdwa.dst_sel.size(), in validate_ir()
182 check(def.bytes() == 4 || sdwa.dst_sel.offset() == 0, in validate_ir()
189 check(op.bytes() >= sdwa.sel[i].size() + sdwa.sel[i].offset(), in validate_ir()
191 check(sdwa.sel[i].size() == 1 || sdwa.sel[i].size() == 2 || sdwa.sel[i].size() == 4, in validate_ir()
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Daco_print_ir.cpp615 const SDWA_instruction& sdwa = instr->sdwa(); in print_instr_format_specific() local
616 switch (sdwa.omod) { in print_instr_format_specific()
621 if (sdwa.clamp) in print_instr_format_specific()
624 char sext = sdwa.dst_sel.sign_extend() ? 's' : 'u'; in print_instr_format_specific()
625 unsigned offset = sdwa.dst_sel.offset(); in print_instr_format_specific()
628 switch (sdwa.dst_sel.size()) { in print_instr_format_specific()
638 char sext = sdwa.sel[i].sign_extend() ? 's' : 'u'; in print_instr_format_specific()
639 unsigned offset = sdwa.sel[i].offset(); in print_instr_format_specific()
642 switch (sdwa.sel[i].size()) { in print_instr_format_specific()
694 const SDWA_instruction& sdwa = instr->sdwa(); in aco_print_instr() local
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Daco_assembler.cpp712 SDWA_instruction& sdwa = instr->sdwa(); in emit_instruction() local
727 encoding |= (sdwa.clamp ? 1 : 0) << 13; in emit_instruction()
729 encoding |= sdwa.dst_sel.to_sdwa_sel(instr->definitions[0].physReg().byte()) << 8; in emit_instruction()
730 uint32_t dst_u = sdwa.dst_sel.sign_extend() ? 1 : 0; in emit_instruction()
734 encoding |= (sdwa.clamp ? 1 : 0) << 13; in emit_instruction()
735 encoding |= sdwa.omod << 14; in emit_instruction()
738 encoding |= sdwa.sel[0].to_sdwa_sel(sdwa_op.physReg().byte()) << 16; in emit_instruction()
739 encoding |= sdwa.sel[0].sign_extend() ? 1 << 19 : 0; in emit_instruction()
740 encoding |= sdwa.abs[0] << 21; in emit_instruction()
741 encoding |= sdwa.neg[0] << 20; in emit_instruction()
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Daco_ir.cpp282 SDWA_instruction& sdwa = instr->sdwa(); in convert_to_SDWA() local
286 memcpy(sdwa.neg, vop3.neg, sizeof(sdwa.neg)); in convert_to_SDWA()
287 memcpy(sdwa.abs, vop3.abs, sizeof(sdwa.abs)); in convert_to_SDWA()
288 sdwa.omod = vop3.omod; in convert_to_SDWA()
289 sdwa.clamp = vop3.clamp; in convert_to_SDWA()
297 sdwa.sel[i] = SubdwordSel(instr->operands[i].bytes(), 0, false); in convert_to_SDWA()
300 sdwa.dst_sel = SubdwordSel(instr->definitions[0].bytes(), 0, false); in convert_to_SDWA()
Daco_lower_to_hw_instr.cpp515 aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>( in emit_reduction() local
517 sdwa->operands[0] = Operand(PhysReg{tmp}, v1); in emit_reduction()
518 sdwa->definitions[0] = Definition(PhysReg{tmp}, v1); in emit_reduction()
520 sdwa->sel[0] = SubdwordSel(1, 0, sext); in emit_reduction()
521 sdwa->dst_sel = SubdwordSel::dword; in emit_reduction()
522 bld.insert(std::move(sdwa)); in emit_reduction()
538 aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>( in emit_reduction() local
540 sdwa->operands[0] = Operand(PhysReg{tmp}, v1); in emit_reduction()
541 sdwa->definitions[0] = Definition(PhysReg{tmp}, v1); in emit_reduction()
543 sdwa->sel[0] = SubdwordSel(2, 0, sext); in emit_reduction()
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Daco_optimizer.cpp1079 if (instr->isSDWA() && instr->sdwa().sel[idx] != SubdwordSel::dword) in can_apply_extract()
1341 can_use_mod = can_use_mod && instr->sdwa().sel[i].size() == 4; in label_instruction()
1361 else if (instr->isSDWA() && !instr->sdwa().abs[i]) in label_instruction()
1362 instr->sdwa().neg[i] = true; in label_instruction()
1374 instr->sdwa().abs[i] = true; in label_instruction()
2430 SDWA_instruction& cmp_sdwa = cmp->sdwa(); in combine_inverse_comparison()
3207 if (!apply_omod_clamp_helper(ctx, &instr->sdwa(), def_info)) in apply_omod_clamp()
3252 if (instr->sdwa().dst_sel.size() != 4) in apply_insert()
3639 vop3p->neg_lo[is_add + i] |= instr->isSDWA() && instr->sdwa().neg[i]; in to_mad_mix()
3641 vop3p->neg_hi[is_add + i] |= instr->isSDWA() && instr->sdwa().abs[i]; in to_mad_mix()
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Daco_opt_value_numbering.cpp194 SDWA_instruction& aSDWA = a->sdwa(); in operator ()()
195 SDWA_instruction& bSDWA = b->sdwa(); in operator ()()
Daco_ir.h1326 SDWA_instruction& sdwa() noexcept in sdwa() function
1331 const SDWA_instruction& sdwa() const noexcept in sdwa() function
Daco_instruction_selection.cpp12272 instr->sdwa().sel[0] = SubdwordSel::ubyte1; in calc_nontrivial_instance_id()
12279 instr->sdwa().sel[0] = SubdwordSel::ubyte2; in calc_nontrivial_instance_id()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPU.td311 def FeatureSDWA : SubtargetFeature<"sdwa",
317 def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
323 def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
329 def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
335 def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
341 def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
DVOP1Instructions.td26 let Inst{8-0} = 0xf9; // sdwa
35 let Inst{8-0} = 0xf9; // sdwa
DSIInstrInfo.td2008 string sdwa = !if(!eq(NumSrcArgs, 0),
2018 string ret = dst#args#sdwa;
2037 string sdwa = !if(!eq(NumSrcArgs, 0), "",
2046 string ret = dst#args#sdwa;
DVOPCInstructions.td26 let Inst{8-0} = 0xf9; // sdwa
39 let Inst{8-0} = 0xf9; // sdwa
DVOP2Instructions.td43 let Inst{8-0} = 0xf9; // sdwa
54 let Inst{8-0} = 0xf9; // sdwa
/third_party/mesa3d/docs/relnotes/
D20.1.0.rst3551 - aco: add emission support for register-allocated sdwa sels
D20.3.0.rst4110 - aco: fix printing of some sdwa sels
D20.2.0.rst3848 - aco: fix sub-dword opsel/sdwa checks
D22.2.0.rst5207 - aco: disable sdwa on gfx11