1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC 4 * 5 * Copyright (C) 2018-2019 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a774c0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a774c0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cluster1_opp: opp_table10 { 48 compatible = "operating-points-v2"; 49 opp-shared; 50 opp-800000000 { 51 opp-hz = /bits/ 64 <800000000>; 52 clock-latency-ns = <300000>; 53 }; 54 opp-1000000000 { 55 opp-hz = /bits/ 64 <1000000000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1200000000 { 59 opp-hz = /bits/ 64 <1200000000>; 60 clock-latency-ns = <300000>; 61 opp-suspend; 62 }; 63 }; 64 65 cpus { 66 #address-cells = <1>; 67 #size-cells = <0>; 68 69 a53_0: cpu@0 { 70 compatible = "arm,cortex-a53"; 71 reg = <0>; 72 device_type = "cpu"; 73 #cooling-cells = <2>; 74 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; 75 next-level-cache = <&L2_CA53>; 76 enable-method = "psci"; 77 dynamic-power-coefficient = <277>; 78 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 79 operating-points-v2 = <&cluster1_opp>; 80 }; 81 82 a53_1: cpu@1 { 83 compatible = "arm,cortex-a53"; 84 reg = <1>; 85 device_type = "cpu"; 86 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; 87 next-level-cache = <&L2_CA53>; 88 enable-method = "psci"; 89 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 90 operating-points-v2 = <&cluster1_opp>; 91 }; 92 93 L2_CA53: cache-controller-0 { 94 compatible = "cache"; 95 power-domains = <&sysc R8A774C0_PD_CA53_SCU>; 96 cache-unified; 97 cache-level = <2>; 98 }; 99 }; 100 101 extal_clk: extal { 102 compatible = "fixed-clock"; 103 #clock-cells = <0>; 104 /* This value must be overridden by the board */ 105 clock-frequency = <0>; 106 }; 107 108 /* External PCIe clock - can be overridden by the board */ 109 pcie_bus_clk: pcie_bus { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <0>; 113 }; 114 115 pmu_a53 { 116 compatible = "arm,cortex-a53-pmu"; 117 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 118 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 119 interrupt-affinity = <&a53_0>, <&a53_1>; 120 }; 121 122 psci { 123 compatible = "arm,psci-1.0", "arm,psci-0.2"; 124 method = "smc"; 125 }; 126 127 /* External SCIF clock - to be overridden by boards that provide it */ 128 scif_clk: scif { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 clock-frequency = <0>; 132 }; 133 134 soc: soc { 135 compatible = "simple-bus"; 136 interrupt-parent = <&gic>; 137 #address-cells = <2>; 138 #size-cells = <2>; 139 ranges; 140 141 rwdt: watchdog@e6020000 { 142 compatible = "renesas,r8a774c0-wdt", 143 "renesas,rcar-gen3-wdt"; 144 reg = <0 0xe6020000 0 0x0c>; 145 clocks = <&cpg CPG_MOD 402>; 146 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 147 resets = <&cpg 402>; 148 status = "disabled"; 149 }; 150 151 gpio0: gpio@e6050000 { 152 compatible = "renesas,gpio-r8a774c0", 153 "renesas,rcar-gen3-gpio"; 154 reg = <0 0xe6050000 0 0x50>; 155 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 156 #gpio-cells = <2>; 157 gpio-controller; 158 gpio-ranges = <&pfc 0 0 18>; 159 #interrupt-cells = <2>; 160 interrupt-controller; 161 clocks = <&cpg CPG_MOD 912>; 162 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 163 resets = <&cpg 912>; 164 }; 165 166 gpio1: gpio@e6051000 { 167 compatible = "renesas,gpio-r8a774c0", 168 "renesas,rcar-gen3-gpio"; 169 reg = <0 0xe6051000 0 0x50>; 170 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 171 #gpio-cells = <2>; 172 gpio-controller; 173 gpio-ranges = <&pfc 0 32 23>; 174 #interrupt-cells = <2>; 175 interrupt-controller; 176 clocks = <&cpg CPG_MOD 911>; 177 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 178 resets = <&cpg 911>; 179 }; 180 181 gpio2: gpio@e6052000 { 182 compatible = "renesas,gpio-r8a774c0", 183 "renesas,rcar-gen3-gpio"; 184 reg = <0 0xe6052000 0 0x50>; 185 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 186 #gpio-cells = <2>; 187 gpio-controller; 188 gpio-ranges = <&pfc 0 64 26>; 189 #interrupt-cells = <2>; 190 interrupt-controller; 191 clocks = <&cpg CPG_MOD 910>; 192 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 193 resets = <&cpg 910>; 194 }; 195 196 gpio3: gpio@e6053000 { 197 compatible = "renesas,gpio-r8a774c0", 198 "renesas,rcar-gen3-gpio"; 199 reg = <0 0xe6053000 0 0x50>; 200 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 201 #gpio-cells = <2>; 202 gpio-controller; 203 gpio-ranges = <&pfc 0 96 16>; 204 #interrupt-cells = <2>; 205 interrupt-controller; 206 clocks = <&cpg CPG_MOD 909>; 207 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 208 resets = <&cpg 909>; 209 }; 210 211 gpio4: gpio@e6054000 { 212 compatible = "renesas,gpio-r8a774c0", 213 "renesas,rcar-gen3-gpio"; 214 reg = <0 0xe6054000 0 0x50>; 215 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 216 #gpio-cells = <2>; 217 gpio-controller; 218 gpio-ranges = <&pfc 0 128 11>; 219 #interrupt-cells = <2>; 220 interrupt-controller; 221 clocks = <&cpg CPG_MOD 908>; 222 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 223 resets = <&cpg 908>; 224 }; 225 226 gpio5: gpio@e6055000 { 227 compatible = "renesas,gpio-r8a774c0", 228 "renesas,rcar-gen3-gpio"; 229 reg = <0 0xe6055000 0 0x50>; 230 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 231 #gpio-cells = <2>; 232 gpio-controller; 233 gpio-ranges = <&pfc 0 160 20>; 234 #interrupt-cells = <2>; 235 interrupt-controller; 236 clocks = <&cpg CPG_MOD 907>; 237 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 238 resets = <&cpg 907>; 239 }; 240 241 gpio6: gpio@e6055400 { 242 compatible = "renesas,gpio-r8a774c0", 243 "renesas,rcar-gen3-gpio"; 244 reg = <0 0xe6055400 0 0x50>; 245 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 246 #gpio-cells = <2>; 247 gpio-controller; 248 gpio-ranges = <&pfc 0 192 18>; 249 #interrupt-cells = <2>; 250 interrupt-controller; 251 clocks = <&cpg CPG_MOD 906>; 252 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 253 resets = <&cpg 906>; 254 }; 255 256 pfc: pinctrl@e6060000 { 257 compatible = "renesas,pfc-r8a774c0"; 258 reg = <0 0xe6060000 0 0x508>; 259 }; 260 261 cmt0: timer@e60f0000 { 262 compatible = "renesas,r8a774c0-cmt0", 263 "renesas,rcar-gen3-cmt0"; 264 reg = <0 0xe60f0000 0 0x1004>; 265 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cpg CPG_MOD 303>; 268 clock-names = "fck"; 269 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 270 resets = <&cpg 303>; 271 status = "disabled"; 272 }; 273 274 cmt1: timer@e6130000 { 275 compatible = "renesas,r8a774c0-cmt1", 276 "renesas,rcar-gen3-cmt1"; 277 reg = <0 0xe6130000 0 0x1004>; 278 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cpg CPG_MOD 302>; 287 clock-names = "fck"; 288 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 289 resets = <&cpg 302>; 290 status = "disabled"; 291 }; 292 293 cmt2: timer@e6140000 { 294 compatible = "renesas,r8a774c0-cmt1", 295 "renesas,rcar-gen3-cmt1"; 296 reg = <0 0xe6140000 0 0x1004>; 297 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&cpg CPG_MOD 301>; 306 clock-names = "fck"; 307 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 308 resets = <&cpg 301>; 309 status = "disabled"; 310 }; 311 312 cmt3: timer@e6148000 { 313 compatible = "renesas,r8a774c0-cmt1", 314 "renesas,rcar-gen3-cmt1"; 315 reg = <0 0xe6148000 0 0x1004>; 316 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&cpg CPG_MOD 300>; 325 clock-names = "fck"; 326 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 327 resets = <&cpg 300>; 328 status = "disabled"; 329 }; 330 331 cpg: clock-controller@e6150000 { 332 compatible = "renesas,r8a774c0-cpg-mssr"; 333 reg = <0 0xe6150000 0 0x1000>; 334 clocks = <&extal_clk>; 335 clock-names = "extal"; 336 #clock-cells = <2>; 337 #power-domain-cells = <0>; 338 #reset-cells = <1>; 339 }; 340 341 rst: reset-controller@e6160000 { 342 compatible = "renesas,r8a774c0-rst"; 343 reg = <0 0xe6160000 0 0x0200>; 344 }; 345 346 sysc: system-controller@e6180000 { 347 compatible = "renesas,r8a774c0-sysc"; 348 reg = <0 0xe6180000 0 0x0400>; 349 #power-domain-cells = <1>; 350 }; 351 352 thermal: thermal@e6190000 { 353 compatible = "renesas,thermal-r8a774c0"; 354 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 355 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&cpg CPG_MOD 522>; 359 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 360 resets = <&cpg 522>; 361 #thermal-sensor-cells = <0>; 362 }; 363 364 intc_ex: interrupt-controller@e61c0000 { 365 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; 366 #interrupt-cells = <2>; 367 interrupt-controller; 368 reg = <0 0xe61c0000 0 0x200>; 369 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cpg CPG_MOD 407>; 376 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 377 resets = <&cpg 407>; 378 }; 379 380 tmu0: timer@e61e0000 { 381 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 382 reg = <0 0xe61e0000 0 0x30>; 383 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&cpg CPG_MOD 125>; 387 clock-names = "fck"; 388 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 389 resets = <&cpg 125>; 390 status = "disabled"; 391 }; 392 393 tmu1: timer@e6fc0000 { 394 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 395 reg = <0 0xe6fc0000 0 0x30>; 396 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&cpg CPG_MOD 124>; 400 clock-names = "fck"; 401 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 402 resets = <&cpg 124>; 403 status = "disabled"; 404 }; 405 406 tmu2: timer@e6fd0000 { 407 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 408 reg = <0 0xe6fd0000 0 0x30>; 409 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&cpg CPG_MOD 123>; 413 clock-names = "fck"; 414 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 415 resets = <&cpg 123>; 416 status = "disabled"; 417 }; 418 419 tmu3: timer@e6fe0000 { 420 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 421 reg = <0 0xe6fe0000 0 0x30>; 422 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&cpg CPG_MOD 122>; 426 clock-names = "fck"; 427 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 428 resets = <&cpg 122>; 429 status = "disabled"; 430 }; 431 432 tmu4: timer@ffc00000 { 433 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 434 reg = <0 0xffc00000 0 0x30>; 435 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cpg CPG_MOD 121>; 439 clock-names = "fck"; 440 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 441 resets = <&cpg 121>; 442 status = "disabled"; 443 }; 444 445 i2c0: i2c@e6500000 { 446 #address-cells = <1>; 447 #size-cells = <0>; 448 compatible = "renesas,i2c-r8a774c0", 449 "renesas,rcar-gen3-i2c"; 450 reg = <0 0xe6500000 0 0x40>; 451 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cpg CPG_MOD 931>; 453 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 454 resets = <&cpg 931>; 455 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 456 <&dmac2 0x91>, <&dmac2 0x90>; 457 dma-names = "tx", "rx", "tx", "rx"; 458 i2c-scl-internal-delay-ns = <110>; 459 status = "disabled"; 460 }; 461 462 i2c1: i2c@e6508000 { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 compatible = "renesas,i2c-r8a774c0", 466 "renesas,rcar-gen3-i2c"; 467 reg = <0 0xe6508000 0 0x40>; 468 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&cpg CPG_MOD 930>; 470 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 471 resets = <&cpg 930>; 472 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 473 <&dmac2 0x93>, <&dmac2 0x92>; 474 dma-names = "tx", "rx", "tx", "rx"; 475 i2c-scl-internal-delay-ns = <6>; 476 status = "disabled"; 477 }; 478 479 i2c2: i2c@e6510000 { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 compatible = "renesas,i2c-r8a774c0", 483 "renesas,rcar-gen3-i2c"; 484 reg = <0 0xe6510000 0 0x40>; 485 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&cpg CPG_MOD 929>; 487 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 488 resets = <&cpg 929>; 489 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 490 <&dmac2 0x95>, <&dmac2 0x94>; 491 dma-names = "tx", "rx", "tx", "rx"; 492 i2c-scl-internal-delay-ns = <6>; 493 status = "disabled"; 494 }; 495 496 i2c3: i2c@e66d0000 { 497 #address-cells = <1>; 498 #size-cells = <0>; 499 compatible = "renesas,i2c-r8a774c0", 500 "renesas,rcar-gen3-i2c"; 501 reg = <0 0xe66d0000 0 0x40>; 502 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cpg CPG_MOD 928>; 504 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 505 resets = <&cpg 928>; 506 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 507 dma-names = "tx", "rx"; 508 i2c-scl-internal-delay-ns = <110>; 509 status = "disabled"; 510 }; 511 512 i2c4: i2c@e66d8000 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 compatible = "renesas,i2c-r8a774c0", 516 "renesas,rcar-gen3-i2c"; 517 reg = <0 0xe66d8000 0 0x40>; 518 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&cpg CPG_MOD 927>; 520 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 521 resets = <&cpg 927>; 522 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 523 dma-names = "tx", "rx"; 524 i2c-scl-internal-delay-ns = <6>; 525 status = "disabled"; 526 }; 527 528 i2c5: i2c@e66e0000 { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 compatible = "renesas,i2c-r8a774c0", 532 "renesas,rcar-gen3-i2c"; 533 reg = <0 0xe66e0000 0 0x40>; 534 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&cpg CPG_MOD 919>; 536 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 537 resets = <&cpg 919>; 538 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 539 dma-names = "tx", "rx"; 540 i2c-scl-internal-delay-ns = <6>; 541 status = "disabled"; 542 }; 543 544 i2c6: i2c@e66e8000 { 545 #address-cells = <1>; 546 #size-cells = <0>; 547 compatible = "renesas,i2c-r8a774c0", 548 "renesas,rcar-gen3-i2c"; 549 reg = <0 0xe66e8000 0 0x40>; 550 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cpg CPG_MOD 918>; 552 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 553 resets = <&cpg 918>; 554 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 555 dma-names = "tx", "rx"; 556 i2c-scl-internal-delay-ns = <6>; 557 status = "disabled"; 558 }; 559 560 i2c7: i2c@e6690000 { 561 #address-cells = <1>; 562 #size-cells = <0>; 563 compatible = "renesas,i2c-r8a774c0", 564 "renesas,rcar-gen3-i2c"; 565 reg = <0 0xe6690000 0 0x40>; 566 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&cpg CPG_MOD 1003>; 568 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 569 resets = <&cpg 1003>; 570 i2c-scl-internal-delay-ns = <6>; 571 status = "disabled"; 572 }; 573 574 i2c_dvfs: i2c@e60b0000 { 575 #address-cells = <1>; 576 #size-cells = <0>; 577 compatible = "renesas,iic-r8a774c0"; 578 reg = <0 0xe60b0000 0 0x15>; 579 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&cpg CPG_MOD 926>; 581 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 582 resets = <&cpg 926>; 583 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 584 dma-names = "tx", "rx"; 585 status = "disabled"; 586 }; 587 588 hscif0: serial@e6540000 { 589 compatible = "renesas,hscif-r8a774c0", 590 "renesas,rcar-gen3-hscif", 591 "renesas,hscif"; 592 reg = <0 0xe6540000 0 0x60>; 593 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&cpg CPG_MOD 520>, 595 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 596 <&scif_clk>; 597 clock-names = "fck", "brg_int", "scif_clk"; 598 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 599 <&dmac2 0x31>, <&dmac2 0x30>; 600 dma-names = "tx", "rx", "tx", "rx"; 601 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 602 resets = <&cpg 520>; 603 status = "disabled"; 604 }; 605 606 hscif1: serial@e6550000 { 607 compatible = "renesas,hscif-r8a774c0", 608 "renesas,rcar-gen3-hscif", 609 "renesas,hscif"; 610 reg = <0 0xe6550000 0 0x60>; 611 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&cpg CPG_MOD 519>, 613 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 614 <&scif_clk>; 615 clock-names = "fck", "brg_int", "scif_clk"; 616 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 617 <&dmac2 0x33>, <&dmac2 0x32>; 618 dma-names = "tx", "rx", "tx", "rx"; 619 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 620 resets = <&cpg 519>; 621 status = "disabled"; 622 }; 623 624 hscif2: serial@e6560000 { 625 compatible = "renesas,hscif-r8a774c0", 626 "renesas,rcar-gen3-hscif", 627 "renesas,hscif"; 628 reg = <0 0xe6560000 0 0x60>; 629 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&cpg CPG_MOD 518>, 631 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 632 <&scif_clk>; 633 clock-names = "fck", "brg_int", "scif_clk"; 634 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 635 <&dmac2 0x35>, <&dmac2 0x34>; 636 dma-names = "tx", "rx", "tx", "rx"; 637 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 638 resets = <&cpg 518>; 639 status = "disabled"; 640 }; 641 642 hscif3: serial@e66a0000 { 643 compatible = "renesas,hscif-r8a774c0", 644 "renesas,rcar-gen3-hscif", 645 "renesas,hscif"; 646 reg = <0 0xe66a0000 0 0x60>; 647 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&cpg CPG_MOD 517>, 649 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 650 <&scif_clk>; 651 clock-names = "fck", "brg_int", "scif_clk"; 652 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 653 dma-names = "tx", "rx"; 654 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 655 resets = <&cpg 517>; 656 status = "disabled"; 657 }; 658 659 hscif4: serial@e66b0000 { 660 compatible = "renesas,hscif-r8a774c0", 661 "renesas,rcar-gen3-hscif", 662 "renesas,hscif"; 663 reg = <0 0xe66b0000 0 0x60>; 664 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&cpg CPG_MOD 516>, 666 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 667 <&scif_clk>; 668 clock-names = "fck", "brg_int", "scif_clk"; 669 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 670 dma-names = "tx", "rx"; 671 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 672 resets = <&cpg 516>; 673 status = "disabled"; 674 }; 675 676 hsusb: usb@e6590000 { 677 compatible = "renesas,usbhs-r8a774c0", 678 "renesas,rcar-gen3-usbhs"; 679 reg = <0 0xe6590000 0 0x200>; 680 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 682 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 683 <&usb_dmac1 0>, <&usb_dmac1 1>; 684 dma-names = "ch0", "ch1", "ch2", "ch3"; 685 renesas,buswait = <11>; 686 phys = <&usb2_phy0 3>; 687 phy-names = "usb"; 688 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 689 resets = <&cpg 704>, <&cpg 703>; 690 status = "disabled"; 691 }; 692 693 usb_dmac0: dma-controller@e65a0000 { 694 compatible = "renesas,r8a774c0-usb-dmac", 695 "renesas,usb-dmac"; 696 reg = <0 0xe65a0000 0 0x100>; 697 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 699 interrupt-names = "ch0", "ch1"; 700 clocks = <&cpg CPG_MOD 330>; 701 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 702 resets = <&cpg 330>; 703 #dma-cells = <1>; 704 dma-channels = <2>; 705 }; 706 707 usb_dmac1: dma-controller@e65b0000 { 708 compatible = "renesas,r8a774c0-usb-dmac", 709 "renesas,usb-dmac"; 710 reg = <0 0xe65b0000 0 0x100>; 711 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 713 interrupt-names = "ch0", "ch1"; 714 clocks = <&cpg CPG_MOD 331>; 715 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 716 resets = <&cpg 331>; 717 #dma-cells = <1>; 718 dma-channels = <2>; 719 }; 720 721 dmac0: dma-controller@e6700000 { 722 compatible = "renesas,dmac-r8a774c0", 723 "renesas,rcar-dmac"; 724 reg = <0 0xe6700000 0 0x10000>; 725 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 742 interrupt-names = "error", 743 "ch0", "ch1", "ch2", "ch3", 744 "ch4", "ch5", "ch6", "ch7", 745 "ch8", "ch9", "ch10", "ch11", 746 "ch12", "ch13", "ch14", "ch15"; 747 clocks = <&cpg CPG_MOD 219>; 748 clock-names = "fck"; 749 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 750 resets = <&cpg 219>; 751 #dma-cells = <1>; 752 dma-channels = <16>; 753 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 754 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 755 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 756 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 757 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 758 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 759 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 760 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 761 }; 762 763 dmac1: dma-controller@e7300000 { 764 compatible = "renesas,dmac-r8a774c0", 765 "renesas,rcar-dmac"; 766 reg = <0 0xe7300000 0 0x10000>; 767 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 784 interrupt-names = "error", 785 "ch0", "ch1", "ch2", "ch3", 786 "ch4", "ch5", "ch6", "ch7", 787 "ch8", "ch9", "ch10", "ch11", 788 "ch12", "ch13", "ch14", "ch15"; 789 clocks = <&cpg CPG_MOD 218>; 790 clock-names = "fck"; 791 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 792 resets = <&cpg 218>; 793 #dma-cells = <1>; 794 dma-channels = <16>; 795 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 796 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 797 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 798 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 799 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 800 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 801 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 802 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 803 }; 804 805 dmac2: dma-controller@e7310000 { 806 compatible = "renesas,dmac-r8a774c0", 807 "renesas,rcar-dmac"; 808 reg = <0 0xe7310000 0 0x10000>; 809 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 826 interrupt-names = "error", 827 "ch0", "ch1", "ch2", "ch3", 828 "ch4", "ch5", "ch6", "ch7", 829 "ch8", "ch9", "ch10", "ch11", 830 "ch12", "ch13", "ch14", "ch15"; 831 clocks = <&cpg CPG_MOD 217>; 832 clock-names = "fck"; 833 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 834 resets = <&cpg 217>; 835 #dma-cells = <1>; 836 dma-channels = <16>; 837 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 838 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 839 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 840 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 841 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 842 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 843 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 844 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 845 }; 846 847 ipmmu_ds0: iommu@e6740000 { 848 compatible = "renesas,ipmmu-r8a774c0"; 849 reg = <0 0xe6740000 0 0x1000>; 850 renesas,ipmmu-main = <&ipmmu_mm 0>; 851 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 852 #iommu-cells = <1>; 853 }; 854 855 ipmmu_ds1: iommu@e7740000 { 856 compatible = "renesas,ipmmu-r8a774c0"; 857 reg = <0 0xe7740000 0 0x1000>; 858 renesas,ipmmu-main = <&ipmmu_mm 1>; 859 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 860 #iommu-cells = <1>; 861 }; 862 863 ipmmu_hc: iommu@e6570000 { 864 compatible = "renesas,ipmmu-r8a774c0"; 865 reg = <0 0xe6570000 0 0x1000>; 866 renesas,ipmmu-main = <&ipmmu_mm 2>; 867 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 868 #iommu-cells = <1>; 869 }; 870 871 ipmmu_mm: iommu@e67b0000 { 872 compatible = "renesas,ipmmu-r8a774c0"; 873 reg = <0 0xe67b0000 0 0x1000>; 874 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 876 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 877 #iommu-cells = <1>; 878 }; 879 880 ipmmu_mp: iommu@ec670000 { 881 compatible = "renesas,ipmmu-r8a774c0"; 882 reg = <0 0xec670000 0 0x1000>; 883 renesas,ipmmu-main = <&ipmmu_mm 4>; 884 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 885 #iommu-cells = <1>; 886 }; 887 888 ipmmu_pv0: iommu@fd800000 { 889 compatible = "renesas,ipmmu-r8a774c0"; 890 reg = <0 0xfd800000 0 0x1000>; 891 renesas,ipmmu-main = <&ipmmu_mm 6>; 892 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 893 #iommu-cells = <1>; 894 }; 895 896 ipmmu_vc0: iommu@fe6b0000 { 897 compatible = "renesas,ipmmu-r8a774c0"; 898 reg = <0 0xfe6b0000 0 0x1000>; 899 renesas,ipmmu-main = <&ipmmu_mm 12>; 900 power-domains = <&sysc R8A774C0_PD_A3VC>; 901 #iommu-cells = <1>; 902 }; 903 904 ipmmu_vi0: iommu@febd0000 { 905 compatible = "renesas,ipmmu-r8a774c0"; 906 reg = <0 0xfebd0000 0 0x1000>; 907 renesas,ipmmu-main = <&ipmmu_mm 14>; 908 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 909 #iommu-cells = <1>; 910 }; 911 912 ipmmu_vp0: iommu@fe990000 { 913 compatible = "renesas,ipmmu-r8a774c0"; 914 reg = <0 0xfe990000 0 0x1000>; 915 renesas,ipmmu-main = <&ipmmu_mm 16>; 916 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 917 #iommu-cells = <1>; 918 }; 919 920 avb: ethernet@e6800000 { 921 compatible = "renesas,etheravb-r8a774c0", 922 "renesas,etheravb-rcar-gen3"; 923 reg = <0 0xe6800000 0 0x800>; 924 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "ch0", "ch1", "ch2", "ch3", 950 "ch4", "ch5", "ch6", "ch7", 951 "ch8", "ch9", "ch10", "ch11", 952 "ch12", "ch13", "ch14", "ch15", 953 "ch16", "ch17", "ch18", "ch19", 954 "ch20", "ch21", "ch22", "ch23", 955 "ch24"; 956 clocks = <&cpg CPG_MOD 812>; 957 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 958 resets = <&cpg 812>; 959 phy-mode = "rgmii"; 960 rx-internal-delay-ps = <0>; 961 iommus = <&ipmmu_ds0 16>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 can0: can@e6c30000 { 968 compatible = "renesas,can-r8a774c0", 969 "renesas,rcar-gen3-can"; 970 reg = <0 0xe6c30000 0 0x1000>; 971 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&cpg CPG_MOD 916>, 973 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 974 <&can_clk>; 975 clock-names = "clkp1", "clkp2", "can_clk"; 976 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 977 assigned-clock-rates = <40000000>; 978 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 979 resets = <&cpg 916>; 980 status = "disabled"; 981 }; 982 983 can1: can@e6c38000 { 984 compatible = "renesas,can-r8a774c0", 985 "renesas,rcar-gen3-can"; 986 reg = <0 0xe6c38000 0 0x1000>; 987 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&cpg CPG_MOD 915>, 989 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 990 <&can_clk>; 991 clock-names = "clkp1", "clkp2", "can_clk"; 992 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 993 assigned-clock-rates = <40000000>; 994 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 995 resets = <&cpg 915>; 996 status = "disabled"; 997 }; 998 999 canfd: can@e66c0000 { 1000 compatible = "renesas,r8a774c0-canfd", 1001 "renesas,rcar-gen3-canfd"; 1002 reg = <0 0xe66c0000 0 0x8000>; 1003 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&cpg CPG_MOD 914>, 1006 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 1007 <&can_clk>; 1008 clock-names = "fck", "canfd", "can_clk"; 1009 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 1010 assigned-clock-rates = <40000000>; 1011 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1012 resets = <&cpg 914>; 1013 status = "disabled"; 1014 1015 channel0 { 1016 status = "disabled"; 1017 }; 1018 1019 channel1 { 1020 status = "disabled"; 1021 }; 1022 }; 1023 1024 pwm0: pwm@e6e30000 { 1025 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1026 reg = <0 0xe6e30000 0 0x8>; 1027 clocks = <&cpg CPG_MOD 523>; 1028 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1029 resets = <&cpg 523>; 1030 #pwm-cells = <2>; 1031 status = "disabled"; 1032 }; 1033 1034 pwm1: pwm@e6e31000 { 1035 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1036 reg = <0 0xe6e31000 0 0x8>; 1037 clocks = <&cpg CPG_MOD 523>; 1038 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1039 resets = <&cpg 523>; 1040 #pwm-cells = <2>; 1041 status = "disabled"; 1042 }; 1043 1044 pwm2: pwm@e6e32000 { 1045 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1046 reg = <0 0xe6e32000 0 0x8>; 1047 clocks = <&cpg CPG_MOD 523>; 1048 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1049 resets = <&cpg 523>; 1050 #pwm-cells = <2>; 1051 status = "disabled"; 1052 }; 1053 1054 pwm3: pwm@e6e33000 { 1055 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1056 reg = <0 0xe6e33000 0 0x8>; 1057 clocks = <&cpg CPG_MOD 523>; 1058 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1059 resets = <&cpg 523>; 1060 #pwm-cells = <2>; 1061 status = "disabled"; 1062 }; 1063 1064 pwm4: pwm@e6e34000 { 1065 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1066 reg = <0 0xe6e34000 0 0x8>; 1067 clocks = <&cpg CPG_MOD 523>; 1068 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1069 resets = <&cpg 523>; 1070 #pwm-cells = <2>; 1071 status = "disabled"; 1072 }; 1073 1074 pwm5: pwm@e6e35000 { 1075 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1076 reg = <0 0xe6e35000 0 0x8>; 1077 clocks = <&cpg CPG_MOD 523>; 1078 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1079 resets = <&cpg 523>; 1080 #pwm-cells = <2>; 1081 status = "disabled"; 1082 }; 1083 1084 pwm6: pwm@e6e36000 { 1085 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1086 reg = <0 0xe6e36000 0 0x8>; 1087 clocks = <&cpg CPG_MOD 523>; 1088 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1089 resets = <&cpg 523>; 1090 #pwm-cells = <2>; 1091 status = "disabled"; 1092 }; 1093 1094 scif0: serial@e6e60000 { 1095 compatible = "renesas,scif-r8a774c0", 1096 "renesas,rcar-gen3-scif", "renesas,scif"; 1097 reg = <0 0xe6e60000 0 64>; 1098 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&cpg CPG_MOD 207>, 1100 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1101 <&scif_clk>; 1102 clock-names = "fck", "brg_int", "scif_clk"; 1103 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1104 <&dmac2 0x51>, <&dmac2 0x50>; 1105 dma-names = "tx", "rx", "tx", "rx"; 1106 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1107 resets = <&cpg 207>; 1108 status = "disabled"; 1109 }; 1110 1111 scif1: serial@e6e68000 { 1112 compatible = "renesas,scif-r8a774c0", 1113 "renesas,rcar-gen3-scif", "renesas,scif"; 1114 reg = <0 0xe6e68000 0 64>; 1115 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&cpg CPG_MOD 206>, 1117 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1118 <&scif_clk>; 1119 clock-names = "fck", "brg_int", "scif_clk"; 1120 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1121 <&dmac2 0x53>, <&dmac2 0x52>; 1122 dma-names = "tx", "rx", "tx", "rx"; 1123 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1124 resets = <&cpg 206>; 1125 status = "disabled"; 1126 }; 1127 1128 scif2: serial@e6e88000 { 1129 compatible = "renesas,scif-r8a774c0", 1130 "renesas,rcar-gen3-scif", "renesas,scif"; 1131 reg = <0 0xe6e88000 0 64>; 1132 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&cpg CPG_MOD 310>, 1134 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1135 <&scif_clk>; 1136 clock-names = "fck", "brg_int", "scif_clk"; 1137 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1138 <&dmac2 0x13>, <&dmac2 0x12>; 1139 dma-names = "tx", "rx", "tx", "rx"; 1140 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1141 resets = <&cpg 310>; 1142 status = "disabled"; 1143 }; 1144 1145 scif3: serial@e6c50000 { 1146 compatible = "renesas,scif-r8a774c0", 1147 "renesas,rcar-gen3-scif", "renesas,scif"; 1148 reg = <0 0xe6c50000 0 64>; 1149 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&cpg CPG_MOD 204>, 1151 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1152 <&scif_clk>; 1153 clock-names = "fck", "brg_int", "scif_clk"; 1154 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1155 dma-names = "tx", "rx"; 1156 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1157 resets = <&cpg 204>; 1158 status = "disabled"; 1159 }; 1160 1161 scif4: serial@e6c40000 { 1162 compatible = "renesas,scif-r8a774c0", 1163 "renesas,rcar-gen3-scif", "renesas,scif"; 1164 reg = <0 0xe6c40000 0 64>; 1165 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1166 clocks = <&cpg CPG_MOD 203>, 1167 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1168 <&scif_clk>; 1169 clock-names = "fck", "brg_int", "scif_clk"; 1170 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1171 dma-names = "tx", "rx"; 1172 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1173 resets = <&cpg 203>; 1174 status = "disabled"; 1175 }; 1176 1177 scif5: serial@e6f30000 { 1178 compatible = "renesas,scif-r8a774c0", 1179 "renesas,rcar-gen3-scif", "renesas,scif"; 1180 reg = <0 0xe6f30000 0 64>; 1181 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&cpg CPG_MOD 202>, 1183 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1184 <&scif_clk>; 1185 clock-names = "fck", "brg_int", "scif_clk"; 1186 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; 1187 dma-names = "tx", "rx"; 1188 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1189 resets = <&cpg 202>; 1190 status = "disabled"; 1191 }; 1192 1193 msiof0: spi@e6e90000 { 1194 compatible = "renesas,msiof-r8a774c0", 1195 "renesas,rcar-gen3-msiof"; 1196 reg = <0 0xe6e90000 0 0x0064>; 1197 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&cpg CPG_MOD 211>; 1199 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1200 <&dmac2 0x41>, <&dmac2 0x40>; 1201 dma-names = "tx", "rx", "tx", "rx"; 1202 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1203 resets = <&cpg 211>; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 status = "disabled"; 1207 }; 1208 1209 msiof1: spi@e6ea0000 { 1210 compatible = "renesas,msiof-r8a774c0", 1211 "renesas,rcar-gen3-msiof"; 1212 reg = <0 0xe6ea0000 0 0x0064>; 1213 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1214 clocks = <&cpg CPG_MOD 210>; 1215 dmas = <&dmac0 0x43>, <&dmac0 0x42>; 1216 dma-names = "tx", "rx"; 1217 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1218 resets = <&cpg 210>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 status = "disabled"; 1222 }; 1223 1224 msiof2: spi@e6c00000 { 1225 compatible = "renesas,msiof-r8a774c0", 1226 "renesas,rcar-gen3-msiof"; 1227 reg = <0 0xe6c00000 0 0x0064>; 1228 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&cpg CPG_MOD 209>; 1230 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1231 dma-names = "tx", "rx"; 1232 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1233 resets = <&cpg 209>; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 status = "disabled"; 1237 }; 1238 1239 msiof3: spi@e6c10000 { 1240 compatible = "renesas,msiof-r8a774c0", 1241 "renesas,rcar-gen3-msiof"; 1242 reg = <0 0xe6c10000 0 0x0064>; 1243 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1244 clocks = <&cpg CPG_MOD 208>; 1245 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1246 dma-names = "tx", "rx"; 1247 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1248 resets = <&cpg 208>; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 status = "disabled"; 1252 }; 1253 1254 vin4: video@e6ef4000 { 1255 compatible = "renesas,vin-r8a774c0"; 1256 reg = <0 0xe6ef4000 0 0x1000>; 1257 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1258 clocks = <&cpg CPG_MOD 807>; 1259 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1260 resets = <&cpg 807>; 1261 renesas,id = <4>; 1262 status = "disabled"; 1263 1264 ports { 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 1268 port@1 { 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 1272 reg = <1>; 1273 1274 vin4csi40: endpoint@2 { 1275 reg = <2>; 1276 remote-endpoint= <&csi40vin4>; 1277 }; 1278 }; 1279 }; 1280 }; 1281 1282 vin5: video@e6ef5000 { 1283 compatible = "renesas,vin-r8a774c0"; 1284 reg = <0 0xe6ef5000 0 0x1000>; 1285 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1286 clocks = <&cpg CPG_MOD 806>; 1287 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1288 resets = <&cpg 806>; 1289 renesas,id = <5>; 1290 status = "disabled"; 1291 1292 ports { 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 1296 port@1 { 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 1300 reg = <1>; 1301 1302 vin5csi40: endpoint@2 { 1303 reg = <2>; 1304 remote-endpoint= <&csi40vin5>; 1305 }; 1306 }; 1307 }; 1308 }; 1309 1310 rcar_sound: sound@ec500000 { 1311 /* 1312 * #sound-dai-cells is required 1313 * 1314 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1315 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1316 */ 1317 /* 1318 * #clock-cells is required for audio_clkout0/1/2/3 1319 * 1320 * clkout : #clock-cells = <0>; <&rcar_sound>; 1321 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1322 */ 1323 compatible = "renesas,rcar_sound-r8a774c0", 1324 "renesas,rcar_sound-gen3"; 1325 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1326 <0 0xec5a0000 0 0x100>, /* ADG */ 1327 <0 0xec540000 0 0x1000>, /* SSIU */ 1328 <0 0xec541000 0 0x280>, /* SSI */ 1329 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1330 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1331 1332 clocks = <&cpg CPG_MOD 1005>, 1333 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1334 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1335 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1336 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1337 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1338 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1339 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1340 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1341 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1342 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1343 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1344 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1345 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1346 <&audio_clk_a>, <&audio_clk_b>, 1347 <&audio_clk_c>, 1348 <&cpg CPG_CORE R8A774C0_CLK_ZA2>; 1349 clock-names = "ssi-all", 1350 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1351 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1352 "ssi.1", "ssi.0", 1353 "src.9", "src.8", "src.7", "src.6", 1354 "src.5", "src.4", "src.3", "src.2", 1355 "src.1", "src.0", 1356 "mix.1", "mix.0", 1357 "ctu.1", "ctu.0", 1358 "dvc.0", "dvc.1", 1359 "clk_a", "clk_b", "clk_c", "clk_i"; 1360 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1361 resets = <&cpg 1005>, 1362 <&cpg 1006>, <&cpg 1007>, 1363 <&cpg 1008>, <&cpg 1009>, 1364 <&cpg 1010>, <&cpg 1011>, 1365 <&cpg 1012>, <&cpg 1013>, 1366 <&cpg 1014>, <&cpg 1015>; 1367 reset-names = "ssi-all", 1368 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1369 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1370 "ssi.1", "ssi.0"; 1371 status = "disabled"; 1372 1373 rcar_sound,ctu { 1374 ctu00: ctu-0 { }; 1375 ctu01: ctu-1 { }; 1376 ctu02: ctu-2 { }; 1377 ctu03: ctu-3 { }; 1378 ctu10: ctu-4 { }; 1379 ctu11: ctu-5 { }; 1380 ctu12: ctu-6 { }; 1381 ctu13: ctu-7 { }; 1382 }; 1383 1384 rcar_sound,dvc { 1385 dvc0: dvc-0 { 1386 dmas = <&audma0 0xbc>; 1387 dma-names = "tx"; 1388 }; 1389 dvc1: dvc-1 { 1390 dmas = <&audma0 0xbe>; 1391 dma-names = "tx"; 1392 }; 1393 }; 1394 1395 rcar_sound,mix { 1396 mix0: mix-0 { }; 1397 mix1: mix-1 { }; 1398 }; 1399 1400 rcar_sound,src { 1401 src0: src-0 { 1402 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1403 dmas = <&audma0 0x85>, <&audma0 0x9a>; 1404 dma-names = "rx", "tx"; 1405 }; 1406 src1: src-1 { 1407 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1408 dmas = <&audma0 0x87>, <&audma0 0x9c>; 1409 dma-names = "rx", "tx"; 1410 }; 1411 src2: src-2 { 1412 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1413 dmas = <&audma0 0x89>, <&audma0 0x9e>; 1414 dma-names = "rx", "tx"; 1415 }; 1416 src3: src-3 { 1417 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1418 dmas = <&audma0 0x8b>, <&audma0 0xa0>; 1419 dma-names = "rx", "tx"; 1420 }; 1421 src4: src-4 { 1422 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1423 dmas = <&audma0 0x8d>, <&audma0 0xb0>; 1424 dma-names = "rx", "tx"; 1425 }; 1426 src5: src-5 { 1427 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1428 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1429 dma-names = "rx", "tx"; 1430 }; 1431 src6: src-6 { 1432 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1433 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1434 dma-names = "rx", "tx"; 1435 }; 1436 src7: src-7 { 1437 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1438 dmas = <&audma0 0x93>, <&audma0 0xb6>; 1439 dma-names = "rx", "tx"; 1440 }; 1441 src8: src-8 { 1442 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1443 dmas = <&audma0 0x95>, <&audma0 0xb8>; 1444 dma-names = "rx", "tx"; 1445 }; 1446 src9: src-9 { 1447 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1448 dmas = <&audma0 0x97>, <&audma0 0xba>; 1449 dma-names = "rx", "tx"; 1450 }; 1451 }; 1452 1453 rcar_sound,ssi { 1454 ssi0: ssi-0 { 1455 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1456 dmas = <&audma0 0x01>, <&audma0 0x02>, 1457 <&audma0 0x15>, <&audma0 0x16>; 1458 dma-names = "rx", "tx", "rxu", "txu"; 1459 }; 1460 ssi1: ssi-1 { 1461 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1462 dmas = <&audma0 0x03>, <&audma0 0x04>, 1463 <&audma0 0x49>, <&audma0 0x4a>; 1464 dma-names = "rx", "tx", "rxu", "txu"; 1465 }; 1466 ssi2: ssi-2 { 1467 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1468 dmas = <&audma0 0x05>, <&audma0 0x06>, 1469 <&audma0 0x63>, <&audma0 0x64>; 1470 dma-names = "rx", "tx", "rxu", "txu"; 1471 }; 1472 ssi3: ssi-3 { 1473 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1474 dmas = <&audma0 0x07>, <&audma0 0x08>, 1475 <&audma0 0x6f>, <&audma0 0x70>; 1476 dma-names = "rx", "tx", "rxu", "txu"; 1477 }; 1478 ssi4: ssi-4 { 1479 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1480 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1481 <&audma0 0x71>, <&audma0 0x72>; 1482 dma-names = "rx", "tx", "rxu", "txu"; 1483 }; 1484 ssi5: ssi-5 { 1485 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1486 dmas = <&audma0 0x0b>, <&audma0 0x0c>, 1487 <&audma0 0x73>, <&audma0 0x74>; 1488 dma-names = "rx", "tx", "rxu", "txu"; 1489 }; 1490 ssi6: ssi-6 { 1491 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1492 dmas = <&audma0 0x0d>, <&audma0 0x0e>, 1493 <&audma0 0x75>, <&audma0 0x76>; 1494 dma-names = "rx", "tx", "rxu", "txu"; 1495 }; 1496 ssi7: ssi-7 { 1497 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1498 dmas = <&audma0 0x0f>, <&audma0 0x10>, 1499 <&audma0 0x79>, <&audma0 0x7a>; 1500 dma-names = "rx", "tx", "rxu", "txu"; 1501 }; 1502 ssi8: ssi-8 { 1503 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1504 dmas = <&audma0 0x11>, <&audma0 0x12>, 1505 <&audma0 0x7b>, <&audma0 0x7c>; 1506 dma-names = "rx", "tx", "rxu", "txu"; 1507 }; 1508 ssi9: ssi-9 { 1509 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1510 dmas = <&audma0 0x13>, <&audma0 0x14>, 1511 <&audma0 0x7d>, <&audma0 0x7e>; 1512 dma-names = "rx", "tx", "rxu", "txu"; 1513 }; 1514 }; 1515 }; 1516 1517 audma0: dma-controller@ec700000 { 1518 compatible = "renesas,dmac-r8a774c0", 1519 "renesas,rcar-dmac"; 1520 reg = <0 0xec700000 0 0x10000>; 1521 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1538 interrupt-names = "error", 1539 "ch0", "ch1", "ch2", "ch3", 1540 "ch4", "ch5", "ch6", "ch7", 1541 "ch8", "ch9", "ch10", "ch11", 1542 "ch12", "ch13", "ch14", "ch15"; 1543 clocks = <&cpg CPG_MOD 502>; 1544 clock-names = "fck"; 1545 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1546 resets = <&cpg 502>; 1547 #dma-cells = <1>; 1548 dma-channels = <16>; 1549 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1550 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1551 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1552 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1553 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1554 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1555 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1556 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1557 }; 1558 1559 xhci0: usb@ee000000 { 1560 compatible = "renesas,xhci-r8a774c0", 1561 "renesas,rcar-gen3-xhci"; 1562 reg = <0 0xee000000 0 0xc00>; 1563 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1564 clocks = <&cpg CPG_MOD 328>; 1565 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1566 resets = <&cpg 328>; 1567 status = "disabled"; 1568 }; 1569 1570 usb3_peri0: usb@ee020000 { 1571 compatible = "renesas,r8a774c0-usb3-peri", 1572 "renesas,rcar-gen3-usb3-peri"; 1573 reg = <0 0xee020000 0 0x400>; 1574 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1575 clocks = <&cpg CPG_MOD 328>; 1576 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1577 resets = <&cpg 328>; 1578 status = "disabled"; 1579 }; 1580 1581 ohci0: usb@ee080000 { 1582 compatible = "generic-ohci"; 1583 reg = <0 0xee080000 0 0x100>; 1584 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1585 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1586 phys = <&usb2_phy0 1>; 1587 phy-names = "usb"; 1588 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1589 resets = <&cpg 703>, <&cpg 704>; 1590 status = "disabled"; 1591 }; 1592 1593 ehci0: usb@ee080100 { 1594 compatible = "generic-ehci"; 1595 reg = <0 0xee080100 0 0x100>; 1596 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1597 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1598 phys = <&usb2_phy0 2>; 1599 phy-names = "usb"; 1600 companion = <&ohci0>; 1601 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1602 resets = <&cpg 703>, <&cpg 704>; 1603 status = "disabled"; 1604 }; 1605 1606 usb2_phy0: usb-phy@ee080200 { 1607 compatible = "renesas,usb2-phy-r8a774c0", 1608 "renesas,rcar-gen3-usb2-phy"; 1609 reg = <0 0xee080200 0 0x700>; 1610 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1611 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1612 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1613 resets = <&cpg 703>, <&cpg 704>; 1614 #phy-cells = <1>; 1615 status = "disabled"; 1616 }; 1617 1618 sdhi0: mmc@ee100000 { 1619 compatible = "renesas,sdhi-r8a774c0", 1620 "renesas,rcar-gen3-sdhi"; 1621 reg = <0 0xee100000 0 0x2000>; 1622 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&cpg CPG_MOD 314>; 1624 max-frequency = <200000000>; 1625 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1626 resets = <&cpg 314>; 1627 status = "disabled"; 1628 }; 1629 1630 sdhi1: mmc@ee120000 { 1631 compatible = "renesas,sdhi-r8a774c0", 1632 "renesas,rcar-gen3-sdhi"; 1633 reg = <0 0xee120000 0 0x2000>; 1634 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1635 clocks = <&cpg CPG_MOD 313>; 1636 max-frequency = <200000000>; 1637 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1638 resets = <&cpg 313>; 1639 status = "disabled"; 1640 }; 1641 1642 sdhi3: mmc@ee160000 { 1643 compatible = "renesas,sdhi-r8a774c0", 1644 "renesas,rcar-gen3-sdhi"; 1645 reg = <0 0xee160000 0 0x2000>; 1646 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1647 clocks = <&cpg CPG_MOD 311>; 1648 max-frequency = <200000000>; 1649 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1650 resets = <&cpg 311>; 1651 status = "disabled"; 1652 }; 1653 1654 gic: interrupt-controller@f1010000 { 1655 compatible = "arm,gic-400"; 1656 #interrupt-cells = <3>; 1657 #address-cells = <0>; 1658 interrupt-controller; 1659 reg = <0x0 0xf1010000 0 0x1000>, 1660 <0x0 0xf1020000 0 0x20000>, 1661 <0x0 0xf1040000 0 0x20000>, 1662 <0x0 0xf1060000 0 0x20000>; 1663 interrupts = <GIC_PPI 9 1664 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1665 clocks = <&cpg CPG_MOD 408>; 1666 clock-names = "clk"; 1667 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1668 resets = <&cpg 408>; 1669 }; 1670 1671 pciec0: pcie@fe000000 { 1672 compatible = "renesas,pcie-r8a774c0", 1673 "renesas,pcie-rcar-gen3"; 1674 reg = <0 0xfe000000 0 0x80000>; 1675 #address-cells = <3>; 1676 #size-cells = <2>; 1677 bus-range = <0x00 0xff>; 1678 device_type = "pci"; 1679 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 1680 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 1681 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 1682 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1683 /* Map all possible DDR as inbound ranges */ 1684 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 1685 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1688 #interrupt-cells = <1>; 1689 interrupt-map-mask = <0 0 0 0>; 1690 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1691 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1692 clock-names = "pcie", "pcie_bus"; 1693 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1694 resets = <&cpg 319>; 1695 status = "disabled"; 1696 }; 1697 1698 pciec0_ep: pcie-ep@fe000000 { 1699 compatible = "renesas,r8a774c0-pcie-ep", 1700 "renesas,rcar-gen3-pcie-ep"; 1701 reg = <0x0 0xfe000000 0 0x80000>, 1702 <0x0 0xfe100000 0 0x100000>, 1703 <0x0 0xfe200000 0 0x200000>, 1704 <0x0 0x30000000 0 0x8000000>, 1705 <0x0 0x38000000 0 0x8000000>; 1706 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 1707 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1710 clocks = <&cpg CPG_MOD 319>; 1711 clock-names = "pcie"; 1712 resets = <&cpg 319>; 1713 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1714 status = "disabled"; 1715 }; 1716 1717 vspb0: vsp@fe960000 { 1718 compatible = "renesas,vsp2"; 1719 reg = <0 0xfe960000 0 0x8000>; 1720 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1721 clocks = <&cpg CPG_MOD 626>; 1722 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1723 resets = <&cpg 626>; 1724 renesas,fcp = <&fcpvb0>; 1725 }; 1726 1727 vspd0: vsp@fea20000 { 1728 compatible = "renesas,vsp2"; 1729 reg = <0 0xfea20000 0 0x7000>; 1730 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1731 clocks = <&cpg CPG_MOD 623>; 1732 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1733 resets = <&cpg 623>; 1734 renesas,fcp = <&fcpvd0>; 1735 }; 1736 1737 vspd1: vsp@fea28000 { 1738 compatible = "renesas,vsp2"; 1739 reg = <0 0xfea28000 0 0x7000>; 1740 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1741 clocks = <&cpg CPG_MOD 622>; 1742 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1743 resets = <&cpg 622>; 1744 renesas,fcp = <&fcpvd1>; 1745 }; 1746 1747 vspi0: vsp@fe9a0000 { 1748 compatible = "renesas,vsp2"; 1749 reg = <0 0xfe9a0000 0 0x8000>; 1750 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1751 clocks = <&cpg CPG_MOD 631>; 1752 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1753 resets = <&cpg 631>; 1754 renesas,fcp = <&fcpvi0>; 1755 }; 1756 1757 fcpvb0: fcp@fe96f000 { 1758 compatible = "renesas,fcpv"; 1759 reg = <0 0xfe96f000 0 0x200>; 1760 clocks = <&cpg CPG_MOD 607>; 1761 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1762 resets = <&cpg 607>; 1763 iommus = <&ipmmu_vp0 5>; 1764 }; 1765 1766 fcpvd0: fcp@fea27000 { 1767 compatible = "renesas,fcpv"; 1768 reg = <0 0xfea27000 0 0x200>; 1769 clocks = <&cpg CPG_MOD 603>; 1770 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1771 resets = <&cpg 603>; 1772 iommus = <&ipmmu_vi0 8>; 1773 }; 1774 1775 fcpvd1: fcp@fea2f000 { 1776 compatible = "renesas,fcpv"; 1777 reg = <0 0xfea2f000 0 0x200>; 1778 clocks = <&cpg CPG_MOD 602>; 1779 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1780 resets = <&cpg 602>; 1781 iommus = <&ipmmu_vi0 9>; 1782 }; 1783 1784 fcpvi0: fcp@fe9af000 { 1785 compatible = "renesas,fcpv"; 1786 reg = <0 0xfe9af000 0 0x200>; 1787 clocks = <&cpg CPG_MOD 611>; 1788 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1789 resets = <&cpg 611>; 1790 iommus = <&ipmmu_vp0 8>; 1791 }; 1792 1793 csi40: csi2@feaa0000 { 1794 compatible = "renesas,r8a774c0-csi2"; 1795 reg = <0 0xfeaa0000 0 0x10000>; 1796 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1797 clocks = <&cpg CPG_MOD 716>; 1798 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1799 resets = <&cpg 716>; 1800 status = "disabled"; 1801 1802 ports { 1803 #address-cells = <1>; 1804 #size-cells = <0>; 1805 1806 port@1 { 1807 #address-cells = <1>; 1808 #size-cells = <0>; 1809 1810 reg = <1>; 1811 1812 csi40vin4: endpoint@0 { 1813 reg = <0>; 1814 remote-endpoint = <&vin4csi40>; 1815 }; 1816 csi40vin5: endpoint@1 { 1817 reg = <1>; 1818 remote-endpoint = <&vin5csi40>; 1819 }; 1820 }; 1821 }; 1822 }; 1823 1824 du: display@feb00000 { 1825 compatible = "renesas,du-r8a774c0"; 1826 reg = <0 0xfeb00000 0 0x40000>; 1827 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1829 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1830 clock-names = "du.0", "du.1"; 1831 resets = <&cpg 724>; 1832 reset-names = "du.0"; 1833 renesas,vsps = <&vspd0 0>, <&vspd1 0>; 1834 1835 status = "disabled"; 1836 1837 ports { 1838 #address-cells = <1>; 1839 #size-cells = <0>; 1840 1841 port@0 { 1842 reg = <0>; 1843 du_out_rgb: endpoint { 1844 }; 1845 }; 1846 1847 port@1 { 1848 reg = <1>; 1849 du_out_lvds0: endpoint { 1850 remote-endpoint = <&lvds0_in>; 1851 }; 1852 }; 1853 1854 port@2 { 1855 reg = <2>; 1856 du_out_lvds1: endpoint { 1857 remote-endpoint = <&lvds1_in>; 1858 }; 1859 }; 1860 }; 1861 }; 1862 1863 lvds0: lvds-encoder@feb90000 { 1864 compatible = "renesas,r8a774c0-lvds"; 1865 reg = <0 0xfeb90000 0 0x20>; 1866 clocks = <&cpg CPG_MOD 727>; 1867 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1868 resets = <&cpg 727>; 1869 status = "disabled"; 1870 1871 renesas,companion = <&lvds1>; 1872 1873 ports { 1874 #address-cells = <1>; 1875 #size-cells = <0>; 1876 1877 port@0 { 1878 reg = <0>; 1879 lvds0_in: endpoint { 1880 remote-endpoint = <&du_out_lvds0>; 1881 }; 1882 }; 1883 1884 port@1 { 1885 reg = <1>; 1886 lvds0_out: endpoint { 1887 }; 1888 }; 1889 }; 1890 }; 1891 1892 lvds1: lvds-encoder@feb90100 { 1893 compatible = "renesas,r8a774c0-lvds"; 1894 reg = <0 0xfeb90100 0 0x20>; 1895 clocks = <&cpg CPG_MOD 727>; 1896 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1897 resets = <&cpg 726>; 1898 status = "disabled"; 1899 1900 ports { 1901 #address-cells = <1>; 1902 #size-cells = <0>; 1903 1904 port@0 { 1905 reg = <0>; 1906 lvds1_in: endpoint { 1907 remote-endpoint = <&du_out_lvds1>; 1908 }; 1909 }; 1910 1911 port@1 { 1912 reg = <1>; 1913 lvds1_out: endpoint { 1914 }; 1915 }; 1916 }; 1917 }; 1918 1919 prr: chipid@fff00044 { 1920 compatible = "renesas,prr"; 1921 reg = <0 0xfff00044 0 4>; 1922 }; 1923 }; 1924 1925 thermal-zones { 1926 cpu-thermal { 1927 polling-delay-passive = <250>; 1928 polling-delay = <0>; 1929 thermal-sensors = <&thermal>; 1930 sustainable-power = <717>; 1931 1932 cooling-maps { 1933 map0 { 1934 trip = <&target>; 1935 cooling-device = <&a53_0 0 2>; 1936 contribution = <1024>; 1937 }; 1938 }; 1939 1940 trips { 1941 sensor1_crit: sensor1-crit { 1942 temperature = <120000>; 1943 hysteresis = <2000>; 1944 type = "critical"; 1945 }; 1946 1947 target: trip-point1 { 1948 temperature = <100000>; 1949 hysteresis = <2000>; 1950 type = "passive"; 1951 }; 1952 }; 1953 }; 1954 }; 1955 1956 timer { 1957 compatible = "arm,armv8-timer"; 1958 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1959 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1960 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1961 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1962 }; 1963 1964 /* External USB clocks - can be overridden by the board */ 1965 usb3s0_clk: usb3s0 { 1966 compatible = "fixed-clock"; 1967 #clock-cells = <0>; 1968 clock-frequency = <0>; 1969 }; 1970 1971 usb_extal_clk: usb_extal { 1972 compatible = "fixed-clock"; 1973 #clock-cells = <0>; 1974 clock-frequency = <0>; 1975 }; 1976}; 1977