Lines Matching refs:r11
76 ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
77 teq r11, #0
80 str r6, [r11, #L2X0_CACHE_SYNC]
82 ldr r6, [r11, #L2X0_CACHE_SYNC]
94 ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
95 ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
103 str r9, [r11, r8]
108 ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
109 ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
116 ldr r6, [r11, r7]
118 str r6, [r11, r7]
120 ldr r6, [r11, r7]
125 ldr r6, [r11, r7]
127 str r6, [r11, r7]
129 ldr r6, [r11, r7]
134 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
136 str r7, [r11, #MX6Q_MMDC_MAPSR]
138 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
143 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
145 str r7, [r11, #MX6Q_MMDC_MAPSR]
170 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
171 ldr r6, [r11, #0x0]
172 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
173 ldr r6, [r11, #0x0]
174 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
175 ldr r6, [r11, #0x0]
178 ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
180 str r9, [r11, #MX6Q_SRC_GPR1]
181 str r1, [r11, #MX6Q_SRC_GPR2]
186 ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
191 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
193 str r7, [r11, #MX6Q_MMDC_MAPSR]
196 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
198 str r7, [r11, #MX6Q_MMDC_MAPSR]
201 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
205 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
215 str r6, [r11, r9]
223 str r6, [r11, r9]
225 str r6, [r11, r9]
228 str r6, [r11, r9]
238 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
239 ldr r6, [r11, #MX6Q_GPC_IMR1]
240 ldr r7, [r11, #MX6Q_GPC_IMR2]
241 ldr r8, [r11, #MX6Q_GPC_IMR3]
242 ldr r9, [r11, #MX6Q_GPC_IMR4]
245 str r10, [r11, #MX6Q_GPC_IMR1]
246 str r10, [r11, #MX6Q_GPC_IMR2]
247 str r10, [r11, #MX6Q_GPC_IMR3]
248 str r10, [r11, #MX6Q_GPC_IMR4]
256 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
257 ldr r10, [r11, #MX6Q_CCM_CCR]
260 str r10, [r11, #MX6Q_CCM_CCR]
263 ldr r10, [r11, #MX6Q_CCM_CCR]
265 str r10, [r11, #MX6Q_CCM_CCR]
268 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
269 str r6, [r11, #MX6Q_GPC_IMR1]
270 str r7, [r11, #MX6Q_GPC_IMR2]
271 str r8, [r11, #MX6Q_GPC_IMR3]
272 str r9, [r11, #MX6Q_GPC_IMR4]
320 ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
322 str r7, [r11, #MX6Q_SRC_GPR1]
323 str r7, [r11, #MX6Q_SRC_GPR2]