Lines Matching refs:NULL
23 { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
28 { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
35 NULL,
39 { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
53 NULL,
71 NULL,
75 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
76 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
77 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
94 NULL,
98 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
103 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
108 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
113 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
120 NULL,
124 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
134 { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
140 { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
145 { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
152 NULL,
156 { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
168 { DRA7_VPE_VPE_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h23x2_ck" },
173 { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
174 { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
179 { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
180 { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
181 { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
182 { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
183 { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
184 { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
185 { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
190 { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
195 { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
200 { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
209 NULL,
216 NULL,
220 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
221 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
231 { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
232 { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
233 { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
234 { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
235 { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
236 { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
237 { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
238 { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
239 { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
240 { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
241 { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
242 { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
243 { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
244 { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
245 { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
250 { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
251 { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
257 NULL,
262 NULL,
267 NULL,
272 NULL,
277 NULL,
282 NULL,
286 { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
287 { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
288 { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
289 { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
290 { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
291 { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
297 { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
305 NULL,
312 NULL,
316 { 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
317 { 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },
329 NULL,
334 NULL,
343 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
344 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
351 NULL,
360 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
361 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
368 NULL,
372 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
378 NULL,
382 { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
387 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
395 { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
396 …{ DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core…
398 { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
399 { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
406 NULL,
411 NULL,
415 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
416 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
417 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
422 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
423 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
424 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
437 NULL,
446 NULL,
450 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
451 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
472 NULL,
476 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
481 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
486 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
491 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
496 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
501 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
506 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
511 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
516 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
521 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
526 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
531 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
536 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
542 NULL,
551 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
552 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
559 NULL,
568 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
569 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
575 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
580 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
585 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
590 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
595 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
606 { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
612 { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
613 { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
614 { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
615 { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
616 { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
617 { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
618 { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
619 { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
620 { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
621 { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
635 { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
636 { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
637 { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
638 { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
639 { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
640 { DRA7_L4SEC_SHAM2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
647 NULL,
652 NULL,
661 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
667 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
668 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
669 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
674 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
675 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
680 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
681 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
686 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
687 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
692 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
693 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
698 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
703 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
708 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
713 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
714 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
719 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
720 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
725 { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },
726 { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
727 { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
728 { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
729 { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
730 { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
740 { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },
747 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
752 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
757 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
762 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
767 { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },
776 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
781 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
786 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
793 NULL,
797 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
802 { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
803 { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
806 { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
807 { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
810 { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SOC_DRA76, "mcan_clk" },
845 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
846 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
847 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
848 DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
849 DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
850 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
851 DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
852 DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
853 DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
854 DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
855 DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
856 DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
857 DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
858 DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
859 DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
860 DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
861 DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
862 DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
863 DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
864 DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
865 DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
866 DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
867 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
868 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
869 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
870 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
871 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
872 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
873 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
874 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
875 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
876 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
877 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
878 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
879 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
880 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
881 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
882 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
883 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
884 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
885 DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
886 DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
887 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
888 DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
889 DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
890 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
891 DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
892 DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
893 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
894 DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
895 DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
896 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
897 DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
898 DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
899 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
900 DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
901 DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
902 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
903 DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
904 DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
905 DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
906 DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
907 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
908 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
909 DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
910 DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
911 DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
912 DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
913 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
914 DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
915 DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
916 DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
917 DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
918 DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
919 DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
920 DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
921 DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
922 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
923 DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
924 DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
925 DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
926 DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
927 DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
928 DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
929 DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
930 DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
931 DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
932 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
933 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),
934 { .node_name = NULL },
951 dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); in dra7xx_dt_clk_init()
956 dpll_ck = clk_get_sys(NULL, "dpll_usb_ck"); in dra7xx_dt_clk_init()
961 dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck"); in dra7xx_dt_clk_init()
966 hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk"); in dra7xx_dt_clk_init()