37 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock)		\  argument
44 	.hw.init	 = CLK_HW_INIT(_name, _parent, &zx_pll_ops,	\
52 #define ZX296718_PLL(_name, _parent, _reg, _table)			\  argument
53 ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
60 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags)		\  argument
67 		.hw.init = CLK_HW_INIT(_name,				\
80 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag)		\  argument
85 		.hw.init	= CLK_HW_INIT(_name,			\
98 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag)	\  argument
106 		.hw.init	= CLK_HW_INIT_PARENTS(_name,		\
114 #define MUX(_id, _name, _parent, _reg, _shift, _width)			\  argument
115 MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
122 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table)	\  argument
131 		.hw.init	= CLK_HW_INIT(_name,			\
147 #define AUDIO_DIV(_id, _name, _parent, _reg)				\  argument
151 	.hw.init	= CLK_HW_INIT(_name,				\