Lines Matching refs:vec4_instruction
154 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
160 bool is_supported_64bit_region(vec4_instruction *inst, unsigned arg);
165 vec4_instruction *inst, int arg);
167 vec4_instruction *emit(vec4_instruction *inst);
169 vec4_instruction *emit(enum opcode opcode);
170 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
171 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
173 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
175 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
179 vec4_instruction *emit_before(bblock_t *block,
180 vec4_instruction *inst,
181 vec4_instruction *new_inst);
183 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
184 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
185 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src…
207 vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
209 vec4_instruction *IF(src_reg src0, src_reg src1,
211 vec4_instruction *IF(enum brw_predicate predicate);
231 vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
245 vec4_instruction *emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
262 vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying, int comp);
265 src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
267 void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
271 void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
277 vec4_instruction *before_inst);
279 vec4_instruction *inst, src_reg src);
295 vec4_instruction *shuffle_64bit_data(dst_reg dst, src_reg src,
299 vec4_instruction *ref = NULL);
341 virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;