225                 const CPURegister& reg3, const CPURegister& reg4,  in AreAliased()  argument
234   const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};  in AreAliased()
261                         const CPURegister& reg3, const CPURegister& reg4,  in AreSameSizeAndType()  argument
268   match &= !reg4.is_valid() || reg4.IsSameSizeAndType(reg1);  in AreSameSizeAndType()
277                    const VRegister& reg3, const VRegister& reg4) {  in AreSameFormat()  argument
281          (!reg4.is_valid() || reg4.IsSameFormat(reg1));  in AreSameFormat()
285                     const VRegister& reg3, const VRegister& reg4) {  in AreConsecutive()  argument
288     DCHECK(!reg3.is_valid() && !reg4.is_valid());  in AreConsecutive()
295     DCHECK(!reg4.is_valid());  in AreConsecutive()
301   if (!reg4.is_valid()) {  in AreConsecutive()
303   } else if (reg4.code() != ((reg3.code() + 1) % kNumberOfVRegisters)) {  in AreConsecutive()