Lines Matching refs:shift_
57 : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {} in Operand()
59 : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {} in Operand()
66 : imm_(0), rm_(rm), shift_(LSL), amount_(0), rs_(NoReg) { in Operand()
74 : imm_(0), rm_(rm), shift_(shift), amount_(0), rs_(NoReg) { in Operand()
76 VIXL_ASSERT(shift_.IsRRX()); in Operand()
84 : imm_(0), rm_(rm), shift_(shift), amount_(amount), rs_(NoReg) { in Operand()
86 VIXL_ASSERT(!shift_.IsRRX()); in Operand()
88 switch (shift_.GetType()) { in Operand()
112 : imm_(0), rm_(rm), shift_(shift), amount_(0), rs_(rs) { in Operand()
114 VIXL_ASSERT(!shift_.IsRRX()); in Operand()
145 return rm_.IsValid() && !shift_.IsRRX() && !rs_.IsValid() && (amount_ == 0); in IsPlainRegister()
175 return shift_; in GetShift()
189 return shift_.IsRRX() ? kRRXEncodedValue : shift_.GetValue(); in GetTypeEncodingValue()
217 Shift shift_; variable
642 shift_(LSL), in rn_()
659 shift_(LSL), in rn_()
669 shift_(LSL), in rn_()
686 shift_(LSL), in rn_()
700 shift_(LSL), in rn_()
720 shift_(shift), in rn_()
724 VIXL_ASSERT(shift_.IsRRX()); in rn_()
736 shift_(shift), in rn_()
740 VIXL_ASSERT(shift_.IsRRX()); in rn_()
759 shift_(shift), in rn_()
780 shift_(shift), in rn_()
797 Shift GetShift() const { return shift_; } in GetShift()
809 return rm_.IsValid() && shift_.IsLSL() && (shift_amount_ == 0); in IsPlainRegister()
819 return (GetAddrMode() == Offset) && rm_.IsValid() && shift_.IsLSL() && in IsRegisterOffset()
826 return shift_.IsRRX() ? kRRXEncodedValue : shift_.GetValue(); in GetTypeEncodingValue()
831 bool IsShiftValid() const { return shift_.IsValidAmount(shift_amount_); } in IsShiftValid()
839 if ((shift_amount_ == 0) && shift_.IsRRX()) return; in CheckShift()
840 if ((shift_amount_ == 0) && !shift_.IsLSL()) { in CheckShift()
846 switch (shift_.GetType()) { in CheckShift()
868 Shift shift_; variable