1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE 23 * 24 ***********************************************************************************************************************/ 25 26 27 /** 28 ************************************************************************************************************************ 29 * @file addrlib2.h 30 * @brief Contains the Addr::V2::Lib class definition. 31 ************************************************************************************************************************ 32 */ 33 34 #ifndef __ADDR2_LIB2_H__ 35 #define __ADDR2_LIB2_H__ 36 37 #include "addrlib.h" 38 39 namespace Addr 40 { 41 namespace V2 42 { 43 44 /** 45 ************************************************************************************************************************ 46 * @brief Flags for SwizzleModeTable 47 ************************************************************************************************************************ 48 */ 49 union SwizzleModeFlags 50 { 51 struct 52 { 53 // Swizzle mode 54 UINT_32 isLinear : 1; // Linear 55 56 // Block size 57 UINT_32 is256b : 1; // Block size is 256B 58 UINT_32 is4kb : 1; // Block size is 4KB 59 UINT_32 is64kb : 1; // Block size is 64KB 60 UINT_32 isVar : 1; // Block size is variable 61 62 UINT_32 isZ : 1; // Z order swizzle mode 63 UINT_32 isStd : 1; // Standard swizzle mode 64 UINT_32 isDisp : 1; // Display swizzle mode 65 UINT_32 isRot : 1; // Rotate swizzle mode 66 67 // XOR mode 68 UINT_32 isXor : 1; // XOR after swizzle if set 69 70 UINT_32 isT : 1; // T mode 71 72 // GFX10 73 UINT_32 isRtOpt : 1; // mode opt for render target 74 75 UINT_32 reserved : 20; // Reserved bits 76 }; 77 78 UINT_32 u32All; 79 }; 80 81 struct Dim2d 82 { 83 UINT_32 w; 84 UINT_32 h; 85 }; 86 87 struct Dim3d 88 { 89 UINT_32 w; 90 UINT_32 h; 91 UINT_32 d; 92 }; 93 94 // Macro define resource block type 95 enum AddrBlockType 96 { 97 AddrBlockLinear = 0, // Resource uses linear swizzle mode 98 AddrBlockMicro = 1, // Resource uses 256B block 99 AddrBlockThin4KB = 2, // Resource uses thin 4KB block 100 AddrBlockThick4KB = 3, // Resource uses thick 4KB block 101 AddrBlockThin64KB = 4, // Resource uses thin 64KB block 102 AddrBlockThick64KB = 5, // Resource uses thick 64KB block 103 AddrBlockThinVar = 6, // Resource uses thin var block 104 AddrBlockThickVar = 7, // Resource uses thick var block 105 AddrBlockMaxTiledType, 106 107 AddrBlockThin256KB = AddrBlockThinVar, 108 AddrBlockThick256KB = AddrBlockThickVar, 109 }; 110 111 enum AddrSwSet 112 { 113 AddrSwSetZ = 1 << ADDR_SW_Z, 114 AddrSwSetS = 1 << ADDR_SW_S, 115 AddrSwSetD = 1 << ADDR_SW_D, 116 AddrSwSetR = 1 << ADDR_SW_R, 117 118 AddrSwSetAll = AddrSwSetZ | AddrSwSetS | AddrSwSetD | AddrSwSetR, 119 }; 120 121 const UINT_32 Size256 = 256u; 122 const UINT_32 Size4K = 4096u; 123 const UINT_32 Size64K = 65536u; 124 125 const UINT_32 Log2Size256 = 8u; 126 const UINT_32 Log2Size4K = 12u; 127 const UINT_32 Log2Size64K = 16u; 128 129 /** 130 ************************************************************************************************************************ 131 * @brief Bit setting for swizzle pattern 132 ************************************************************************************************************************ 133 */ 134 union ADDR_BIT_SETTING 135 { 136 struct 137 { 138 UINT_16 x; 139 UINT_16 y; 140 UINT_16 z; 141 UINT_16 s; 142 }; 143 UINT_64 value; 144 }; 145 146 /** 147 ************************************************************************************************************************ 148 * @brief Swizzle pattern information 149 ************************************************************************************************************************ 150 */ 151 // Accessed by index representing the logbase2 of (8bpp/16bpp/32bpp/64bpp/128bpp) 152 // contains the indices which map to 2D arrays SW_PATTERN_NIBBLE[0-9] which contain sections of an index equation. They are dependant on pipe# and bpe # 153 struct ADDR_SW_PATINFO 154 { 155 UINT_8 maxItemCount; 156 UINT_8 nibble01Idx; 157 UINT_16 nibble2Idx; 158 UINT_16 nibble3Idx; 159 UINT_8 nibble4Idx; 160 }; 161 162 /** 163 ************************************************************************************************************************ 164 * InitBit 165 * 166 * @brief 167 * Initialize bit setting value via a return value 168 ************************************************************************************************************************ 169 */ 170 #define InitBit(c, index) (1ull << ((c << 4) + index)) 171 172 const UINT_64 X0 = InitBit(0, 0); 173 const UINT_64 X1 = InitBit(0, 1); 174 const UINT_64 X2 = InitBit(0, 2); 175 const UINT_64 X3 = InitBit(0, 3); 176 const UINT_64 X4 = InitBit(0, 4); 177 const UINT_64 X5 = InitBit(0, 5); 178 const UINT_64 X6 = InitBit(0, 6); 179 const UINT_64 X7 = InitBit(0, 7); 180 const UINT_64 X8 = InitBit(0, 8); 181 const UINT_64 X9 = InitBit(0, 9); 182 const UINT_64 X10 = InitBit(0, 10); 183 const UINT_64 X11 = InitBit(0, 11); 184 185 const UINT_64 Y0 = InitBit(1, 0); 186 const UINT_64 Y1 = InitBit(1, 1); 187 const UINT_64 Y2 = InitBit(1, 2); 188 const UINT_64 Y3 = InitBit(1, 3); 189 const UINT_64 Y4 = InitBit(1, 4); 190 const UINT_64 Y5 = InitBit(1, 5); 191 const UINT_64 Y6 = InitBit(1, 6); 192 const UINT_64 Y7 = InitBit(1, 7); 193 const UINT_64 Y8 = InitBit(1, 8); 194 const UINT_64 Y9 = InitBit(1, 9); 195 const UINT_64 Y10 = InitBit(1, 10); 196 const UINT_64 Y11 = InitBit(1, 11); 197 198 const UINT_64 Z0 = InitBit(2, 0); 199 const UINT_64 Z1 = InitBit(2, 1); 200 const UINT_64 Z2 = InitBit(2, 2); 201 const UINT_64 Z3 = InitBit(2, 3); 202 const UINT_64 Z4 = InitBit(2, 4); 203 const UINT_64 Z5 = InitBit(2, 5); 204 const UINT_64 Z6 = InitBit(2, 6); 205 const UINT_64 Z7 = InitBit(2, 7); 206 const UINT_64 Z8 = InitBit(2, 8); 207 208 const UINT_64 S0 = InitBit(3, 0); 209 const UINT_64 S1 = InitBit(3, 1); 210 const UINT_64 S2 = InitBit(3, 2); 211 212 /** 213 ************************************************************************************************************************ 214 * @brief This class contains asic independent address lib functionalities 215 ************************************************************************************************************************ 216 */ 217 class Lib : public Addr::Lib 218 { 219 public: 220 virtual ~Lib(); 221 222 static Lib* GetLib( 223 ADDR_HANDLE hLib); 224 225 // 226 // Interface stubs 227 // 228 229 // For data surface 230 ADDR_E_RETURNCODE ComputeSurfaceInfo( 231 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 232 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 233 234 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord( 235 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 236 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 237 238 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr( 239 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 240 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 241 242 // For HTile 243 ADDR_E_RETURNCODE ComputeHtileInfo( 244 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 245 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 246 247 ADDR_E_RETURNCODE ComputeHtileAddrFromCoord( 248 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 249 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 250 251 ADDR_E_RETURNCODE ComputeHtileCoordFromAddr( 252 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 253 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 254 255 // For CMask 256 ADDR_E_RETURNCODE ComputeCmaskInfo( 257 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 258 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 259 260 ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord( 261 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 262 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 263 264 ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr( 265 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 266 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const; 267 268 // For FMask 269 ADDR_E_RETURNCODE ComputeFmaskInfo( 270 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, 271 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); 272 273 ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord( 274 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 275 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const; 276 277 ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr( 278 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 279 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const; 280 281 // For DCC key 282 ADDR_E_RETURNCODE ComputeDccInfo( 283 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 284 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 285 286 ADDR_E_RETURNCODE ComputeDccAddrFromCoord( 287 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 288 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 289 290 // Misc 291 ADDR_E_RETURNCODE ComputePipeBankXor( 292 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 293 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 294 295 ADDR_E_RETURNCODE ComputeSlicePipeBankXor( 296 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 297 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 298 299 ADDR_E_RETURNCODE ComputeSubResourceOffsetForSwizzlePattern( 300 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 301 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 302 303 ADDR_E_RETURNCODE ComputeNonBlockCompressedView( 304 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 305 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut); 306 307 ADDR_E_RETURNCODE Addr2GetPreferredSurfaceSetting( 308 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 309 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 310 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)311 virtual BOOL_32 IsValidDisplaySwizzleMode( 312 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 313 { 314 ADDR_NOT_IMPLEMENTED(); 315 return ADDR_NOTIMPLEMENTED; 316 } 317 318 protected: 319 Lib(); // Constructor is protected 320 Lib(const Client* pClient); 321 322 static const UINT_32 MaxNumOfBpp = 5; 323 static const UINT_32 MaxNumOfAA = 4; 324 325 static const Dim2d Block256_2d[MaxNumOfBpp]; 326 static const Dim3d Block1K_3d[MaxNumOfBpp]; 327 328 static const UINT_32 PrtAlignment = 64 * 1024; 329 static const UINT_32 MaxMacroBits = 20; 330 331 static const UINT_32 MaxMipLevels = 16; 332 IsValidSwMode(AddrSwizzleMode swizzleMode)333 BOOL_32 IsValidSwMode(AddrSwizzleMode swizzleMode) const 334 { 335 return (m_swizzleModeTable[swizzleMode].u32All != 0); 336 } 337 338 // Checking block size IsBlock256b(AddrSwizzleMode swizzleMode)339 BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode) const 340 { 341 return m_swizzleModeTable[swizzleMode].is256b; 342 } 343 IsBlock4kb(AddrSwizzleMode swizzleMode)344 BOOL_32 IsBlock4kb(AddrSwizzleMode swizzleMode) const 345 { 346 return m_swizzleModeTable[swizzleMode].is4kb; 347 } 348 IsBlock64kb(AddrSwizzleMode swizzleMode)349 BOOL_32 IsBlock64kb(AddrSwizzleMode swizzleMode) const 350 { 351 return m_swizzleModeTable[swizzleMode].is64kb; 352 } 353 IsBlockVariable(AddrSwizzleMode swizzleMode)354 BOOL_32 IsBlockVariable(AddrSwizzleMode swizzleMode) const 355 { 356 return m_swizzleModeTable[swizzleMode].isVar; 357 } 358 359 // Checking swizzle mode IsLinear(AddrSwizzleMode swizzleMode)360 BOOL_32 IsLinear(AddrSwizzleMode swizzleMode) const 361 { 362 return m_swizzleModeTable[swizzleMode].isLinear; 363 } 364 IsRtOptSwizzle(AddrSwizzleMode swizzleMode)365 BOOL_32 IsRtOptSwizzle(AddrSwizzleMode swizzleMode) const 366 { 367 return m_swizzleModeTable[swizzleMode].isRtOpt; 368 } 369 IsZOrderSwizzle(AddrSwizzleMode swizzleMode)370 BOOL_32 IsZOrderSwizzle(AddrSwizzleMode swizzleMode) const 371 { 372 return m_swizzleModeTable[swizzleMode].isZ; 373 } 374 IsStandardSwizzle(AddrSwizzleMode swizzleMode)375 BOOL_32 IsStandardSwizzle(AddrSwizzleMode swizzleMode) const 376 { 377 return m_swizzleModeTable[swizzleMode].isStd; 378 } 379 IsDisplaySwizzle(AddrSwizzleMode swizzleMode)380 BOOL_32 IsDisplaySwizzle(AddrSwizzleMode swizzleMode) const 381 { 382 return m_swizzleModeTable[swizzleMode].isDisp; 383 } 384 IsRotateSwizzle(AddrSwizzleMode swizzleMode)385 BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const 386 { 387 return m_swizzleModeTable[swizzleMode].isRot; 388 } 389 IsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)390 BOOL_32 IsStandardSwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 391 { 392 return HwlIsStandardSwizzle(resourceType, swizzleMode); 393 } 394 IsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)395 BOOL_32 IsDisplaySwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 396 { 397 return HwlIsDisplaySwizzle(resourceType, swizzleMode); 398 } 399 IsXor(AddrSwizzleMode swizzleMode)400 BOOL_32 IsXor(AddrSwizzleMode swizzleMode) const 401 { 402 return m_swizzleModeTable[swizzleMode].isXor; 403 } 404 IsPrt(AddrSwizzleMode swizzleMode)405 BOOL_32 IsPrt(AddrSwizzleMode swizzleMode) const 406 { 407 return m_swizzleModeTable[swizzleMode].isT; 408 } 409 IsNonPrtXor(AddrSwizzleMode swizzleMode)410 BOOL_32 IsNonPrtXor(AddrSwizzleMode swizzleMode) const 411 { 412 return (IsXor(swizzleMode) && (IsPrt(swizzleMode) == FALSE)); 413 } 414 415 // Checking resource type IsTex1d(AddrResourceType resourceType)416 static BOOL_32 IsTex1d(AddrResourceType resourceType) 417 { 418 return (resourceType == ADDR_RSRC_TEX_1D); 419 } 420 IsTex2d(AddrResourceType resourceType)421 static BOOL_32 IsTex2d(AddrResourceType resourceType) 422 { 423 return (resourceType == ADDR_RSRC_TEX_2D); 424 } 425 IsTex3d(AddrResourceType resourceType)426 static BOOL_32 IsTex3d(AddrResourceType resourceType) 427 { 428 return (resourceType == ADDR_RSRC_TEX_3D); 429 } 430 IsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)431 BOOL_32 IsThick(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 432 { 433 return HwlIsThick(resourceType, swizzleMode); 434 } 435 IsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)436 BOOL_32 IsThin(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 437 { 438 return HwlIsThin(resourceType, swizzleMode); 439 } 440 GetBlockSizeLog2(AddrSwizzleMode swizzleMode)441 UINT_32 GetBlockSizeLog2(AddrSwizzleMode swizzleMode) const 442 { 443 UINT_32 blockSizeLog2 = 0; 444 445 if (IsBlock256b(swizzleMode) || IsLinear(swizzleMode)) 446 { 447 blockSizeLog2 = 8; 448 } 449 else if (IsBlock4kb(swizzleMode)) 450 { 451 blockSizeLog2 = 12; 452 } 453 else if (IsBlock64kb(swizzleMode)) 454 { 455 blockSizeLog2 = 16; 456 } 457 else if (IsBlockVariable(swizzleMode) && (m_blockVarSizeLog2 != 0)) 458 { 459 blockSizeLog2 = m_blockVarSizeLog2; 460 } 461 else 462 { 463 ADDR_ASSERT_ALWAYS(); 464 } 465 466 return blockSizeLog2; 467 } 468 GetBlockSize(AddrSwizzleMode swizzleMode)469 UINT_32 GetBlockSize(AddrSwizzleMode swizzleMode) const 470 { 471 return (1 << GetBlockSizeLog2(swizzleMode)); 472 } 473 GetFmaskBpp(UINT_32 sample,UINT_32 frag)474 static UINT_32 GetFmaskBpp(UINT_32 sample, UINT_32 frag) 475 { 476 sample = (sample == 0) ? 1 : sample; 477 frag = (frag == 0) ? sample : frag; 478 479 UINT_32 fmaskBpp = QLog2(frag); 480 481 if (sample > frag) 482 { 483 fmaskBpp++; 484 } 485 486 if (fmaskBpp == 3) 487 { 488 fmaskBpp = 4; 489 } 490 491 fmaskBpp = Max(8u, fmaskBpp * sample); 492 493 return fmaskBpp; 494 } 495 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)496 virtual BOOL_32 HwlIsStandardSwizzle( 497 AddrResourceType resourceType, 498 AddrSwizzleMode swizzleMode) const 499 { 500 ADDR_NOT_IMPLEMENTED(); 501 return FALSE; 502 } 503 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)504 virtual BOOL_32 HwlIsDisplaySwizzle( 505 AddrResourceType resourceType, 506 AddrSwizzleMode swizzleMode) const 507 { 508 ADDR_NOT_IMPLEMENTED(); 509 return FALSE; 510 } 511 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)512 virtual BOOL_32 HwlIsThin( 513 AddrResourceType resourceType, 514 AddrSwizzleMode swizzleMode) const 515 { 516 ADDR_NOT_IMPLEMENTED(); 517 return FALSE; 518 } 519 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)520 virtual BOOL_32 HwlIsThick( 521 AddrResourceType resourceType, 522 AddrSwizzleMode swizzleMode) const 523 { 524 ADDR_NOT_IMPLEMENTED(); 525 return FALSE; 526 } 527 HwlComputeHtileInfo(const ADDR2_COMPUTE_HTILE_INFO_INPUT * pIn,ADDR2_COMPUTE_HTILE_INFO_OUTPUT * pOut)528 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 529 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 530 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const 531 { 532 ADDR_NOT_IMPLEMENTED(); 533 return ADDR_NOTSUPPORTED; 534 } 535 HwlComputeCmaskInfo(const ADDR2_COMPUTE_CMASK_INFO_INPUT * pIn,ADDR2_COMPUTE_CMASK_INFO_OUTPUT * pOut)536 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 537 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 538 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const 539 { 540 ADDR_NOT_IMPLEMENTED(); 541 return ADDR_NOTSUPPORTED; 542 } 543 HwlComputeDccInfo(const ADDR2_COMPUTE_DCCINFO_INPUT * pIn,ADDR2_COMPUTE_DCCINFO_OUTPUT * pOut)544 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 545 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 546 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const 547 { 548 ADDR_NOT_IMPLEMENTED(); 549 return ADDR_NOTSUPPORTED; 550 } 551 HwlSupportComputeDccAddrFromCoord(const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT * pIn)552 virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord( 553 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn) 554 { 555 ADDR_NOT_IMPLEMENTED(); 556 return ADDR_NOTSUPPORTED; 557 } 558 HwlComputeDccAddrFromCoord(const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT * pOut)559 virtual VOID HwlComputeDccAddrFromCoord( 560 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 561 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) 562 { 563 ADDR_NOT_IMPLEMENTED(); 564 } 565 HwlComputeCmaskAddrFromCoord(const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT * pOut)566 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 567 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 568 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) 569 { 570 ADDR_NOT_IMPLEMENTED(); 571 return ADDR_NOTSUPPORTED; 572 } 573 HwlComputeHtileAddrFromCoord(const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT * pOut)574 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 575 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 576 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) 577 { 578 ADDR_NOT_IMPLEMENTED(); 579 return ADDR_NOTSUPPORTED; 580 } 581 HwlComputeHtileCoordFromAddr(const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT * pIn,ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT * pOut)582 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 583 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 584 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) 585 { 586 ADDR_NOT_IMPLEMENTED(); 587 return ADDR_NOTSUPPORTED; 588 } 589 HwlComputeBlock256Equation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)590 virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation( 591 AddrResourceType rsrcType, 592 AddrSwizzleMode swMode, 593 UINT_32 elementBytesLog2, 594 ADDR_EQUATION* pEquation) const 595 { 596 ADDR_NOT_IMPLEMENTED(); 597 return ADDR_NOTSUPPORTED; 598 } 599 HwlComputeThinEquation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)600 virtual ADDR_E_RETURNCODE HwlComputeThinEquation( 601 AddrResourceType rsrcType, 602 AddrSwizzleMode swMode, 603 UINT_32 elementBytesLog2, 604 ADDR_EQUATION* pEquation) const 605 { 606 ADDR_NOT_IMPLEMENTED(); 607 return ADDR_NOTSUPPORTED; 608 } 609 HwlComputeThickEquation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)610 virtual ADDR_E_RETURNCODE HwlComputeThickEquation( 611 AddrResourceType rsrcType, 612 AddrSwizzleMode swMode, 613 UINT_32 elementBytesLog2, 614 ADDR_EQUATION* pEquation) const 615 { 616 ADDR_NOT_IMPLEMENTED(); 617 return ADDR_NOTSUPPORTED; 618 } 619 HwlGetEquationIndex(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)620 virtual UINT_32 HwlGetEquationIndex( 621 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 622 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 623 { 624 ADDR_NOT_IMPLEMENTED(); 625 return ADDR_INVALID_EQUATION_INDEX; 626 } 627 GetEquationIndex(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)628 UINT_32 GetEquationIndex( 629 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 630 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 631 { 632 return HwlGetEquationIndex(pIn, pOut); 633 } 634 HwlComputePipeBankXor(const ADDR2_COMPUTE_PIPEBANKXOR_INPUT * pIn,ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT * pOut)635 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 636 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 637 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const 638 { 639 ADDR_NOT_IMPLEMENTED(); 640 return ADDR_NOTSUPPORTED; 641 } 642 HwlComputeSlicePipeBankXor(const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT * pIn,ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT * pOut)643 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 644 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 645 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const 646 { 647 ADDR_NOT_IMPLEMENTED(); 648 return ADDR_NOTSUPPORTED; 649 } 650 HwlComputeSubResourceOffsetForSwizzlePattern(const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT * pIn,ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT * pOut)651 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 652 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 653 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const 654 { 655 ADDR_NOT_IMPLEMENTED(); 656 return ADDR_NOTSUPPORTED; 657 } 658 HwlComputeNonBlockCompressedView(const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT * pIn,ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT * pOut)659 virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView( 660 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 661 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const 662 { 663 ADDR_NOT_IMPLEMENTED(); 664 return ADDR_NOTSUPPORTED; 665 } 666 HwlGetPreferredSurfaceSetting(const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT * pIn,ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT * pOut)667 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 668 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 669 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const 670 { 671 ADDR_NOT_IMPLEMENTED(); 672 return ADDR_NOTSUPPORTED; 673 } 674 HwlComputeSurfaceInfoSanityCheck(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)675 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 676 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 677 { 678 ADDR_NOT_IMPLEMENTED(); 679 return ADDR_NOTSUPPORTED; 680 } 681 HwlComputeSurfaceInfoTiled(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)682 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 683 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 684 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 685 { 686 ADDR_NOT_IMPLEMENTED(); 687 return ADDR_NOTIMPLEMENTED; 688 } 689 HwlComputeSurfaceInfoLinear(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)690 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 691 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 692 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 693 { 694 ADDR_NOT_IMPLEMENTED(); 695 return ADDR_NOTIMPLEMENTED; 696 } 697 HwlComputeSurfaceAddrFromCoordTiled(const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT * pOut)698 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 699 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 700 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const 701 { 702 ADDR_NOT_IMPLEMENTED(); 703 return ADDR_NOTIMPLEMENTED; 704 } 705 706 ADDR_E_RETURNCODE ComputeBlock256Equation( 707 AddrResourceType rsrcType, 708 AddrSwizzleMode swMode, 709 UINT_32 elementBytesLog2, 710 ADDR_EQUATION* pEquation) const; 711 712 ADDR_E_RETURNCODE ComputeThinEquation( 713 AddrResourceType rsrcType, 714 AddrSwizzleMode swMode, 715 UINT_32 elementBytesLog2, 716 ADDR_EQUATION* pEquation) const; 717 718 ADDR_E_RETURNCODE ComputeThickEquation( 719 AddrResourceType rsrcType, 720 AddrSwizzleMode swMode, 721 UINT_32 elementBytesLog2, 722 ADDR_EQUATION* pEquation) const; 723 724 ADDR_E_RETURNCODE ComputeSurfaceInfoSanityCheck( 725 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 726 727 ADDR_E_RETURNCODE ComputeSurfaceInfoLinear( 728 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 729 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 730 731 ADDR_E_RETURNCODE ComputeSurfaceInfoTiled( 732 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 733 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 734 735 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordLinear( 736 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 737 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 738 739 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordTiled( 740 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 741 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 742 743 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrLinear( 744 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 745 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 746 747 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrTiled( 748 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 749 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 750 751 UINT_32 ComputeSurface2DMicroBlockOffset( 752 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const; 753 754 UINT_32 ComputeSurface3DMicroBlockOffset( 755 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const; 756 757 // Misc 758 ADDR_E_RETURNCODE ComputeBlockDimensionForSurf( 759 UINT_32* pWidth, 760 UINT_32* pHeight, 761 UINT_32* pDepth, 762 UINT_32 bpp, 763 UINT_32 numSamples, 764 AddrResourceType resourceType, 765 AddrSwizzleMode swizzleMode) const; 766 767 ADDR_E_RETURNCODE ComputeBlockDimension( 768 UINT_32* pWidth, 769 UINT_32* pHeight, 770 UINT_32* pDepth, 771 UINT_32 bpp, 772 AddrResourceType resourceType, 773 AddrSwizzleMode swizzleMode) const; 774 775 virtual VOID ComputeThinBlockDimension( 776 UINT_32* pWidth, 777 UINT_32* pHeight, 778 UINT_32* pDepth, 779 UINT_32 bpp, 780 UINT_32 numSamples, 781 AddrResourceType resourceType, 782 AddrSwizzleMode swizzleMode) const; 783 784 VOID ComputeThickBlockDimension( 785 UINT_32* pWidth, 786 UINT_32* pHeight, 787 UINT_32* pDepth, 788 UINT_32 bpp, 789 AddrResourceType resourceType, 790 AddrSwizzleMode swizzleMode) const; 791 ComputePadSize(const Dim3d * pBlkDim,UINT_32 width,UINT_32 height,UINT_32 numSlices,Dim3d * pPadDim)792 static UINT_64 ComputePadSize( 793 const Dim3d* pBlkDim, 794 UINT_32 width, 795 UINT_32 height, 796 UINT_32 numSlices, 797 Dim3d* pPadDim) 798 { 799 pPadDim->w = PowTwoAlign(width ,pBlkDim->w); 800 pPadDim->h = PowTwoAlign(height ,pBlkDim->h); 801 pPadDim->d = PowTwoAlign(numSlices, pBlkDim->d); 802 return static_cast<UINT_64>(pPadDim->w) * pPadDim->h * pPadDim->d; 803 } 804 805 static ADDR_E_RETURNCODE ExtractPipeBankXor( 806 UINT_32 pipeBankXor, 807 UINT_32 bankBits, 808 UINT_32 pipeBits, 809 UINT_32* pBankX, 810 UINT_32* pPipeX); 811 Valid3DMipSliceIdConstraint(UINT_32 numSlices,UINT_32 mipId,UINT_32 slice)812 static BOOL_32 Valid3DMipSliceIdConstraint( 813 UINT_32 numSlices, 814 UINT_32 mipId, 815 UINT_32 slice) 816 { 817 return (Max((numSlices >> mipId), 1u) > slice); 818 } 819 820 Dim3d GetMipTailDim( 821 AddrResourceType resourceType, 822 AddrSwizzleMode swizzleMode, 823 UINT_32 blockWidth, 824 UINT_32 blockHeight, 825 UINT_32 blockDepth) const; 826 IsLocalHeap(AddrResrouceLocation resourceType)827 static BOOL_32 IsLocalHeap(AddrResrouceLocation resourceType) 828 { 829 return ((resourceType == ADDR_RSRC_LOC_LOCAL) || 830 (resourceType == ADDR_RSRC_LOC_INVIS)); 831 } 832 IsInvisibleHeap(AddrResrouceLocation resourceType)833 static BOOL_32 IsInvisibleHeap(AddrResrouceLocation resourceType) 834 { 835 return (resourceType == ADDR_RSRC_LOC_INVIS); 836 } 837 IsNonlocalHeap(AddrResrouceLocation resourceType)838 static BOOL_32 IsNonlocalHeap(AddrResrouceLocation resourceType) 839 { 840 return ((resourceType == ADDR_RSRC_LOC_USWC) || 841 (resourceType == ADDR_RSRC_LOC_CACHED)); 842 } 843 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned,AddrSwizzleMode swizzleMode)844 UINT_32 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const 845 { 846 UINT_32 numPipeLog2 = pipeAligned ? Min(m_pipesLog2 + m_seLog2, 5u) : 0; 847 848 if (IsXor(swizzleMode)) 849 { 850 UINT_32 maxPipeLog2 = GetBlockSizeLog2(swizzleMode) - m_pipeInterleaveLog2; 851 852 numPipeLog2 = Min(numPipeLog2, maxPipeLog2); 853 } 854 855 return numPipeLog2; 856 } 857 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned,AddrSwizzleMode swizzleMode)858 UINT_32 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const 859 { 860 return (1 << GetPipeLog2ForMetaAddressing(pipeAligned, swizzleMode)); 861 } 862 VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)863 VOID VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 864 { 865 #if DEBUG 866 if (pIn->numMipLevels > 1) 867 { 868 UINT_32 actualMipLevels = 1; 869 switch (pIn->resourceType) 870 { 871 case ADDR_RSRC_TEX_3D: 872 // Fall through to share 2D case 873 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->numSlices) + 1); 874 case ADDR_RSRC_TEX_2D: 875 // Fall through to share 1D case 876 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->height) + 1); 877 case ADDR_RSRC_TEX_1D: 878 // Base 1D case 879 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->width) + 1); 880 break; 881 default: 882 ADDR_ASSERT_ALWAYS(); 883 break; 884 } 885 // Client pass wrong number of MipLevels to addrlib and result will be bad. 886 // Not sure if we should fail this calling instead of putting an assertion here. 887 ADDR_ASSERT(actualMipLevels >= pIn->numMipLevels); 888 } 889 #endif 890 } 891 ApplyCustomerPipeBankXor(AddrSwizzleMode swizzleMode,UINT_32 pipeBankXor,UINT_32 bankBits,UINT_32 pipeBits,UINT_32 * pBlockOffset)892 ADDR_E_RETURNCODE ApplyCustomerPipeBankXor( 893 AddrSwizzleMode swizzleMode, 894 UINT_32 pipeBankXor, 895 UINT_32 bankBits, 896 UINT_32 pipeBits, 897 UINT_32* pBlockOffset) const 898 { 899 ADDR_E_RETURNCODE returnCode = ADDR_OK; 900 901 if (IsXor(swizzleMode)) 902 { 903 // Apply driver set bankPipeXor 904 UINT_32 bankX = 0; 905 UINT_32 pipeX = 0; 906 returnCode = ExtractPipeBankXor(pipeBankXor, bankBits, pipeBits, &bankX, &pipeX); 907 *pBlockOffset ^= (pipeX << m_pipeInterleaveLog2); 908 *pBlockOffset ^= (bankX << (m_pipeInterleaveLog2 + pipeBits)); 909 } 910 911 return returnCode; 912 } 913 914 UINT_32 GetPipeXorBits(UINT_32 macroBlockBits) const; 915 916 ADDR_E_RETURNCODE ApplyCustomizedPitchHeight( 917 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 918 UINT_32 elementBytes, 919 UINT_32 pitchAlignInElement, 920 UINT_32* pPitch, 921 UINT_32* pHeight) const; 922 923 VOID ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 924 925 VOID FilterInvalidEqSwizzleMode( 926 ADDR2_SWMODE_SET& allowedSwModeSet, 927 AddrResourceType resourceType, 928 UINT_32 elemLog2) const; 929 930 static BOOL_32 IsBlockTypeAvaiable(ADDR2_BLOCK_SET blockSet, AddrBlockType blockType); 931 932 static BOOL_32 BlockTypeWithinMemoryBudget( 933 UINT_64 minSize, 934 UINT_64 newBlockTypeSize, 935 UINT_32 ratioLow, 936 UINT_32 ratioHi, 937 DOUBLE memoryBudget = 0.0f, 938 BOOL_32 newBlockTypeBigger = TRUE); 939 940 #if DEBUG 941 VOID ValidateStereoInfo( 942 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 943 const ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 944 #endif 945 946 UINT_32 m_se; ///< Number of shader engine 947 UINT_32 m_rbPerSe; ///< Number of render backend per shader engine 948 UINT_32 m_maxCompFrag; ///< Number of max compressed fragment 949 950 UINT_32 m_banksLog2; ///< Number of bank Log2 951 UINT_32 m_pipesLog2; ///< Number of pipe per shader engine Log2 952 UINT_32 m_seLog2; ///< Number of shader engine Log2 953 UINT_32 m_rbPerSeLog2; ///< Number of render backend per shader engine Log2 954 UINT_32 m_maxCompFragLog2; ///< Number of max compressed fragment Log2 955 956 UINT_32 m_pipeInterleaveLog2; ///< Log2 of pipe interleave bytes 957 958 UINT_32 m_blockVarSizeLog2; ///< Log2 of block var size 959 960 SwizzleModeFlags m_swizzleModeTable[ADDR_SW_MAX_TYPE]; ///< Swizzle mode table 961 962 // Max number of swizzle mode supported for equation 963 static const UINT_32 MaxSwModeType = 32; 964 // Max number of resource type (2D/3D) supported for equation 965 static const UINT_32 MaxRsrcType = 2; 966 // Max number of bpp (8bpp/16bpp/32bpp/64bpp/128bpp) 967 static const UINT_32 MaxElementBytesLog2 = 5; 968 // Almost all swizzle mode + resource type support equation 969 static const UINT_32 EquationTableSize = MaxElementBytesLog2 * MaxSwModeType * MaxRsrcType; 970 // Equation table 971 ADDR_EQUATION m_equationTable[EquationTableSize]; 972 973 // Number of equation entries in the table 974 UINT_32 m_numEquations; 975 // Equation lookup table according to bpp and tile index 976 UINT_32 m_equationLookupTable[MaxRsrcType][MaxSwModeType][MaxElementBytesLog2]; 977 978 private: 979 // Disallow the copy constructor 980 Lib(const Lib& a); 981 982 // Disallow the assignment operator 983 Lib& operator=(const Lib& a); 984 }; 985 986 } // V2 987 } // Addr 988 989 #endif 990 991