| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixupVectorISel.cpp | 86 unsigned &BaseReg, in findSRegBaseAndIndex()
175 unsigned BaseReg = 0; in fixupGlobalSaddr() local
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| D | SIRegisterInfo.cpp | 112 unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); in reservedPrivateSegmentBufferReg() local
343 unsigned BaseReg, in materializeFrameBaseRegister()
377 void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
414 unsigned BaseReg, in isFrameOffsetLegal()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCOptAddrMode.cpp | 287 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
343 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
449 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
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| D | ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg; in ReplaceFrameIndex() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.cpp | 398 unsigned BaseReg, in isFrameOffsetLegal()
408 unsigned BaseReg, in materializeFrameBaseRegister()
429 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
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| D | AArch64StorePairSuppress.cpp | 154 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
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| D | AArch64FalkorHWPFFix.cpp | 217 Register BaseReg; member
646 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
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| D | AArch64LoadStoreOptimizer.cpp | 1176 Register BaseReg = getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1447 Register BaseReg = getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1703 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn()
1754 Register BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnForward() local
1814 Register BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnBackward() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 126 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmInReg()
189 unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmediate()
430 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
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| D | ARMBaseRegisterInfo.cpp | 631 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
655 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
683 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal()
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| D | Thumb2SizeReduction.cpp | 499 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
527 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
540 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 269 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg()
343 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 285 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference() local
350 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference() local
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| D | X86FixupLEAs.cpp | 368 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
548 Register BaseReg = Base.getReg(); in processInstrForSlow3OpLEA() local
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| D | X86InsertPrefetch.cpp | 82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
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| D | X86SelectionDAGInfo.cpp | 39 Register BaseReg = TRI->getBaseRegister(); in isBaseRegConflictPossible() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 186 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand() local
205 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand() local
227 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is64BitMemOperand() local
378 unsigned BaseReg = Base.getReg(); in emitMemModRMByte() local
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| D | X86IntelInstPrinter.cpp | 346 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference() local
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| D | X86ATTInstPrinter.cpp | 388 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 888 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
896 virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
903 virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 1250 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
1270 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
1295 unsigned BaseReg, in isFrameOffsetLegal()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 374 BaseReg = MBBIter->getOperand(1).getReg(); in combineMemAluInBasicBlock() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 581 for (const SCEV *BaseReg : BaseRegs) in hasRegsUsedByUsesOtherThan() local
598 for (const SCEV *BaseReg : BaseRegs) { in print() local
1342 for (const SCEV *BaseReg : F.BaseRegs) { in RateFormula() local
1552 for (const SCEV *BaseReg : F.BaseRegs) in InsertFormula() local
3366 for (const SCEV *BaseReg : F.BaseRegs) in CountRegisters() local
3574 const SCEV *BaseReg = IsScaledReg ? Base.ScaledReg : Base.BaseRegs[Idx]; in GenerateReassociationsImpl() local
3694 for (const SCEV *BaseReg : Base.BaseRegs) { in GenerateCombinations() local
3880 for (const SCEV *BaseReg : Base.BaseRegs) in GenerateICmpZeroScales() local
4048 for (const SCEV *&BaseReg : F.BaseRegs) { in GenerateTruncates() local
4232 const SCEV *BaseReg = F.BaseRegs[N]; in GenerateCrossUseConstantOffsets() local
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 345 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anonc3356ce30111::X86AsmParser::IntelExprStateMachine
1043 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg, in CheckBaseRegAndIndexRegAndScale()
1409 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, in CreateMemForInlineAsm()
1970 unsigned BaseReg = SM.getBaseReg(); in ParseIntelOperand() local
2294 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseMemOperand() local
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