1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 8 select ARCH_HAS_DEBUG_VIRTUAL if MMU 9 select ARCH_HAS_DEVMEM_IS_ALLOWED 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_PHYS_TO_DMA 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAS_GCOV_PROFILE_ALL 29 select ARCH_KEEP_MEMBLOCK 30 select ARCH_MIGHT_HAVE_PC_PARPORT 31 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 32 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 33 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 34 select ARCH_SUPPORTS_ATOMIC_RMW 35 select ARCH_USE_BUILTIN_BSWAP 36 select ARCH_USE_CMPXCHG_LOCKREF 37 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 38 select ARCH_WANT_IPC_PARSE_VERSION 39 select ARCH_WANT_LD_ORPHAN_WARN 40 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 41 select BUILDTIME_TABLE_SORT if MMU 42 select CLONE_BACKWARDS 43 select CPU_PM if SUSPEND || CPU_IDLE 44 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 45 select DMA_DECLARE_COHERENT 46 select DMA_OPS 47 select DMA_REMAP if MMU 48 select EDAC_SUPPORT 49 select EDAC_ATOMIC_SCRUB 50 select GENERIC_ALLOCATOR 51 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 52 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 53 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 54 select GENERIC_IRQ_IPI if SMP 55 select GENERIC_CPU_AUTOPROBE 56 select GENERIC_EARLY_IOREMAP 57 select GENERIC_IDLE_POLL_SETUP 58 select GENERIC_IRQ_PROBE 59 select GENERIC_IRQ_SHOW 60 select GENERIC_IRQ_SHOW_LEVEL 61 select GENERIC_PCI_IOMAP 62 select GENERIC_SCHED_CLOCK 63 select GENERIC_SMP_IDLE_THREAD 64 select GENERIC_STRNCPY_FROM_USER 65 select GENERIC_STRNLEN_USER 66 select HANDLE_DOMAIN_IRQ 67 select HARDIRQS_SW_RESEND 68 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 69 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 70 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 71 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 72 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 73 select HAVE_ARCH_MMAP_RND_BITS if MMU 74 select HAVE_ARCH_SECCOMP 75 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 76 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 77 select HAVE_ARCH_TRACEHOOK 78 select HAVE_ARM_SMCCC if CPU_V7 79 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 80 select HAVE_CONTEXT_TRACKING 81 select HAVE_C_RECORDMCOUNT 82 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 83 select HAVE_DMA_CONTIGUOUS if MMU 84 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 85 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 86 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 87 select HAVE_EXIT_THREAD 88 select HAVE_FAST_GUP if ARM_LPAE 89 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 90 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 91 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 92 select HAVE_FUTEX_CMPXCHG if FUTEX 93 select HAVE_GCC_PLUGINS 94 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 95 select HAVE_IDE if PCI || ISA || PCMCIA 96 select HAVE_IRQ_TIME_ACCOUNTING 97 select HAVE_KERNEL_GZIP 98 select HAVE_KERNEL_LZ4 99 select HAVE_KERNEL_LZMA 100 select HAVE_KERNEL_LZO 101 select HAVE_KERNEL_XZ 102 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 103 select HAVE_KRETPROBES if HAVE_KPROBES 104 select HAVE_MOD_ARCH_SPECIFIC 105 select HAVE_NMI 106 select HAVE_OPROFILE if HAVE_PERF_EVENTS 107 select HAVE_OPTPROBES if !THUMB2_KERNEL 108 select HAVE_PERF_EVENTS 109 select HAVE_PERF_REGS 110 select HAVE_PERF_USER_STACK_DUMP 111 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 112 select HAVE_REGS_AND_STACK_ACCESS_API 113 select HAVE_RSEQ 114 select HAVE_STACKPROTECTOR 115 select HAVE_SYSCALL_TRACEPOINTS 116 select HAVE_UID16 117 select HAVE_VIRT_CPU_ACCOUNTING_GEN 118 select IRQ_FORCED_THREADING 119 select MODULES_USE_ELF_REL 120 select NEED_DMA_MAP_STATE 121 select OF_EARLY_FLATTREE if OF 122 select OLD_SIGACTION 123 select OLD_SIGSUSPEND3 124 select PCI_SYSCALL if PCI 125 select PERF_USE_VMALLOC 126 select RTC_LIB 127 select SET_FS 128 select SYS_SUPPORTS_APM_EMULATION 129 # Above selects are sorted alphabetically; please add new ones 130 # according to that. Thanks. 131 help 132 The ARM series is a line of low-power-consumption RISC chip designs 133 licensed by ARM Ltd and targeted at embedded applications and 134 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 135 manufactured, but legacy ARM-based PC hardware remains popular in 136 Europe. There is an ARM Linux project with a web page at 137 <http://www.arm.linux.org.uk/>. 138 139config ARM_HAS_SG_CHAIN 140 bool 141 142config ARM_DMA_USE_IOMMU 143 bool 144 select ARM_HAS_SG_CHAIN 145 select NEED_SG_DMA_LENGTH 146 147if ARM_DMA_USE_IOMMU 148 149config ARM_DMA_IOMMU_ALIGNMENT 150 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 151 range 4 9 152 default 8 153 help 154 DMA mapping framework by default aligns all buffers to the smallest 155 PAGE_SIZE order which is greater than or equal to the requested buffer 156 size. This works well for buffers up to a few hundreds kilobytes, but 157 for larger buffers it just a waste of address space. Drivers which has 158 relatively small addressing window (like 64Mib) might run out of 159 virtual space with just a few allocations. 160 161 With this parameter you can specify the maximum PAGE_SIZE order for 162 DMA IOMMU buffers. Larger buffers will be aligned only to this 163 specified order. The order is expressed as a power of two multiplied 164 by the PAGE_SIZE. 165 166endif 167 168config SYS_SUPPORTS_APM_EMULATION 169 bool 170 171config HAVE_TCM 172 bool 173 select GENERIC_ALLOCATOR 174 175config HAVE_PROC_CPU 176 bool 177 178config NO_IOPORT_MAP 179 bool 180 181config SBUS 182 bool 183 184config STACKTRACE_SUPPORT 185 bool 186 default y 187 188config LOCKDEP_SUPPORT 189 bool 190 default y 191 192config TRACE_IRQFLAGS_SUPPORT 193 bool 194 default !CPU_V7M 195 196config ARCH_HAS_ILOG2_U32 197 bool 198 199config ARCH_HAS_ILOG2_U64 200 bool 201 202config ARCH_HAS_BANDGAP 203 bool 204 205config FIX_EARLYCON_MEM 206 def_bool y if MMU 207 208config GENERIC_HWEIGHT 209 bool 210 default y 211 212config GENERIC_CALIBRATE_DELAY 213 bool 214 default y 215 216config ARCH_MAY_HAVE_PC_FDC 217 bool 218 219config ZONE_DMA 220 bool 221 222config ARCH_SUPPORTS_UPROBES 223 def_bool y 224 225config ARCH_HAS_DMA_SET_COHERENT_MASK 226 bool 227 228config GENERIC_ISA_DMA 229 bool 230 231config FIQ 232 bool 233 234config NEED_RET_TO_USER 235 bool 236 237config ARCH_MTD_XIP 238 bool 239 240config ARM_PATCH_PHYS_VIRT 241 bool "Patch physical to virtual translations at runtime" if EMBEDDED 242 default y 243 depends on !XIP_KERNEL && MMU 244 help 245 Patch phys-to-virt and virt-to-phys translation functions at 246 boot and module load time according to the position of the 247 kernel in system memory. 248 249 This can only be used with non-XIP MMU kernels where the base 250 of physical memory is at a 2 MiB boundary. 251 252 Only disable this option if you know that you do not require 253 this feature (eg, building a kernel for a single machine) and 254 you need to shrink the kernel to the minimal size. 255 256config NEED_MACH_IO_H 257 bool 258 help 259 Select this when mach/io.h is required to provide special 260 definitions for this platform. The need for mach/io.h should 261 be avoided when possible. 262 263config NEED_MACH_MEMORY_H 264 bool 265 help 266 Select this when mach/memory.h is required to provide special 267 definitions for this platform. The need for mach/memory.h should 268 be avoided when possible. 269 270config PHYS_OFFSET 271 hex "Physical address of main memory" if MMU 272 depends on !ARM_PATCH_PHYS_VIRT 273 default DRAM_BASE if !MMU 274 default 0x00000000 if ARCH_EBSA110 || \ 275 ARCH_FOOTBRIDGE 276 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 277 default 0x20000000 if ARCH_S5PV210 278 default 0xc0000000 if ARCH_SA1100 279 help 280 Please provide the physical address corresponding to the 281 location of main memory in your system. 282 283config GENERIC_BUG 284 def_bool y 285 depends on BUG 286 287config PGTABLE_LEVELS 288 int 289 default 3 if ARM_LPAE 290 default 2 291 292menu "System Type" 293 294config MMU 295 bool "MMU-based Paged Memory Management Support" 296 default y 297 help 298 Select if you want MMU-based virtualised addressing space 299 support by paged memory management. If unsure, say 'Y'. 300 301config ARCH_MMAP_RND_BITS_MIN 302 default 8 303 304config ARCH_MMAP_RND_BITS_MAX 305 default 14 if PAGE_OFFSET=0x40000000 306 default 15 if PAGE_OFFSET=0x80000000 307 default 16 308 309# 310# The "ARM system type" choice list is ordered alphabetically by option 311# text. Please add new entries in the option alphabetic order. 312# 313choice 314 prompt "ARM system type" 315 default ARM_SINGLE_ARMV7M if !MMU 316 default ARCH_MULTIPLATFORM if MMU 317 318config ARCH_MULTIPLATFORM 319 bool "Allow multiple platforms to be selected" 320 depends on MMU 321 select ARCH_FLATMEM_ENABLE 322 select ARCH_SPARSEMEM_ENABLE 323 select ARCH_SELECT_MEMORY_MODEL 324 select ARM_HAS_SG_CHAIN 325 select ARM_PATCH_PHYS_VIRT 326 select AUTO_ZRELADDR 327 select TIMER_OF 328 select COMMON_CLK 329 select GENERIC_CLOCKEVENTS 330 select GENERIC_IRQ_MULTI_HANDLER 331 select HAVE_PCI 332 select PCI_DOMAINS_GENERIC if PCI 333 select SPARSE_IRQ 334 select USE_OF 335 336config ARM_SINGLE_ARMV7M 337 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 338 depends on !MMU 339 select ARM_NVIC 340 select AUTO_ZRELADDR 341 select TIMER_OF 342 select COMMON_CLK 343 select CPU_V7M 344 select GENERIC_CLOCKEVENTS 345 select NO_IOPORT_MAP 346 select SPARSE_IRQ 347 select USE_OF 348 349config ARCH_EBSA110 350 bool "EBSA-110" 351 select ARCH_USES_GETTIMEOFFSET 352 select CPU_SA110 353 select ISA 354 select NEED_MACH_IO_H 355 select NEED_MACH_MEMORY_H 356 select NO_IOPORT_MAP 357 help 358 This is an evaluation board for the StrongARM processor available 359 from Digital. It has limited hardware on-board, including an 360 Ethernet interface, two PCMCIA sockets, two serial ports and a 361 parallel port. 362 363config ARCH_EP93XX 364 bool "EP93xx-based" 365 select ARCH_SPARSEMEM_ENABLE 366 select ARM_AMBA 367 imply ARM_PATCH_PHYS_VIRT 368 select ARM_VIC 369 select AUTO_ZRELADDR 370 select CLKDEV_LOOKUP 371 select CLKSRC_MMIO 372 select CPU_ARM920T 373 select GENERIC_CLOCKEVENTS 374 select GPIOLIB 375 select HAVE_LEGACY_CLK 376 help 377 This enables support for the Cirrus EP93xx series of CPUs. 378 379config ARCH_FOOTBRIDGE 380 bool "FootBridge" 381 select CPU_SA110 382 select FOOTBRIDGE 383 select GENERIC_CLOCKEVENTS 384 select HAVE_IDE 385 select NEED_MACH_IO_H if !MMU 386 select NEED_MACH_MEMORY_H 387 help 388 Support for systems based on the DC21285 companion chip 389 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 390 391config ARCH_IOP32X 392 bool "IOP32x-based" 393 depends on MMU 394 select CPU_XSCALE 395 select GPIO_IOP 396 select GPIOLIB 397 select NEED_RET_TO_USER 398 select FORCE_PCI 399 select PLAT_IOP 400 help 401 Support for Intel's 80219 and IOP32X (XScale) family of 402 processors. 403 404config ARCH_IXP4XX 405 bool "IXP4xx-based" 406 depends on MMU 407 select ARCH_HAS_DMA_SET_COHERENT_MASK 408 select ARCH_SUPPORTS_BIG_ENDIAN 409 select CPU_XSCALE 410 select DMABOUNCE if PCI 411 select GENERIC_CLOCKEVENTS 412 select GENERIC_IRQ_MULTI_HANDLER 413 select GPIO_IXP4XX 414 select GPIOLIB 415 select HAVE_PCI 416 select IXP4XX_IRQ 417 select IXP4XX_TIMER 418 select NEED_MACH_IO_H 419 select USB_EHCI_BIG_ENDIAN_DESC 420 select USB_EHCI_BIG_ENDIAN_MMIO 421 help 422 Support for Intel's IXP4XX (XScale) family of processors. 423 424config ARCH_DOVE 425 bool "Marvell Dove" 426 select CPU_PJ4 427 select GENERIC_CLOCKEVENTS 428 select GENERIC_IRQ_MULTI_HANDLER 429 select GPIOLIB 430 select HAVE_PCI 431 select MVEBU_MBUS 432 select PINCTRL 433 select PINCTRL_DOVE 434 select PLAT_ORION_LEGACY 435 select SPARSE_IRQ 436 select PM_GENERIC_DOMAINS if PM 437 help 438 Support for the Marvell Dove SoC 88AP510 439 440config ARCH_PXA 441 bool "PXA2xx/PXA3xx-based" 442 depends on MMU 443 select ARCH_MTD_XIP 444 select ARM_CPU_SUSPEND if PM 445 select AUTO_ZRELADDR 446 select COMMON_CLK 447 select CLKSRC_PXA 448 select CLKSRC_MMIO 449 select TIMER_OF 450 select CPU_XSCALE if !CPU_XSC3 451 select GENERIC_CLOCKEVENTS 452 select GENERIC_IRQ_MULTI_HANDLER 453 select GPIO_PXA 454 select GPIOLIB 455 select HAVE_IDE 456 select IRQ_DOMAIN 457 select PLAT_PXA 458 select SPARSE_IRQ 459 help 460 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 461 462config ARCH_RPC 463 bool "RiscPC" 464 depends on MMU 465 select ARCH_ACORN 466 select ARCH_MAY_HAVE_PC_FDC 467 select ARCH_SPARSEMEM_ENABLE 468 select ARM_HAS_SG_CHAIN 469 select CPU_SA110 470 select FIQ 471 select HAVE_IDE 472 select HAVE_PATA_PLATFORM 473 select ISA_DMA_API 474 select NEED_MACH_IO_H 475 select NEED_MACH_MEMORY_H 476 select NO_IOPORT_MAP 477 help 478 On the Acorn Risc-PC, Linux can support the internal IDE disk and 479 CD-ROM interface, serial and parallel port, and the floppy drive. 480 481config ARCH_SA1100 482 bool "SA1100-based" 483 select ARCH_MTD_XIP 484 select ARCH_SPARSEMEM_ENABLE 485 select CLKSRC_MMIO 486 select CLKSRC_PXA 487 select TIMER_OF if OF 488 select COMMON_CLK 489 select CPU_FREQ 490 select CPU_SA1100 491 select GENERIC_CLOCKEVENTS 492 select GENERIC_IRQ_MULTI_HANDLER 493 select GPIOLIB 494 select HAVE_IDE 495 select IRQ_DOMAIN 496 select ISA 497 select NEED_MACH_MEMORY_H 498 select SPARSE_IRQ 499 help 500 Support for StrongARM 11x0 based boards. 501 502config ARCH_S3C24XX 503 bool "Samsung S3C24XX SoCs" 504 select ATAGS 505 select CLKSRC_SAMSUNG_PWM 506 select GENERIC_CLOCKEVENTS 507 select GPIO_SAMSUNG 508 select GPIOLIB 509 select GENERIC_IRQ_MULTI_HANDLER 510 select HAVE_S3C2410_I2C if I2C 511 select HAVE_S3C_RTC if RTC_CLASS 512 select NEED_MACH_IO_H 513 select S3C2410_WATCHDOG 514 select SAMSUNG_ATAGS 515 select USE_OF 516 select WATCHDOG 517 help 518 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 519 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 520 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 521 Samsung SMDK2410 development board (and derivatives). 522 523config ARCH_OMAP1 524 bool "TI OMAP1" 525 depends on MMU 526 select ARCH_OMAP 527 select CLKDEV_LOOKUP 528 select CLKSRC_MMIO 529 select GENERIC_CLOCKEVENTS 530 select GENERIC_IRQ_CHIP 531 select GENERIC_IRQ_MULTI_HANDLER 532 select GPIOLIB 533 select HAVE_IDE 534 select HAVE_LEGACY_CLK 535 select IRQ_DOMAIN 536 select NEED_MACH_IO_H if PCCARD 537 select NEED_MACH_MEMORY_H 538 select SPARSE_IRQ 539 help 540 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 541 542endchoice 543 544menu "Multiple platform selection" 545 depends on ARCH_MULTIPLATFORM 546 547comment "CPU Core family selection" 548 549config ARCH_MULTI_V4 550 bool "ARMv4 based platforms (FA526)" 551 depends on !ARCH_MULTI_V6_V7 552 select ARCH_MULTI_V4_V5 553 select CPU_FA526 554 555config ARCH_MULTI_V4T 556 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 557 depends on !ARCH_MULTI_V6_V7 558 select ARCH_MULTI_V4_V5 559 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 560 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 561 CPU_ARM925T || CPU_ARM940T) 562 563config ARCH_MULTI_V5 564 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 565 depends on !ARCH_MULTI_V6_V7 566 select ARCH_MULTI_V4_V5 567 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 568 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 569 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 570 571config ARCH_MULTI_V4_V5 572 bool 573 574config ARCH_MULTI_V6 575 bool "ARMv6 based platforms (ARM11)" 576 select ARCH_MULTI_V6_V7 577 select CPU_V6K 578 579config ARCH_MULTI_V7 580 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 581 default y 582 select ARCH_MULTI_V6_V7 583 select CPU_V7 584 select HAVE_SMP 585 586config ARCH_MULTI_V6_V7 587 bool 588 select MIGHT_HAVE_CACHE_L2X0 589 590config ARCH_MULTI_CPU_AUTO 591 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 592 select ARCH_MULTI_V5 593 594endmenu 595 596config ARCH_VIRT 597 bool "Dummy Virtual Machine" 598 depends on ARCH_MULTI_V7 599 select ARM_AMBA 600 select ARM_GIC 601 select ARM_GIC_V2M if PCI 602 select ARM_GIC_V3 603 select ARM_GIC_V3_ITS if PCI 604 select ARM_PSCI 605 select HAVE_ARM_ARCH_TIMER 606 select ARCH_SUPPORTS_BIG_ENDIAN 607 608# 609# This is sorted alphabetically by mach-* pathname. However, plat-* 610# Kconfigs may be included either alphabetically (according to the 611# plat- suffix) or along side the corresponding mach-* source. 612# 613source "arch/arm/mach-actions/Kconfig" 614 615source "arch/arm/mach-alpine/Kconfig" 616 617source "arch/arm/mach-artpec/Kconfig" 618 619source "arch/arm/mach-asm9260/Kconfig" 620 621source "arch/arm/mach-aspeed/Kconfig" 622 623source "arch/arm/mach-at91/Kconfig" 624 625source "arch/arm/mach-axxia/Kconfig" 626 627source "arch/arm/mach-bcm/Kconfig" 628 629source "arch/arm/mach-berlin/Kconfig" 630 631source "arch/arm/mach-clps711x/Kconfig" 632 633source "arch/arm/mach-cns3xxx/Kconfig" 634 635source "arch/arm/mach-davinci/Kconfig" 636 637source "arch/arm/mach-digicolor/Kconfig" 638 639source "arch/arm/mach-dove/Kconfig" 640 641source "arch/arm/mach-ep93xx/Kconfig" 642 643source "arch/arm/mach-exynos/Kconfig" 644 645source "arch/arm/mach-footbridge/Kconfig" 646 647source "arch/arm/mach-gemini/Kconfig" 648 649source "arch/arm/mach-highbank/Kconfig" 650 651source "arch/arm/mach-hisi/Kconfig" 652 653source "arch/arm/mach-imx/Kconfig" 654 655source "arch/arm/mach-integrator/Kconfig" 656 657source "arch/arm/mach-iop32x/Kconfig" 658 659source "arch/arm/mach-ixp4xx/Kconfig" 660 661source "arch/arm/mach-keystone/Kconfig" 662 663source "arch/arm/mach-lpc32xx/Kconfig" 664 665source "arch/arm/mach-mediatek/Kconfig" 666 667source "arch/arm/mach-meson/Kconfig" 668 669source "arch/arm/mach-milbeaut/Kconfig" 670 671source "arch/arm/mach-mmp/Kconfig" 672 673source "arch/arm/mach-moxart/Kconfig" 674 675source "arch/arm/mach-mstar/Kconfig" 676 677source "arch/arm/mach-mv78xx0/Kconfig" 678 679source "arch/arm/mach-mvebu/Kconfig" 680 681source "arch/arm/mach-mxs/Kconfig" 682 683source "arch/arm/mach-nomadik/Kconfig" 684 685source "arch/arm/mach-npcm/Kconfig" 686 687source "arch/arm/mach-nspire/Kconfig" 688 689source "arch/arm/plat-omap/Kconfig" 690 691source "arch/arm/mach-omap1/Kconfig" 692 693source "arch/arm/mach-omap2/Kconfig" 694 695source "arch/arm/mach-orion5x/Kconfig" 696 697source "arch/arm/mach-oxnas/Kconfig" 698 699source "arch/arm/mach-picoxcell/Kconfig" 700 701source "arch/arm/mach-prima2/Kconfig" 702 703source "arch/arm/mach-pxa/Kconfig" 704source "arch/arm/plat-pxa/Kconfig" 705 706source "arch/arm/mach-qcom/Kconfig" 707 708source "arch/arm/mach-rda/Kconfig" 709 710source "arch/arm/mach-realtek/Kconfig" 711 712source "arch/arm/mach-realview/Kconfig" 713 714source "arch/arm/mach-rockchip/Kconfig" 715 716source "arch/arm/mach-s3c/Kconfig" 717 718source "arch/arm/mach-s5pv210/Kconfig" 719 720source "arch/arm/mach-sa1100/Kconfig" 721 722source "arch/arm/mach-shmobile/Kconfig" 723 724source "arch/arm/mach-socfpga/Kconfig" 725 726source "arch/arm/mach-spear/Kconfig" 727 728source "arch/arm/mach-sti/Kconfig" 729 730source "arch/arm/mach-stm32/Kconfig" 731 732source "arch/arm/mach-sunxi/Kconfig" 733 734source "arch/arm/mach-tango/Kconfig" 735 736source "arch/arm/mach-tegra/Kconfig" 737 738source "arch/arm/mach-u300/Kconfig" 739 740source "arch/arm/mach-uniphier/Kconfig" 741 742source "arch/arm/mach-ux500/Kconfig" 743 744source "arch/arm/mach-versatile/Kconfig" 745 746source "arch/arm/mach-vexpress/Kconfig" 747 748source "arch/arm/mach-vt8500/Kconfig" 749 750source "arch/arm/mach-zx/Kconfig" 751 752source "arch/arm/mach-zynq/Kconfig" 753 754# ARMv7-M architecture 755config ARCH_EFM32 756 bool "Energy Micro efm32" 757 depends on ARM_SINGLE_ARMV7M 758 select GPIOLIB 759 help 760 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 761 processors. 762 763config ARCH_LPC18XX 764 bool "NXP LPC18xx/LPC43xx" 765 depends on ARM_SINGLE_ARMV7M 766 select ARCH_HAS_RESET_CONTROLLER 767 select ARM_AMBA 768 select CLKSRC_LPC32XX 769 select PINCTRL 770 help 771 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 772 high performance microcontrollers. 773 774config ARCH_MPS2 775 bool "ARM MPS2 platform" 776 depends on ARM_SINGLE_ARMV7M 777 select ARM_AMBA 778 select CLKSRC_MPS2 779 help 780 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 781 with a range of available cores like Cortex-M3/M4/M7. 782 783 Please, note that depends which Application Note is used memory map 784 for the platform may vary, so adjustment of RAM base might be needed. 785 786# Definitions to make life easier 787config ARCH_ACORN 788 bool 789 790config PLAT_IOP 791 bool 792 select GENERIC_CLOCKEVENTS 793 794config PLAT_ORION 795 bool 796 select CLKSRC_MMIO 797 select COMMON_CLK 798 select GENERIC_IRQ_CHIP 799 select IRQ_DOMAIN 800 801config PLAT_ORION_LEGACY 802 bool 803 select PLAT_ORION 804 805config PLAT_PXA 806 bool 807 808config PLAT_VERSATILE 809 bool 810 811source "arch/arm/mm/Kconfig" 812 813config IWMMXT 814 bool "Enable iWMMXt support" 815 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 816 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 817 help 818 Enable support for iWMMXt context switching at run time if 819 running on a CPU that supports it. 820 821if !MMU 822source "arch/arm/Kconfig-nommu" 823endif 824 825config PJ4B_ERRATA_4742 826 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 827 depends on CPU_PJ4B && MACH_ARMADA_370 828 default y 829 help 830 When coming out of either a Wait for Interrupt (WFI) or a Wait for 831 Event (WFE) IDLE states, a specific timing sensitivity exists between 832 the retiring WFI/WFE instructions and the newly issued subsequent 833 instructions. This sensitivity can result in a CPU hang scenario. 834 Workaround: 835 The software must insert either a Data Synchronization Barrier (DSB) 836 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 837 instruction 838 839config ARM_ERRATA_326103 840 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 841 depends on CPU_V6 842 help 843 Executing a SWP instruction to read-only memory does not set bit 11 844 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 845 treat the access as a read, preventing a COW from occurring and 846 causing the faulting task to livelock. 847 848config ARM_ERRATA_411920 849 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 850 depends on CPU_V6 || CPU_V6K 851 help 852 Invalidation of the Instruction Cache operation can 853 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 854 It does not affect the MPCore. This option enables the ARM Ltd. 855 recommended workaround. 856 857config ARM_ERRATA_430973 858 bool "ARM errata: Stale prediction on replaced interworking branch" 859 depends on CPU_V7 860 help 861 This option enables the workaround for the 430973 Cortex-A8 862 r1p* erratum. If a code sequence containing an ARM/Thumb 863 interworking branch is replaced with another code sequence at the 864 same virtual address, whether due to self-modifying code or virtual 865 to physical address re-mapping, Cortex-A8 does not recover from the 866 stale interworking branch prediction. This results in Cortex-A8 867 executing the new code sequence in the incorrect ARM or Thumb state. 868 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 869 and also flushes the branch target cache at every context switch. 870 Note that setting specific bits in the ACTLR register may not be 871 available in non-secure mode. 872 873config ARM_ERRATA_458693 874 bool "ARM errata: Processor deadlock when a false hazard is created" 875 depends on CPU_V7 876 depends on !ARCH_MULTIPLATFORM 877 help 878 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 879 erratum. For very specific sequences of memory operations, it is 880 possible for a hazard condition intended for a cache line to instead 881 be incorrectly associated with a different cache line. This false 882 hazard might then cause a processor deadlock. The workaround enables 883 the L1 caching of the NEON accesses and disables the PLD instruction 884 in the ACTLR register. Note that setting specific bits in the ACTLR 885 register may not be available in non-secure mode. 886 887config ARM_ERRATA_460075 888 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 889 depends on CPU_V7 890 depends on !ARCH_MULTIPLATFORM 891 help 892 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 893 erratum. Any asynchronous access to the L2 cache may encounter a 894 situation in which recent store transactions to the L2 cache are lost 895 and overwritten with stale memory contents from external memory. The 896 workaround disables the write-allocate mode for the L2 cache via the 897 ACTLR register. Note that setting specific bits in the ACTLR register 898 may not be available in non-secure mode. 899 900config ARM_ERRATA_742230 901 bool "ARM errata: DMB operation may be faulty" 902 depends on CPU_V7 && SMP 903 depends on !ARCH_MULTIPLATFORM 904 help 905 This option enables the workaround for the 742230 Cortex-A9 906 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 907 between two write operations may not ensure the correct visibility 908 ordering of the two writes. This workaround sets a specific bit in 909 the diagnostic register of the Cortex-A9 which causes the DMB 910 instruction to behave as a DSB, ensuring the correct behaviour of 911 the two writes. 912 913config ARM_ERRATA_742231 914 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 915 depends on CPU_V7 && SMP 916 depends on !ARCH_MULTIPLATFORM 917 help 918 This option enables the workaround for the 742231 Cortex-A9 919 (r2p0..r2p2) erratum. Under certain conditions, specific to the 920 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 921 accessing some data located in the same cache line, may get corrupted 922 data due to bad handling of the address hazard when the line gets 923 replaced from one of the CPUs at the same time as another CPU is 924 accessing it. This workaround sets specific bits in the diagnostic 925 register of the Cortex-A9 which reduces the linefill issuing 926 capabilities of the processor. 927 928config ARM_ERRATA_643719 929 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 930 depends on CPU_V7 && SMP 931 default y 932 help 933 This option enables the workaround for the 643719 Cortex-A9 (prior to 934 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 935 register returns zero when it should return one. The workaround 936 corrects this value, ensuring cache maintenance operations which use 937 it behave as intended and avoiding data corruption. 938 939config ARM_ERRATA_720789 940 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 941 depends on CPU_V7 942 help 943 This option enables the workaround for the 720789 Cortex-A9 (prior to 944 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 945 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 946 As a consequence of this erratum, some TLB entries which should be 947 invalidated are not, resulting in an incoherency in the system page 948 tables. The workaround changes the TLB flushing routines to invalidate 949 entries regardless of the ASID. 950 951config ARM_ERRATA_743622 952 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 953 depends on CPU_V7 954 depends on !ARCH_MULTIPLATFORM 955 help 956 This option enables the workaround for the 743622 Cortex-A9 957 (r2p*) erratum. Under very rare conditions, a faulty 958 optimisation in the Cortex-A9 Store Buffer may lead to data 959 corruption. This workaround sets a specific bit in the diagnostic 960 register of the Cortex-A9 which disables the Store Buffer 961 optimisation, preventing the defect from occurring. This has no 962 visible impact on the overall performance or power consumption of the 963 processor. 964 965config ARM_ERRATA_751472 966 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 967 depends on CPU_V7 968 depends on !ARCH_MULTIPLATFORM 969 help 970 This option enables the workaround for the 751472 Cortex-A9 (prior 971 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 972 completion of a following broadcasted operation if the second 973 operation is received by a CPU before the ICIALLUIS has completed, 974 potentially leading to corrupted entries in the cache or TLB. 975 976config ARM_ERRATA_754322 977 bool "ARM errata: possible faulty MMU translations following an ASID switch" 978 depends on CPU_V7 979 help 980 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 981 r3p*) erratum. A speculative memory access may cause a page table walk 982 which starts prior to an ASID switch but completes afterwards. This 983 can populate the micro-TLB with a stale entry which may be hit with 984 the new ASID. This workaround places two dsb instructions in the mm 985 switching code so that no page table walks can cross the ASID switch. 986 987config ARM_ERRATA_754327 988 bool "ARM errata: no automatic Store Buffer drain" 989 depends on CPU_V7 && SMP 990 help 991 This option enables the workaround for the 754327 Cortex-A9 (prior to 992 r2p0) erratum. The Store Buffer does not have any automatic draining 993 mechanism and therefore a livelock may occur if an external agent 994 continuously polls a memory location waiting to observe an update. 995 This workaround defines cpu_relax() as smp_mb(), preventing correctly 996 written polling loops from denying visibility of updates to memory. 997 998config ARM_ERRATA_364296 999 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1000 depends on CPU_V6 1001 help 1002 This options enables the workaround for the 364296 ARM1136 1003 r0p2 erratum (possible cache data corruption with 1004 hit-under-miss enabled). It sets the undocumented bit 31 in 1005 the auxiliary control register and the FI bit in the control 1006 register, thus disabling hit-under-miss without putting the 1007 processor into full low interrupt latency mode. ARM11MPCore 1008 is not affected. 1009 1010config ARM_ERRATA_764369 1011 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1012 depends on CPU_V7 && SMP 1013 help 1014 This option enables the workaround for erratum 764369 1015 affecting Cortex-A9 MPCore with two or more processors (all 1016 current revisions). Under certain timing circumstances, a data 1017 cache line maintenance operation by MVA targeting an Inner 1018 Shareable memory region may fail to proceed up to either the 1019 Point of Coherency or to the Point of Unification of the 1020 system. This workaround adds a DSB instruction before the 1021 relevant cache maintenance functions and sets a specific bit 1022 in the diagnostic control register of the SCU. 1023 1024config ARM_ERRATA_775420 1025 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1026 depends on CPU_V7 1027 help 1028 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1029 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1030 operation aborts with MMU exception, it might cause the processor 1031 to deadlock. This workaround puts DSB before executing ISB if 1032 an abort may occur on cache maintenance. 1033 1034config ARM_ERRATA_798181 1035 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1036 depends on CPU_V7 && SMP 1037 help 1038 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1039 adequately shooting down all use of the old entries. This 1040 option enables the Linux kernel workaround for this erratum 1041 which sends an IPI to the CPUs that are running the same ASID 1042 as the one being invalidated. 1043 1044config ARM_ERRATA_773022 1045 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1046 depends on CPU_V7 1047 help 1048 This option enables the workaround for the 773022 Cortex-A15 1049 (up to r0p4) erratum. In certain rare sequences of code, the 1050 loop buffer may deliver incorrect instructions. This 1051 workaround disables the loop buffer to avoid the erratum. 1052 1053config ARM_ERRATA_818325_852422 1054 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1055 depends on CPU_V7 1056 help 1057 This option enables the workaround for: 1058 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1059 instruction might deadlock. Fixed in r0p1. 1060 - Cortex-A12 852422: Execution of a sequence of instructions might 1061 lead to either a data corruption or a CPU deadlock. Not fixed in 1062 any Cortex-A12 cores yet. 1063 This workaround for all both errata involves setting bit[12] of the 1064 Feature Register. This bit disables an optimisation applied to a 1065 sequence of 2 instructions that use opposing condition codes. 1066 1067config ARM_ERRATA_821420 1068 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1069 depends on CPU_V7 1070 help 1071 This option enables the workaround for the 821420 Cortex-A12 1072 (all revs) erratum. In very rare timing conditions, a sequence 1073 of VMOV to Core registers instructions, for which the second 1074 one is in the shadow of a branch or abort, can lead to a 1075 deadlock when the VMOV instructions are issued out-of-order. 1076 1077config ARM_ERRATA_825619 1078 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1079 depends on CPU_V7 1080 help 1081 This option enables the workaround for the 825619 Cortex-A12 1082 (all revs) erratum. Within rare timing constraints, executing a 1083 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1084 and Device/Strongly-Ordered loads and stores might cause deadlock 1085 1086config ARM_ERRATA_857271 1087 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1088 depends on CPU_V7 1089 help 1090 This option enables the workaround for the 857271 Cortex-A12 1091 (all revs) erratum. Under very rare timing conditions, the CPU might 1092 hang. The workaround is expected to have a < 1% performance impact. 1093 1094config ARM_ERRATA_852421 1095 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1096 depends on CPU_V7 1097 help 1098 This option enables the workaround for the 852421 Cortex-A17 1099 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1100 execution of a DMB ST instruction might fail to properly order 1101 stores from GroupA and stores from GroupB. 1102 1103config ARM_ERRATA_852423 1104 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1105 depends on CPU_V7 1106 help 1107 This option enables the workaround for: 1108 - Cortex-A17 852423: Execution of a sequence of instructions might 1109 lead to either a data corruption or a CPU deadlock. Not fixed in 1110 any Cortex-A17 cores yet. 1111 This is identical to Cortex-A12 erratum 852422. It is a separate 1112 config option from the A12 erratum due to the way errata are checked 1113 for and handled. 1114 1115config ARM_ERRATA_857272 1116 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1117 depends on CPU_V7 1118 help 1119 This option enables the workaround for the 857272 Cortex-A17 erratum. 1120 This erratum is not known to be fixed in any A17 revision. 1121 This is identical to Cortex-A12 erratum 857271. It is a separate 1122 config option from the A12 erratum due to the way errata are checked 1123 for and handled. 1124 1125endmenu 1126 1127source "arch/arm/common/Kconfig" 1128 1129menu "Bus support" 1130 1131config ISA 1132 bool 1133 help 1134 Find out whether you have ISA slots on your motherboard. ISA is the 1135 name of a bus system, i.e. the way the CPU talks to the other stuff 1136 inside your box. Other bus systems are PCI, EISA, MicroChannel 1137 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1138 newer boards don't support it. If you have ISA, say Y, otherwise N. 1139 1140# Select ISA DMA controller support 1141config ISA_DMA 1142 bool 1143 select ISA_DMA_API 1144 1145# Select ISA DMA interface 1146config ISA_DMA_API 1147 bool 1148 1149config PCI_NANOENGINE 1150 bool "BSE nanoEngine PCI support" 1151 depends on SA1100_NANOENGINE 1152 help 1153 Enable PCI on the BSE nanoEngine board. 1154 1155config ARM_ERRATA_814220 1156 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1157 depends on CPU_V7 1158 help 1159 The v7 ARM states that all cache and branch predictor maintenance 1160 operations that do not specify an address execute, relative to 1161 each other, in program order. 1162 However, because of this erratum, an L2 set/way cache maintenance 1163 operation can overtake an L1 set/way cache maintenance operation. 1164 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1165 r0p4, r0p5. 1166 1167endmenu 1168 1169menu "Kernel Features" 1170 1171config HAVE_SMP 1172 bool 1173 help 1174 This option should be selected by machines which have an SMP- 1175 capable CPU. 1176 1177 The only effect of this option is to make the SMP-related 1178 options available to the user for configuration. 1179 1180config SMP 1181 bool "Symmetric Multi-Processing" 1182 depends on CPU_V6K || CPU_V7 1183 depends on GENERIC_CLOCKEVENTS 1184 depends on HAVE_SMP 1185 depends on MMU || ARM_MPU 1186 select IRQ_WORK 1187 help 1188 This enables support for systems with more than one CPU. If you have 1189 a system with only one CPU, say N. If you have a system with more 1190 than one CPU, say Y. 1191 1192 If you say N here, the kernel will run on uni- and multiprocessor 1193 machines, but will use only one CPU of a multiprocessor machine. If 1194 you say Y here, the kernel will run on many, but not all, 1195 uniprocessor machines. On a uniprocessor machine, the kernel 1196 will run faster if you say N here. 1197 1198 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1199 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1200 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1201 1202 If you don't know what to do here, say N. 1203 1204config SMP_ON_UP 1205 bool "Allow booting SMP kernel on uniprocessor systems" 1206 depends on SMP && !XIP_KERNEL && MMU 1207 default y 1208 help 1209 SMP kernels contain instructions which fail on non-SMP processors. 1210 Enabling this option allows the kernel to modify itself to make 1211 these instructions safe. Disabling it allows about 1K of space 1212 savings. 1213 1214 If you don't know what to do here, say Y. 1215 1216config ARM_CPU_TOPOLOGY 1217 bool "Support cpu topology definition" 1218 depends on SMP && CPU_V7 1219 default y 1220 help 1221 Support ARM cpu topology definition. The MPIDR register defines 1222 affinity between processors which is then used to describe the cpu 1223 topology of an ARM System. 1224 1225config SCHED_MC 1226 bool "Multi-core scheduler support" 1227 depends on ARM_CPU_TOPOLOGY 1228 help 1229 Multi-core scheduler support improves the CPU scheduler's decision 1230 making when dealing with multi-core CPU chips at a cost of slightly 1231 increased overhead in some places. If unsure say N here. 1232 1233config SCHED_SMT 1234 bool "SMT scheduler support" 1235 depends on ARM_CPU_TOPOLOGY 1236 help 1237 Improves the CPU scheduler's decision making when dealing with 1238 MultiThreading at a cost of slightly increased overhead in some 1239 places. If unsure say N here. 1240 1241config HAVE_ARM_SCU 1242 bool 1243 help 1244 This option enables support for the ARM snoop control unit 1245 1246config HAVE_ARM_ARCH_TIMER 1247 bool "Architected timer support" 1248 depends on CPU_V7 1249 select ARM_ARCH_TIMER 1250 help 1251 This option enables support for the ARM architected timer 1252 1253config HAVE_ARM_TWD 1254 bool 1255 help 1256 This options enables support for the ARM timer and watchdog unit 1257 1258config MCPM 1259 bool "Multi-Cluster Power Management" 1260 depends on CPU_V7 && SMP 1261 help 1262 This option provides the common power management infrastructure 1263 for (multi-)cluster based systems, such as big.LITTLE based 1264 systems. 1265 1266config MCPM_QUAD_CLUSTER 1267 bool 1268 depends on MCPM 1269 help 1270 To avoid wasting resources unnecessarily, MCPM only supports up 1271 to 2 clusters by default. 1272 Platforms with 3 or 4 clusters that use MCPM must select this 1273 option to allow the additional clusters to be managed. 1274 1275config BIG_LITTLE 1276 bool "big.LITTLE support (Experimental)" 1277 depends on CPU_V7 && SMP 1278 select MCPM 1279 help 1280 This option enables support selections for the big.LITTLE 1281 system architecture. 1282 1283config BL_SWITCHER 1284 bool "big.LITTLE switcher support" 1285 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1286 select CPU_PM 1287 help 1288 The big.LITTLE "switcher" provides the core functionality to 1289 transparently handle transition between a cluster of A15's 1290 and a cluster of A7's in a big.LITTLE system. 1291 1292config BL_SWITCHER_DUMMY_IF 1293 tristate "Simple big.LITTLE switcher user interface" 1294 depends on BL_SWITCHER && DEBUG_KERNEL 1295 help 1296 This is a simple and dummy char dev interface to control 1297 the big.LITTLE switcher core code. It is meant for 1298 debugging purposes only. 1299 1300choice 1301 prompt "Memory split" 1302 depends on MMU 1303 default VMSPLIT_3G 1304 help 1305 Select the desired split between kernel and user memory. 1306 1307 If you are not absolutely sure what you are doing, leave this 1308 option alone! 1309 1310 config VMSPLIT_3G 1311 bool "3G/1G user/kernel split" 1312 config VMSPLIT_3G_OPT 1313 depends on !ARM_LPAE 1314 bool "3G/1G user/kernel split (for full 1G low memory)" 1315 config VMSPLIT_2G 1316 bool "2G/2G user/kernel split" 1317 config VMSPLIT_1G 1318 bool "1G/3G user/kernel split" 1319endchoice 1320 1321config PAGE_OFFSET 1322 hex 1323 default PHYS_OFFSET if !MMU 1324 default 0x40000000 if VMSPLIT_1G 1325 default 0x80000000 if VMSPLIT_2G 1326 default 0xB0000000 if VMSPLIT_3G_OPT 1327 default 0xC0000000 1328 1329config KASAN_SHADOW_OFFSET 1330 hex 1331 depends on KASAN 1332 default 0x1f000000 if PAGE_OFFSET=0x40000000 1333 default 0x5f000000 if PAGE_OFFSET=0x80000000 1334 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1335 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1336 default 0xffffffff 1337 1338config NR_CPUS 1339 int "Maximum number of CPUs (2-32)" 1340 range 2 32 1341 depends on SMP 1342 default "4" 1343 1344config HOTPLUG_CPU 1345 bool "Support for hot-pluggable CPUs" 1346 depends on SMP 1347 select GENERIC_IRQ_MIGRATION 1348 help 1349 Say Y here to experiment with turning CPUs off and on. CPUs 1350 can be controlled through /sys/devices/system/cpu. 1351 1352config ARM_PSCI 1353 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1354 depends on HAVE_ARM_SMCCC 1355 select ARM_PSCI_FW 1356 help 1357 Say Y here if you want Linux to communicate with system firmware 1358 implementing the PSCI specification for CPU-centric power 1359 management operations described in ARM document number ARM DEN 1360 0022A ("Power State Coordination Interface System Software on 1361 ARM processors"). 1362 1363# The GPIO number here must be sorted by descending number. In case of 1364# a multiplatform kernel, we just want the highest value required by the 1365# selected platforms. 1366config ARCH_NR_GPIO 1367 int 1368 default 2048 if ARCH_SOCFPGA 1369 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1370 ARCH_ZYNQ || ARCH_ASPEED 1371 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1372 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1373 default 416 if ARCH_SUNXI 1374 default 392 if ARCH_U8500 1375 default 352 if ARCH_VT8500 1376 default 288 if ARCH_ROCKCHIP 1377 default 264 if MACH_H4700 1378 default 0 1379 help 1380 Maximum number of GPIOs in the system. 1381 1382 If unsure, leave the default value. 1383 1384config HZ_FIXED 1385 int 1386 default 200 if ARCH_EBSA110 1387 default 128 if SOC_AT91RM9200 1388 default 0 1389 1390choice 1391 depends on HZ_FIXED = 0 1392 prompt "Timer frequency" 1393 1394config HZ_100 1395 bool "100 Hz" 1396 1397config HZ_200 1398 bool "200 Hz" 1399 1400config HZ_250 1401 bool "250 Hz" 1402 1403config HZ_300 1404 bool "300 Hz" 1405 1406config HZ_500 1407 bool "500 Hz" 1408 1409config HZ_1000 1410 bool "1000 Hz" 1411 1412endchoice 1413 1414config HZ 1415 int 1416 default HZ_FIXED if HZ_FIXED != 0 1417 default 100 if HZ_100 1418 default 200 if HZ_200 1419 default 250 if HZ_250 1420 default 300 if HZ_300 1421 default 500 if HZ_500 1422 default 1000 1423 1424config SCHED_HRTICK 1425 def_bool HIGH_RES_TIMERS 1426 1427config THUMB2_KERNEL 1428 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1429 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1430 default y if CPU_THUMBONLY 1431 select ARM_UNWIND 1432 help 1433 By enabling this option, the kernel will be compiled in 1434 Thumb-2 mode. 1435 1436 If unsure, say N. 1437 1438config ARM_PATCH_IDIV 1439 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1440 depends on CPU_32v7 && !XIP_KERNEL 1441 default y 1442 help 1443 The ARM compiler inserts calls to __aeabi_idiv() and 1444 __aeabi_uidiv() when it needs to perform division on signed 1445 and unsigned integers. Some v7 CPUs have support for the sdiv 1446 and udiv instructions that can be used to implement those 1447 functions. 1448 1449 Enabling this option allows the kernel to modify itself to 1450 replace the first two instructions of these library functions 1451 with the sdiv or udiv plus "bx lr" instructions when the CPU 1452 it is running on supports them. Typically this will be faster 1453 and less power intensive than running the original library 1454 code to do integer division. 1455 1456config AEABI 1457 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1458 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1459 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1460 help 1461 This option allows for the kernel to be compiled using the latest 1462 ARM ABI (aka EABI). This is only useful if you are using a user 1463 space environment that is also compiled with EABI. 1464 1465 Since there are major incompatibilities between the legacy ABI and 1466 EABI, especially with regard to structure member alignment, this 1467 option also changes the kernel syscall calling convention to 1468 disambiguate both ABIs and allow for backward compatibility support 1469 (selected with CONFIG_OABI_COMPAT). 1470 1471 To use this you need GCC version 4.0.0 or later. 1472 1473config OABI_COMPAT 1474 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1475 depends on AEABI && !THUMB2_KERNEL 1476 help 1477 This option preserves the old syscall interface along with the 1478 new (ARM EABI) one. It also provides a compatibility layer to 1479 intercept syscalls that have structure arguments which layout 1480 in memory differs between the legacy ABI and the new ARM EABI 1481 (only for non "thumb" binaries). This option adds a tiny 1482 overhead to all syscalls and produces a slightly larger kernel. 1483 1484 The seccomp filter system will not be available when this is 1485 selected, since there is no way yet to sensibly distinguish 1486 between calling conventions during filtering. 1487 1488 If you know you'll be using only pure EABI user space then you 1489 can say N here. If this option is not selected and you attempt 1490 to execute a legacy ABI binary then the result will be 1491 UNPREDICTABLE (in fact it can be predicted that it won't work 1492 at all). If in doubt say N. 1493 1494config ARCH_SELECT_MEMORY_MODEL 1495 bool 1496 1497config ARCH_FLATMEM_ENABLE 1498 bool 1499 1500config ARCH_SPARSEMEM_ENABLE 1501 bool 1502 select SPARSEMEM_STATIC if SPARSEMEM 1503 1504config HAVE_ARCH_PFN_VALID 1505 def_bool y 1506 1507config HIGHMEM 1508 bool "High Memory Support" 1509 depends on MMU 1510 help 1511 The address space of ARM processors is only 4 Gigabytes large 1512 and it has to accommodate user address space, kernel address 1513 space as well as some memory mapped IO. That means that, if you 1514 have a large amount of physical memory and/or IO, not all of the 1515 memory can be "permanently mapped" by the kernel. The physical 1516 memory that is not permanently mapped is called "high memory". 1517 1518 Depending on the selected kernel/user memory split, minimum 1519 vmalloc space and actual amount of RAM, you may not need this 1520 option which should result in a slightly faster kernel. 1521 1522 If unsure, say n. 1523 1524config HIGHPTE 1525 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1526 depends on HIGHMEM 1527 default y 1528 help 1529 The VM uses one page of physical memory for each page table. 1530 For systems with a lot of processes, this can use a lot of 1531 precious low memory, eventually leading to low memory being 1532 consumed by page tables. Setting this option will allow 1533 user-space 2nd level page tables to reside in high memory. 1534 1535config CPU_SW_DOMAIN_PAN 1536 bool "Enable use of CPU domains to implement privileged no-access" 1537 depends on MMU && !ARM_LPAE 1538 default y 1539 help 1540 Increase kernel security by ensuring that normal kernel accesses 1541 are unable to access userspace addresses. This can help prevent 1542 use-after-free bugs becoming an exploitable privilege escalation 1543 by ensuring that magic values (such as LIST_POISON) will always 1544 fault when dereferenced. 1545 1546 CPUs with low-vector mappings use a best-efforts implementation. 1547 Their lower 1MB needs to remain accessible for the vectors, but 1548 the remainder of userspace will become appropriately inaccessible. 1549 1550config HW_PERF_EVENTS 1551 def_bool y 1552 depends on ARM_PMU 1553 1554config SYS_SUPPORTS_HUGETLBFS 1555 def_bool y 1556 depends on ARM_LPAE 1557 1558config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1559 def_bool y 1560 depends on ARM_LPAE 1561 1562config ARCH_WANT_GENERAL_HUGETLB 1563 def_bool y 1564 1565config ARM_MODULE_PLTS 1566 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1567 depends on MODULES 1568 default y 1569 help 1570 Allocate PLTs when loading modules so that jumps and calls whose 1571 targets are too far away for their relative offsets to be encoded 1572 in the instructions themselves can be bounced via veneers in the 1573 module's PLT. This allows modules to be allocated in the generic 1574 vmalloc area after the dedicated module memory area has been 1575 exhausted. The modules will use slightly more memory, but after 1576 rounding up to page size, the actual memory footprint is usually 1577 the same. 1578 1579 Disabling this is usually safe for small single-platform 1580 configurations. If unsure, say y. 1581 1582config FORCE_MAX_ZONEORDER 1583 int "Maximum zone order" 1584 default "12" if SOC_AM33XX 1585 default "9" if SA1111 || ARCH_EFM32 1586 default "11" 1587 help 1588 The kernel memory allocator divides physically contiguous memory 1589 blocks into "zones", where each zone is a power of two number of 1590 pages. This option selects the largest power of two that the kernel 1591 keeps in the memory allocator. If you need to allocate very large 1592 blocks of physically contiguous memory, then you may need to 1593 increase this value. 1594 1595 This config option is actually maximum order plus one. For example, 1596 a value of 11 means that the largest free memory block is 2^10 pages. 1597 1598config ALIGNMENT_TRAP 1599 bool 1600 depends on CPU_CP15_MMU 1601 default y if !ARCH_EBSA110 1602 select HAVE_PROC_CPU if PROC_FS 1603 help 1604 ARM processors cannot fetch/store information which is not 1605 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1606 address divisible by 4. On 32-bit ARM processors, these non-aligned 1607 fetch/store instructions will be emulated in software if you say 1608 here, which has a severe performance impact. This is necessary for 1609 correct operation of some network protocols. With an IP-only 1610 configuration it is safe to say N, otherwise say Y. 1611 1612config UACCESS_WITH_MEMCPY 1613 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1614 depends on MMU 1615 default y if CPU_FEROCEON 1616 help 1617 Implement faster copy_to_user and clear_user methods for CPU 1618 cores where a 8-word STM instruction give significantly higher 1619 memory write throughput than a sequence of individual 32bit stores. 1620 1621 A possible side effect is a slight increase in scheduling latency 1622 between threads sharing the same address space if they invoke 1623 such copy operations with large buffers. 1624 1625 However, if the CPU data cache is using a write-allocate mode, 1626 this option is unlikely to provide any performance gain. 1627 1628config PARAVIRT 1629 bool "Enable paravirtualization code" 1630 help 1631 This changes the kernel so it can modify itself when it is run 1632 under a hypervisor, potentially improving performance significantly 1633 over full virtualization. 1634 1635config PARAVIRT_TIME_ACCOUNTING 1636 bool "Paravirtual steal time accounting" 1637 select PARAVIRT 1638 help 1639 Select this option to enable fine granularity task steal time 1640 accounting. Time spent executing other tasks in parallel with 1641 the current vCPU is discounted from the vCPU power. To account for 1642 that, there can be a small performance impact. 1643 1644 If in doubt, say N here. 1645 1646config XEN_DOM0 1647 def_bool y 1648 depends on XEN 1649 1650config XEN 1651 bool "Xen guest support on ARM" 1652 depends on ARM && AEABI && OF 1653 depends on CPU_V7 && !CPU_V6 1654 depends on !GENERIC_ATOMIC64 1655 depends on MMU 1656 select ARCH_DMA_ADDR_T_64BIT 1657 select ARM_PSCI 1658 select SWIOTLB 1659 select SWIOTLB_XEN 1660 select PARAVIRT 1661 help 1662 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1663 1664config STACKPROTECTOR_PER_TASK 1665 bool "Use a unique stack canary value for each task" 1666 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1667 select GCC_PLUGIN_ARM_SSP_PER_TASK 1668 default y 1669 help 1670 Due to the fact that GCC uses an ordinary symbol reference from 1671 which to load the value of the stack canary, this value can only 1672 change at reboot time on SMP systems, and all tasks running in the 1673 kernel's address space are forced to use the same canary value for 1674 the entire duration that the system is up. 1675 1676 Enable this option to switch to a different method that uses a 1677 different canary value for each task. 1678 1679config RELOCATABLE 1680 bool 1681 depends on !XIP_KERNEL && !JUMP_LABEL 1682 select HAVE_ARCH_PREL32_RELOCATIONS 1683 1684config RANDOMIZE_BASE 1685 bool "Randomize the address of the kernel image" 1686 depends on MMU && AUTO_ZRELADDR 1687 depends on !XIP_KERNEL && !ZBOOT_ROM && !JUMP_LABEL 1688 select RELOCATABLE 1689 select ARM_MODULE_PLTS if MODULES 1690 select MODULE_REL_CRCS if MODVERSIONS 1691 help 1692 Randomizes the virtual and physical address at which the kernel 1693 image is loaded, as a security feature that deters exploit attempts 1694 relying on knowledge of the location of kernel internals. 1695 1696endmenu 1697 1698menu "Boot options" 1699 1700config USE_OF 1701 bool "Flattened Device Tree support" 1702 select IRQ_DOMAIN 1703 select OF 1704 help 1705 Include support for flattened device tree machine descriptions. 1706 1707config ATAGS 1708 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1709 default y 1710 help 1711 This is the traditional way of passing data to the kernel at boot 1712 time. If you are solely relying on the flattened device tree (or 1713 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1714 to remove ATAGS support from your kernel binary. If unsure, 1715 leave this to y. 1716 1717config DEPRECATED_PARAM_STRUCT 1718 bool "Provide old way to pass kernel parameters" 1719 depends on ATAGS 1720 help 1721 This was deprecated in 2001 and announced to live on for 5 years. 1722 Some old boot loaders still use this way. 1723 1724# Compressed boot loader in ROM. Yes, we really want to ask about 1725# TEXT and BSS so we preserve their values in the config files. 1726config ZBOOT_ROM_TEXT 1727 hex "Compressed ROM boot loader base address" 1728 default 0x0 1729 help 1730 The physical address at which the ROM-able zImage is to be 1731 placed in the target. Platforms which normally make use of 1732 ROM-able zImage formats normally set this to a suitable 1733 value in their defconfig file. 1734 1735 If ZBOOT_ROM is not enabled, this has no effect. 1736 1737config ZBOOT_ROM_BSS 1738 hex "Compressed ROM boot loader BSS address" 1739 default 0x0 1740 help 1741 The base address of an area of read/write memory in the target 1742 for the ROM-able zImage which must be available while the 1743 decompressor is running. It must be large enough to hold the 1744 entire decompressed kernel plus an additional 128 KiB. 1745 Platforms which normally make use of ROM-able zImage formats 1746 normally set this to a suitable value in their defconfig file. 1747 1748 If ZBOOT_ROM is not enabled, this has no effect. 1749 1750config ZBOOT_ROM 1751 bool "Compressed boot loader in ROM/flash" 1752 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1753 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1754 help 1755 Say Y here if you intend to execute your compressed kernel image 1756 (zImage) directly from ROM or flash. If unsure, say N. 1757 1758config ARM_APPENDED_DTB 1759 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1760 depends on OF 1761 help 1762 With this option, the boot code will look for a device tree binary 1763 (DTB) appended to zImage 1764 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1765 1766 This is meant as a backward compatibility convenience for those 1767 systems with a bootloader that can't be upgraded to accommodate 1768 the documented boot protocol using a device tree. 1769 1770 Beware that there is very little in terms of protection against 1771 this option being confused by leftover garbage in memory that might 1772 look like a DTB header after a reboot if no actual DTB is appended 1773 to zImage. Do not leave this option active in a production kernel 1774 if you don't intend to always append a DTB. Proper passing of the 1775 location into r2 of a bootloader provided DTB is always preferable 1776 to this option. 1777 1778config ARM_ATAG_DTB_COMPAT 1779 bool "Supplement the appended DTB with traditional ATAG information" 1780 depends on ARM_APPENDED_DTB 1781 help 1782 Some old bootloaders can't be updated to a DTB capable one, yet 1783 they provide ATAGs with memory configuration, the ramdisk address, 1784 the kernel cmdline string, etc. Such information is dynamically 1785 provided by the bootloader and can't always be stored in a static 1786 DTB. To allow a device tree enabled kernel to be used with such 1787 bootloaders, this option allows zImage to extract the information 1788 from the ATAG list and store it at run time into the appended DTB. 1789 1790choice 1791 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1792 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1793 1794config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1795 bool "Use bootloader kernel arguments if available" 1796 help 1797 Uses the command-line options passed by the boot loader instead of 1798 the device tree bootargs property. If the boot loader doesn't provide 1799 any, the device tree bootargs property will be used. 1800 1801config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1802 bool "Extend with bootloader kernel arguments" 1803 help 1804 The command-line arguments provided by the boot loader will be 1805 appended to the the device tree bootargs property. 1806 1807endchoice 1808 1809config CMDLINE 1810 string "Default kernel command string" 1811 default "" 1812 help 1813 On some architectures (EBSA110 and CATS), there is currently no way 1814 for the boot loader to pass arguments to the kernel. For these 1815 architectures, you should supply some command-line options at build 1816 time by entering them here. As a minimum, you should specify the 1817 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1818 1819choice 1820 prompt "Kernel command line type" if CMDLINE != "" 1821 default CMDLINE_FROM_BOOTLOADER 1822 1823config CMDLINE_FROM_BOOTLOADER 1824 bool "Use bootloader kernel arguments if available" 1825 help 1826 Uses the command-line options passed by the boot loader. If 1827 the boot loader doesn't provide any, the default kernel command 1828 string provided in CMDLINE will be used. 1829 1830config CMDLINE_EXTEND 1831 bool "Extend bootloader kernel arguments" 1832 help 1833 The command-line arguments provided by the boot loader will be 1834 appended to the default kernel command string. 1835 1836config CMDLINE_FORCE 1837 bool "Always use the default kernel command string" 1838 help 1839 Always use the default kernel command string, even if the boot 1840 loader passes other arguments to the kernel. 1841 This is useful if you cannot or don't want to change the 1842 command-line options your boot loader passes to the kernel. 1843endchoice 1844 1845config XIP_KERNEL 1846 bool "Kernel Execute-In-Place from ROM" 1847 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1848 help 1849 Execute-In-Place allows the kernel to run from non-volatile storage 1850 directly addressable by the CPU, such as NOR flash. This saves RAM 1851 space since the text section of the kernel is not loaded from flash 1852 to RAM. Read-write sections, such as the data section and stack, 1853 are still copied to RAM. The XIP kernel is not compressed since 1854 it has to run directly from flash, so it will take more space to 1855 store it. The flash address used to link the kernel object files, 1856 and for storing it, is configuration dependent. Therefore, if you 1857 say Y here, you must know the proper physical address where to 1858 store the kernel image depending on your own flash memory usage. 1859 1860 Also note that the make target becomes "make xipImage" rather than 1861 "make zImage" or "make Image". The final kernel binary to put in 1862 ROM memory will be arch/arm/boot/xipImage. 1863 1864 If unsure, say N. 1865 1866config XIP_PHYS_ADDR 1867 hex "XIP Kernel Physical Location" 1868 depends on XIP_KERNEL 1869 default "0x00080000" 1870 help 1871 This is the physical address in your flash memory the kernel will 1872 be linked for and stored to. This address is dependent on your 1873 own flash usage. 1874 1875config XIP_DEFLATED_DATA 1876 bool "Store kernel .data section compressed in ROM" 1877 depends on XIP_KERNEL 1878 select ZLIB_INFLATE 1879 help 1880 Before the kernel is actually executed, its .data section has to be 1881 copied to RAM from ROM. This option allows for storing that data 1882 in compressed form and decompressed to RAM rather than merely being 1883 copied, saving some precious ROM space. A possible drawback is a 1884 slightly longer boot delay. 1885 1886config KEXEC 1887 bool "Kexec system call (EXPERIMENTAL)" 1888 depends on (!SMP || PM_SLEEP_SMP) 1889 depends on MMU 1890 select KEXEC_CORE 1891 help 1892 kexec is a system call that implements the ability to shutdown your 1893 current kernel, and to start another kernel. It is like a reboot 1894 but it is independent of the system firmware. And like a reboot 1895 you can start any kernel with it, not just Linux. 1896 1897 It is an ongoing process to be certain the hardware in a machine 1898 is properly shutdown, so do not be surprised if this code does not 1899 initially work for you. 1900 1901config ATAGS_PROC 1902 bool "Export atags in procfs" 1903 depends on ATAGS && KEXEC 1904 default y 1905 help 1906 Should the atags used to boot the kernel be exported in an "atags" 1907 file in procfs. Useful with kexec. 1908 1909config CRASH_DUMP 1910 bool "Build kdump crash kernel (EXPERIMENTAL)" 1911 help 1912 Generate crash dump after being started by kexec. This should 1913 be normally only set in special crash dump kernels which are 1914 loaded in the main kernel with kexec-tools into a specially 1915 reserved region and then later executed after a crash by 1916 kdump/kexec. The crash dump kernel must be compiled to a 1917 memory address not used by the main kernel 1918 1919 For more details see Documentation/admin-guide/kdump/kdump.rst 1920 1921config AUTO_ZRELADDR 1922 bool "Auto calculation of the decompressed kernel image address" 1923 help 1924 ZRELADDR is the physical address where the decompressed kernel 1925 image will be placed. If AUTO_ZRELADDR is selected, the address 1926 will be determined at run-time by masking the current IP with 1927 0xf8000000. This assumes the zImage being placed in the first 128MB 1928 from start of memory. 1929 1930config EFI_STUB 1931 bool 1932 1933config EFI 1934 bool "UEFI runtime support" 1935 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1936 select UCS2_STRING 1937 select EFI_PARAMS_FROM_FDT 1938 select EFI_STUB 1939 select EFI_GENERIC_STUB 1940 select EFI_RUNTIME_WRAPPERS 1941 help 1942 This option provides support for runtime services provided 1943 by UEFI firmware (such as non-volatile variables, realtime 1944 clock, and platform reset). A UEFI stub is also provided to 1945 allow the kernel to be booted as an EFI application. This 1946 is only useful for kernels that may run on systems that have 1947 UEFI firmware. 1948 1949config DMI 1950 bool "Enable support for SMBIOS (DMI) tables" 1951 depends on EFI 1952 default y 1953 help 1954 This enables SMBIOS/DMI feature for systems. 1955 1956 This option is only useful on systems that have UEFI firmware. 1957 However, even with this option, the resultant kernel should 1958 continue to boot on existing non-UEFI platforms. 1959 1960 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1961 i.e., the the practice of identifying the platform via DMI to 1962 decide whether certain workarounds for buggy hardware and/or 1963 firmware need to be enabled. This would require the DMI subsystem 1964 to be enabled much earlier than we do on ARM, which is non-trivial. 1965 1966endmenu 1967 1968menu "CPU Power Management" 1969 1970source "drivers/cpufreq/Kconfig" 1971 1972source "drivers/cpuidle/Kconfig" 1973 1974endmenu 1975 1976menu "Floating point emulation" 1977 1978comment "At least one emulation must be selected" 1979 1980config FPE_NWFPE 1981 bool "NWFPE math emulation" 1982 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1983 help 1984 Say Y to include the NWFPE floating point emulator in the kernel. 1985 This is necessary to run most binaries. Linux does not currently 1986 support floating point hardware so you need to say Y here even if 1987 your machine has an FPA or floating point co-processor podule. 1988 1989 You may say N here if you are going to load the Acorn FPEmulator 1990 early in the bootup. 1991 1992config FPE_NWFPE_XP 1993 bool "Support extended precision" 1994 depends on FPE_NWFPE 1995 help 1996 Say Y to include 80-bit support in the kernel floating-point 1997 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1998 Note that gcc does not generate 80-bit operations by default, 1999 so in most cases this option only enlarges the size of the 2000 floating point emulator without any good reason. 2001 2002 You almost surely want to say N here. 2003 2004config FPE_FASTFPE 2005 bool "FastFPE math emulation (EXPERIMENTAL)" 2006 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2007 help 2008 Say Y here to include the FAST floating point emulator in the kernel. 2009 This is an experimental much faster emulator which now also has full 2010 precision for the mantissa. It does not support any exceptions. 2011 It is very simple, and approximately 3-6 times faster than NWFPE. 2012 2013 It should be sufficient for most programs. It may be not suitable 2014 for scientific calculations, but you have to check this for yourself. 2015 If you do not feel you need a faster FP emulation you should better 2016 choose NWFPE. 2017 2018config VFP 2019 bool "VFP-format floating point maths" 2020 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2021 help 2022 Say Y to include VFP support code in the kernel. This is needed 2023 if your hardware includes a VFP unit. 2024 2025 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2026 release notes and additional status information. 2027 2028 Say N if your target does not have VFP hardware. 2029 2030config VFPv3 2031 bool 2032 depends on VFP 2033 default y if CPU_V7 2034 2035config NEON 2036 bool "Advanced SIMD (NEON) Extension support" 2037 depends on VFPv3 && CPU_V7 2038 help 2039 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2040 Extension. 2041 2042config KERNEL_MODE_NEON 2043 bool "Support for NEON in kernel mode" 2044 depends on NEON && AEABI 2045 help 2046 Say Y to include support for NEON in kernel mode. 2047 2048endmenu 2049 2050menu "Power management options" 2051 2052source "kernel/power/Kconfig" 2053 2054config ARCH_SUSPEND_POSSIBLE 2055 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2056 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2057 def_bool y 2058 2059config ARM_CPU_SUSPEND 2060 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2061 depends on ARCH_SUSPEND_POSSIBLE 2062 2063config ARCH_HIBERNATION_POSSIBLE 2064 bool 2065 depends on MMU 2066 default y if ARCH_SUSPEND_POSSIBLE 2067 2068endmenu 2069 2070source "drivers/firmware/Kconfig" 2071 2072if CRYPTO 2073source "arch/arm/crypto/Kconfig" 2074endif 2075 2076source "arch/arm/Kconfig.assembler" 2077