1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #ifndef IRIS_SCREEN_H
24 #define IRIS_SCREEN_H
25
26 #include "pipe/p_screen.h"
27 #include "frontend/drm_driver.h"
28 #include "util/disk_cache.h"
29 #include "util/slab.h"
30 #include "util/u_screen.h"
31 #include "intel/dev/intel_device_info.h"
32 #include "intel/isl/isl.h"
33 #include "iris_bufmgr.h"
34 #include "iris_binder.h"
35 #include "iris_measure.h"
36 #include "iris_resource.h"
37
38 struct intel_l3_config;
39 struct brw_vue_map;
40 struct iris_vs_prog_key;
41 struct iris_tcs_prog_key;
42 struct iris_tes_prog_key;
43 struct iris_gs_prog_key;
44 struct iris_fs_prog_key;
45 struct iris_cs_prog_key;
46 enum iris_program_cache_id;
47
48 struct u_trace;
49
50 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
51 #define WRITE_ONCE(x, v) *(volatile __typeof__(x) *)&(x) = (v)
52
53 #define IRIS_MAX_TEXTURE_SAMPLERS 32
54 #define IRIS_MAX_SOL_BUFFERS 4
55 #define IRIS_MAP_BUFFER_ALIGNMENT 64
56
57 /**
58 * Virtual table for generation-specific (genxml) function calls.
59 */
60 struct iris_vtable {
61 void (*destroy_state)(struct iris_context *ice);
62 void (*init_render_context)(struct iris_batch *batch);
63 void (*init_compute_context)(struct iris_batch *batch);
64 void (*upload_render_state)(struct iris_context *ice,
65 struct iris_batch *batch,
66 const struct pipe_draw_info *draw,
67 unsigned drawid_offset,
68 const struct pipe_draw_indirect_info *indirect,
69 const struct pipe_draw_start_count_bias *sc);
70 void (*update_binder_address)(struct iris_batch *batch,
71 struct iris_binder *binder);
72 void (*upload_compute_state)(struct iris_context *ice,
73 struct iris_batch *batch,
74 const struct pipe_grid_info *grid);
75 void (*rebind_buffer)(struct iris_context *ice,
76 struct iris_resource *res);
77 void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
78 uint32_t src);
79 void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
80 uint32_t src);
81 void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
82 uint32_t val);
83 void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
84 uint64_t val);
85 void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
86 struct iris_bo *bo, uint32_t offset);
87 void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
88 struct iris_bo *bo, uint32_t offset);
89 void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
90 struct iris_bo *bo, uint32_t offset,
91 bool predicated);
92 void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
93 struct iris_bo *bo, uint32_t offset,
94 bool predicated);
95 void (*store_data_imm32)(struct iris_batch *batch,
96 struct iris_bo *bo, uint32_t offset,
97 uint32_t value);
98 void (*store_data_imm64)(struct iris_batch *batch,
99 struct iris_bo *bo, uint32_t offset,
100 uint64_t value);
101 void (*copy_mem_mem)(struct iris_batch *batch,
102 struct iris_bo *dst_bo, uint32_t dst_offset,
103 struct iris_bo *src_bo, uint32_t src_offset,
104 unsigned bytes);
105 void (*emit_raw_pipe_control)(struct iris_batch *batch,
106 const char *reason, uint32_t flags,
107 struct iris_bo *bo, uint32_t offset,
108 uint64_t imm);
109
110 void (*emit_mi_report_perf_count)(struct iris_batch *batch,
111 struct iris_bo *bo,
112 uint32_t offset_in_bytes,
113 uint32_t report_id);
114
115 unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
116 void (*store_derived_program_state)(const struct intel_device_info *devinfo,
117 enum iris_program_cache_id cache_id,
118 struct iris_compiled_shader *shader);
119 uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
120 const struct brw_vue_map *vue_map);
121 void (*populate_vs_key)(const struct iris_context *ice,
122 const struct shader_info *info,
123 gl_shader_stage last_stage,
124 struct iris_vs_prog_key *key);
125 void (*populate_tcs_key)(const struct iris_context *ice,
126 struct iris_tcs_prog_key *key);
127 void (*populate_tes_key)(const struct iris_context *ice,
128 const struct shader_info *info,
129 gl_shader_stage last_stage,
130 struct iris_tes_prog_key *key);
131 void (*populate_gs_key)(const struct iris_context *ice,
132 const struct shader_info *info,
133 gl_shader_stage last_stage,
134 struct iris_gs_prog_key *key);
135 void (*populate_fs_key)(const struct iris_context *ice,
136 const struct shader_info *info,
137 struct iris_fs_prog_key *key);
138 void (*populate_cs_key)(const struct iris_context *ice,
139 struct iris_cs_prog_key *key);
140 void (*lost_genx_state)(struct iris_context *ice, struct iris_batch *batch);
141 void (*disable_rhwo_optimization)(struct iris_batch *batch, bool disable);
142 };
143
144 struct iris_address {
145 struct iris_bo *bo;
146 uint64_t offset;
147 enum iris_domain access;
148 };
149
150 struct iris_screen {
151 struct pipe_screen base;
152
153 uint32_t refcount;
154
155 /** Global slab allocator for iris_transfer_map objects */
156 struct slab_parent_pool transfer_pool;
157
158 /** drm device file descriptor, shared with bufmgr, do not close. */
159 int fd;
160
161 /**
162 * drm device file descriptor to used for window system integration, owned
163 * by iris_screen, can be a different DRM instance than fd.
164 */
165 int winsys_fd;
166
167 /** PCI ID for our GPU device */
168 int pci_id;
169
170 struct iris_vtable vtbl;
171
172 /** Global program_string_id counter (see get_program_string_id()) */
173 unsigned program_id;
174
175 /** Precompile shaders at link time? (Can be disabled for debugging.) */
176 bool precompile;
177
178 /** driconf options and application workarounds */
179 struct {
180 /** Dual color blend by location instead of index (for broken apps) */
181 bool dual_color_blend_by_location;
182 bool disable_throttling;
183 bool always_flush_cache;
184 bool sync_compile;
185 bool limit_trig_input_range;
186 } driconf;
187
188 /** Does the kernel support various features (KERNEL_HAS_* bitfield)? */
189 unsigned kernel_features;
190 #define KERNEL_HAS_WAIT_FOR_SUBMIT (1<<0)
191
192 /**
193 * Last sequence number allocated by the cache tracking mechanism.
194 *
195 * These are used for synchronization and are expected to identify a single
196 * section of a batch, so they should be monotonically increasing and
197 * unique across a single pipe_screen.
198 */
199 uint64_t last_seqno;
200
201 struct intel_device_info devinfo;
202 struct isl_device isl_dev;
203 struct iris_bufmgr *bufmgr;
204 struct brw_compiler *compiler;
205 struct intel_perf_config *perf_cfg;
206
207 const struct intel_l3_config *l3_config_3d;
208 const struct intel_l3_config *l3_config_cs;
209
210 /**
211 * A buffer containing a marker + description of the driver. This buffer is
212 * added to all execbufs syscalls so that we can identify the driver that
213 * generated a hang by looking at the content of the buffer in the error
214 * state. It is also used for hardware workarounds that require scratch
215 * writes or reads from some unimportant memory. To avoid overriding the
216 * debug data, use the workaround_address field for workarounds.
217 */
218 struct iris_bo *workaround_bo;
219 struct iris_address workaround_address;
220
221 struct util_queue shader_compiler_queue;
222
223 struct disk_cache *disk_cache;
224
225 struct intel_measure_device measure;
226
227 /** Every screen on a bufmgr has an unique ID assigned by the bufmgr. */
228 int id;
229 };
230
231 struct pipe_screen *
232 iris_screen_create(int fd, const struct pipe_screen_config *config);
233
234 void iris_screen_destroy(struct iris_screen *screen);
235
236 UNUSED static inline struct pipe_screen *
iris_pscreen_ref(struct pipe_screen * pscreen)237 iris_pscreen_ref(struct pipe_screen *pscreen)
238 {
239 struct iris_screen *screen = (struct iris_screen *) pscreen;
240
241 p_atomic_inc(&screen->refcount);
242 return pscreen;
243 }
244
245 UNUSED static inline void
iris_pscreen_unref(struct pipe_screen * pscreen)246 iris_pscreen_unref(struct pipe_screen *pscreen)
247 {
248 struct iris_screen *screen = (struct iris_screen *) pscreen;
249
250 if (p_atomic_dec_zero(&screen->refcount))
251 iris_screen_destroy(screen);
252 }
253
254 bool
255 iris_is_format_supported(struct pipe_screen *pscreen,
256 enum pipe_format format,
257 enum pipe_texture_target target,
258 unsigned sample_count,
259 unsigned storage_sample_count,
260 unsigned usage);
261
262 void iris_disk_cache_init(struct iris_screen *screen);
263
264 #endif
265