| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_instr_tex.h | 79 struct Inputs { struct
81 const nir_variable *sampler_deref;
82 const nir_variable *texture_deref;
83 RegisterVec4 coord;
84 PVirtualValue bias;
85 PVirtualValue comperator;
86 PVirtualValue lod;
87 RegisterVec4 ddx;
88 RegisterVec4 ddy;
89 nir_src *offset;
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| /third_party/skia/third_party/externals/swiftshader/src/Device/ |
| D | Context.hpp | 63 struct Inputs struct
70 inline const DescriptorSet::Array &getDescriptorSetObjects() const { return descriptorSetObjects; } in getDescriptorSetObjects()
71 inline const DescriptorSet::Bindings &getDescriptorSets() const { return descriptorSets; } in getDescriptorSets()
72 …riptorSet::DynamicOffsets &getDescriptorDynamicOffsets() const { return descriptorDynamicOffsets; } in getDescriptorDynamicOffsets()
73 inline const sw::Stream &getStream(uint32_t i) const { return stream[i]; } in getStream()
80 VertexInputBinding vertexInputBindings[MAX_VERTEX_INPUT_BINDINGS] = {};
81 DescriptorSet::Array descriptorSetObjects = {};
82 DescriptorSet::Bindings descriptorSets = {};
83 DescriptorSet::DynamicOffsets descriptorDynamicOffsets = {};
84 sw::Stream stream[sw::MAX_INTERFACE_COMPONENTS / 4];
|
| /third_party/gn/src/gn/ |
| D | analyzer.cc | 31 struct Inputs { struct
32 std::vector<SourceFile> source_vec;
33 std::vector<Label> compile_vec;
34 std::vector<Label> test_vec;
35 bool compile_included_all = false;
36 std::set<const SourceFile*> source_files;
37 std::set<Label> compile_labels;
38 std::set<Label> test_labels;
|
| /third_party/vixl/test/aarch32/ |
| D | test-simulator-cond-rd-rn-rm-a32.cc | 195 struct Inputs { struct
196 uint32_t apsr;
197 uint32_t qbit;
198 uint32_t ge;
199 uint32_t rd;
200 uint32_t rn;
201 uint32_t rm;
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| D | test-simulator-cond-rd-rn-rm-sel-a32.cc | 137 struct Inputs { struct
138 uint32_t apsr;
139 uint32_t qbit;
140 uint32_t ge;
141 uint32_t rd;
142 uint32_t rn;
143 uint32_t rm;
|
| D | test-simulator-cond-rd-rn-rm-q-t32.cc | 141 struct Inputs { struct
142 uint32_t apsr;
143 uint32_t qbit;
144 uint32_t ge;
145 uint32_t rd;
146 uint32_t rn;
147 uint32_t rm;
|
| D | test-simulator-cond-rd-rn-rm-q-a32.cc | 141 struct Inputs { struct
142 uint32_t apsr;
143 uint32_t qbit;
144 uint32_t ge;
145 uint32_t rd;
146 uint32_t rn;
147 uint32_t rm;
|
| D | test-simulator-cond-rd-rn-rm-ge-t32.cc | 149 struct Inputs { struct
150 uint32_t apsr;
151 uint32_t qbit;
152 uint32_t ge;
153 uint32_t rd;
154 uint32_t rn;
155 uint32_t rm;
|
| D | test-simulator-cond-rd-rn-rm-t32.cc | 194 struct Inputs { struct
195 uint32_t apsr;
196 uint32_t qbit;
197 uint32_t ge;
198 uint32_t rd;
199 uint32_t rn;
200 uint32_t rm;
|
| D | test-simulator-cond-rd-rn-rm-ge-a32.cc | 149 struct Inputs { struct
150 uint32_t apsr;
151 uint32_t qbit;
152 uint32_t ge;
153 uint32_t rd;
154 uint32_t rn;
155 uint32_t rm;
|
| D | test-simulator-cond-rd-rn-rm-sel-t32.cc | 137 struct Inputs { struct
138 uint32_t apsr;
139 uint32_t qbit;
140 uint32_t ge;
141 uint32_t rd;
142 uint32_t rn;
143 uint32_t rm;
|
| D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 159 struct Inputs { struct
160 uint32_t apsr;
161 uint32_t rd;
162 uint32_t rn;
163 uint32_t rm;
164 uint32_t rs;
|
| D | test-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc | 139 struct Inputs { struct
140 uint32_t fpscr;
141 uint64_t rd;
142 uint64_t rn;
143 uint64_t rm;
|
| D | test-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc | 139 struct Inputs { struct
140 uint32_t fpscr;
141 uint64_t rd;
142 uint64_t rn;
143 uint64_t rm;
|
| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 171 struct Inputs { struct
172 uint32_t apsr;
173 uint32_t rd;
174 uint32_t rn;
175 uint32_t rm;
|
| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 171 struct Inputs { struct
172 uint32_t apsr;
173 uint32_t rd;
174 uint32_t rn;
175 uint32_t rm;
|
| D | test-simulator-cond-rdlow-rnlow-rmlow-t32.cc | 139 struct Inputs { struct
140 uint32_t apsr;
141 uint32_t rd;
142 uint32_t rn;
143 uint32_t rm;
|
| D | test-simulator-rd-rn-rm-t32.cc | 142 struct Inputs { struct
143 uint32_t rd;
144 uint32_t rn;
145 uint32_t rm;
|
| D | test-simulator-rd-rn-rm-a32.cc | 142 struct Inputs { struct
143 uint32_t rd;
144 uint32_t rn;
145 uint32_t rm;
|
| D | test-simulator-cond-rd-operand-rn-shift-rs-t32.cc | 140 struct Inputs { struct
141 uint32_t apsr;
142 uint32_t rd;
143 uint32_t rn;
144 uint32_t rs;
|
| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 159 struct Inputs { struct
160 uint32_t apsr;
161 uint32_t rd;
162 uint32_t rn;
163 uint32_t rm;
|
| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 159 struct Inputs { struct
160 uint32_t apsr;
161 uint32_t rd;
162 uint32_t rn;
163 uint32_t rm;
|
| D | test-simulator-cond-rd-operand-rn-shift-rs-a32.cc | 146 struct Inputs { struct
147 uint32_t apsr;
148 uint32_t rd;
149 uint32_t rn;
150 uint32_t rs;
|
| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc | 145 struct Inputs { struct
146 uint32_t apsr;
147 uint32_t rd;
148 uint32_t rn;
149 uint32_t rm;
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonConstPropagation.cpp | 1081 bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs, in getCell()
1108 const RegisterSubReg &R2, const CellMap &Inputs, bool &Result) { in evaluateCMPrr()
1147 const APInt &A2, const CellMap &Inputs, bool &Result) { in evaluateCMPri()
1174 uint64_t Props2, const CellMap &Inputs, bool &Result) { in evaluateCMPrp()
1367 const CellMap &Inputs, LatticeCell &Result) { in evaluateCOPY()
1372 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateANDrr()
1403 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { in evaluateANDri()
1439 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateORrr()
1470 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { in evaluateORri()
1506 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateXORrr()
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