1 // Copyright 2017, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 #ifndef VIXL_DISASM_AARCH32_H_ 28 #define VIXL_DISASM_AARCH32_H_ 29 30 extern "C" { 31 #include <stdint.h> 32 } 33 34 #include <iomanip> 35 36 #include "aarch32/constants-aarch32.h" 37 #include "aarch32/operands-aarch32.h" 38 39 namespace vixl { 40 namespace aarch32 { 41 42 class ITBlock { 43 Condition first_condition_; 44 Condition condition_; 45 uint16_t it_mask_; 46 47 public: ITBlock()48 ITBlock() : first_condition_(al), condition_(al), it_mask_(0) {} Advance()49 void Advance() { 50 condition_ = Condition((condition_.GetCondition() & 0xe) | (it_mask_ >> 3)); 51 it_mask_ = (it_mask_ << 1) & 0xf; 52 } InITBlock()53 bool InITBlock() const { return it_mask_ != 0; } OutsideITBlock()54 bool OutsideITBlock() const { return !InITBlock(); } LastInITBlock()55 bool LastInITBlock() const { return it_mask_ == 0x8; } OutsideITBlockOrLast()56 bool OutsideITBlockOrLast() const { 57 return OutsideITBlock() || LastInITBlock(); 58 } Set(Condition first_condition,uint16_t mask)59 void Set(Condition first_condition, uint16_t mask) { 60 condition_ = first_condition_ = first_condition; 61 it_mask_ = mask; 62 } GetFirstCondition()63 Condition GetFirstCondition() const { return first_condition_; } GetCurrentCondition()64 Condition GetCurrentCondition() const { return condition_; } 65 }; 66 67 class Disassembler { 68 public: 69 enum LocationType { 70 kAnyLocation, 71 kCodeLocation, 72 kDataLocation, 73 kCoprocLocation, 74 kLoadByteLocation, 75 kLoadHalfWordLocation, 76 kLoadWordLocation, 77 kLoadDoubleWordLocation, 78 kLoadSignedByteLocation, 79 kLoadSignedHalfWordLocation, 80 kLoadSinglePrecisionLocation, 81 kLoadDoublePrecisionLocation, 82 kStoreByteLocation, 83 kStoreHalfWordLocation, 84 kStoreWordLocation, 85 kStoreDoubleWordLocation, 86 kStoreSinglePrecisionLocation, 87 kStoreDoublePrecisionLocation, 88 kVld1Location, 89 kVld2Location, 90 kVld3Location, 91 kVld4Location, 92 kVst1Location, 93 kVst2Location, 94 kVst3Location, 95 kVst4Location 96 }; 97 98 class ConditionPrinter { 99 const ITBlock& it_block_; 100 Condition cond_; 101 102 public: ConditionPrinter(const ITBlock & it_block,Condition cond)103 ConditionPrinter(const ITBlock& it_block, Condition cond) 104 : it_block_(it_block), cond_(cond) {} GetITBlock()105 const ITBlock& GetITBlock() const { return it_block_; } GetCond()106 Condition GetCond() const { return cond_; } 107 friend std::ostream& operator<<(std::ostream& os, ConditionPrinter cond) { 108 if (cond.it_block_.InITBlock() && cond.cond_.Is(al) && 109 !cond.cond_.IsNone()) { 110 return os << "al"; 111 } 112 return os << cond.cond_; 113 } 114 }; 115 116 class ImmediatePrinter { 117 uint32_t imm_; 118 119 public: ImmediatePrinter(uint32_t imm)120 explicit ImmediatePrinter(uint32_t imm) : imm_(imm) {} GetImm()121 uint32_t GetImm() const { return imm_; } 122 friend std::ostream& operator<<(std::ostream& os, ImmediatePrinter imm) { 123 return os << "#" << imm.GetImm(); 124 } 125 }; 126 127 class SignedImmediatePrinter { 128 int32_t imm_; 129 130 public: SignedImmediatePrinter(int32_t imm)131 explicit SignedImmediatePrinter(int32_t imm) : imm_(imm) {} GetImm()132 int32_t GetImm() const { return imm_; } 133 friend std::ostream& operator<<(std::ostream& os, 134 SignedImmediatePrinter imm) { 135 return os << "#" << imm.GetImm(); 136 } 137 }; 138 139 class RawImmediatePrinter { 140 uint32_t imm_; 141 142 public: RawImmediatePrinter(uint32_t imm)143 explicit RawImmediatePrinter(uint32_t imm) : imm_(imm) {} GetImm()144 uint32_t GetImm() const { return imm_; } 145 friend std::ostream& operator<<(std::ostream& os, RawImmediatePrinter imm) { 146 return os << imm.GetImm(); 147 } 148 }; 149 150 class DtPrinter { 151 DataType dt_; 152 DataType default_dt_; 153 154 public: DtPrinter(DataType dt,DataType default_dt)155 DtPrinter(DataType dt, DataType default_dt) 156 : dt_(dt), default_dt_(default_dt) {} GetDt()157 DataType GetDt() const { return dt_; } GetDefaultDt()158 DataType GetDefaultDt() const { return default_dt_; } 159 friend std::ostream& operator<<(std::ostream& os, DtPrinter dt) { 160 if (dt.dt_.Is(dt.default_dt_)) return os; 161 return os << dt.dt_; 162 } 163 }; 164 165 class IndexedRegisterPrinter { 166 DRegister reg_; 167 uint32_t index_; 168 169 public: IndexedRegisterPrinter(DRegister reg,uint32_t index)170 IndexedRegisterPrinter(DRegister reg, uint32_t index) 171 : reg_(reg), index_(index) {} GetReg()172 DRegister GetReg() const { return reg_; } GetIndex()173 uint32_t GetIndex() const { return index_; } 174 friend std::ostream& operator<<(std::ostream& os, 175 IndexedRegisterPrinter reg) { 176 return os << reg.GetReg() << "[" << reg.GetIndex() << "]"; 177 } 178 }; 179 180 // TODO: Merge this class with PrintLabel below. This Location class 181 // represents a PC-relative offset, not an address. 182 class Location { 183 public: 184 typedef int32_t Offset; 185 Location(Offset immediate,Offset pc_offset)186 Location(Offset immediate, Offset pc_offset) 187 : immediate_(immediate), pc_offset_(pc_offset) {} GetImmediate()188 Offset GetImmediate() const { return immediate_; } GetPCOffset()189 Offset GetPCOffset() const { return pc_offset_; } 190 191 private: 192 Offset immediate_; 193 Offset pc_offset_; 194 }; 195 196 class PrintLabel { 197 LocationType location_type_; 198 Location::Offset immediate_; 199 Location::Offset location_; 200 201 public: PrintLabel(LocationType location_type,Location * offset,Location::Offset position)202 PrintLabel(LocationType location_type, 203 Location* offset, 204 Location::Offset position) 205 : location_type_(location_type), 206 immediate_(offset->GetImmediate()), 207 location_(static_cast<Location::Offset>( 208 static_cast<int64_t>(offset->GetPCOffset()) + 209 offset->GetImmediate() + position)) {} 210 GetLocationType()211 LocationType GetLocationType() const { return location_type_; } GetLocation()212 Location::Offset GetLocation() const { return location_; } GetImmediate()213 Location::Offset GetImmediate() const { return immediate_; } 214 215 friend inline std::ostream& operator<<(std::ostream& os, 216 const PrintLabel& label) { 217 os << "0x" << std::hex << std::setw(8) << std::setfill('0') 218 << label.GetLocation() << std::dec; 219 return os; 220 } 221 }; 222 223 224 class PrintMemOperand { 225 LocationType location_type_; 226 const MemOperand& operand_; 227 228 public: PrintMemOperand(LocationType location_type,const MemOperand & operand)229 PrintMemOperand(LocationType location_type, const MemOperand& operand) 230 : location_type_(location_type), operand_(operand) {} GetLocationType()231 LocationType GetLocationType() const { return location_type_; } GetOperand()232 const MemOperand& GetOperand() const { return operand_; } 233 }; 234 235 class PrintAlignedMemOperand { 236 LocationType location_type_; 237 const AlignedMemOperand& operand_; 238 239 public: PrintAlignedMemOperand(LocationType location_type,const AlignedMemOperand & operand)240 PrintAlignedMemOperand(LocationType location_type, 241 const AlignedMemOperand& operand) 242 : location_type_(location_type), operand_(operand) {} GetLocationType()243 LocationType GetLocationType() const { return location_type_; } GetOperand()244 const AlignedMemOperand& GetOperand() const { return operand_; } 245 }; 246 247 class DisassemblerStream { 248 std::ostream& os_; 249 InstructionType current_instruction_type_; 250 InstructionAttribute current_instruction_attributes_; 251 252 public: DisassemblerStream(std::ostream & os)253 explicit DisassemblerStream(std::ostream& os) // NOLINT(runtime/references) 254 : os_(os), 255 current_instruction_type_(kUndefInstructionType), 256 current_instruction_attributes_(kNoAttribute) {} ~DisassemblerStream()257 virtual ~DisassemblerStream() {} os()258 std::ostream& os() const { return os_; } SetCurrentInstruction(InstructionType current_instruction_type,InstructionAttribute current_instruction_attributes)259 void SetCurrentInstruction( 260 InstructionType current_instruction_type, 261 InstructionAttribute current_instruction_attributes) { 262 current_instruction_type_ = current_instruction_type; 263 current_instruction_attributes_ = current_instruction_attributes; 264 } GetCurrentInstructionType()265 InstructionType GetCurrentInstructionType() const { 266 return current_instruction_type_; 267 } GetCurrentInstructionAttributes()268 InstructionAttribute GetCurrentInstructionAttributes() const { 269 return current_instruction_attributes_; 270 } Has(InstructionAttribute attributes)271 bool Has(InstructionAttribute attributes) const { 272 return (current_instruction_attributes_ & attributes) == attributes; 273 } 274 template <typename T> 275 DisassemblerStream& operator<<(T value) { 276 os_ << value; 277 return *this; 278 } 279 virtual DisassemblerStream& operator<<(const char* string) { 280 os_ << string; 281 return *this; 282 } 283 virtual DisassemblerStream& operator<<(const ConditionPrinter& cond) { 284 os_ << cond; 285 return *this; 286 } 287 virtual DisassemblerStream& operator<<(Condition cond) { 288 os_ << cond; 289 return *this; 290 } 291 virtual DisassemblerStream& operator<<(const EncodingSize& size) { 292 os_ << size; 293 return *this; 294 } 295 virtual DisassemblerStream& operator<<(const ImmediatePrinter& imm) { 296 os_ << imm; 297 return *this; 298 } 299 virtual DisassemblerStream& operator<<(const SignedImmediatePrinter& imm) { 300 os_ << imm; 301 return *this; 302 } 303 virtual DisassemblerStream& operator<<(const RawImmediatePrinter& imm) { 304 os_ << imm; 305 return *this; 306 } 307 virtual DisassemblerStream& operator<<(const DtPrinter& dt) { 308 os_ << dt; 309 return *this; 310 } 311 virtual DisassemblerStream& operator<<(const DataType& type) { 312 os_ << type; 313 return *this; 314 } 315 virtual DisassemblerStream& operator<<(Shift shift) { 316 os_ << shift; 317 return *this; 318 } 319 virtual DisassemblerStream& operator<<(Sign sign) { 320 os_ << sign; 321 return *this; 322 } 323 virtual DisassemblerStream& operator<<(Alignment alignment) { 324 os_ << alignment; 325 return *this; 326 } 327 virtual DisassemblerStream& operator<<(const PrintLabel& label) { 328 os_ << label; 329 return *this; 330 } 331 virtual DisassemblerStream& operator<<(const WriteBack& write_back) { 332 os_ << write_back; 333 return *this; 334 } 335 virtual DisassemblerStream& operator<<(const NeonImmediate& immediate) { 336 os_ << immediate; 337 return *this; 338 } 339 virtual DisassemblerStream& operator<<(Register reg) { 340 os_ << reg; 341 return *this; 342 } 343 virtual DisassemblerStream& operator<<(SRegister reg) { 344 os_ << reg; 345 return *this; 346 } 347 virtual DisassemblerStream& operator<<(DRegister reg) { 348 os_ << reg; 349 return *this; 350 } 351 virtual DisassemblerStream& operator<<(QRegister reg) { 352 os_ << reg; 353 return *this; 354 } 355 virtual DisassemblerStream& operator<<(const RegisterOrAPSR_nzcv reg) { 356 os_ << reg; 357 return *this; 358 } 359 virtual DisassemblerStream& operator<<(SpecialRegister reg) { 360 os_ << reg; 361 return *this; 362 } 363 virtual DisassemblerStream& operator<<(MaskedSpecialRegister reg) { 364 os_ << reg; 365 return *this; 366 } 367 virtual DisassemblerStream& operator<<(SpecialFPRegister reg) { 368 os_ << reg; 369 return *this; 370 } 371 virtual DisassemblerStream& operator<<(BankedRegister reg) { 372 os_ << reg; 373 return *this; 374 } 375 virtual DisassemblerStream& operator<<(const RegisterList& list) { 376 os_ << list; 377 return *this; 378 } 379 virtual DisassemblerStream& operator<<(const SRegisterList& list) { 380 os_ << list; 381 return *this; 382 } 383 virtual DisassemblerStream& operator<<(const DRegisterList& list) { 384 os_ << list; 385 return *this; 386 } 387 virtual DisassemblerStream& operator<<(const NeonRegisterList& list) { 388 os_ << list; 389 return *this; 390 } 391 virtual DisassemblerStream& operator<<(const DRegisterLane& reg) { 392 os_ << reg; 393 return *this; 394 } 395 virtual DisassemblerStream& operator<<(const IndexedRegisterPrinter& reg) { 396 os_ << reg; 397 return *this; 398 } 399 virtual DisassemblerStream& operator<<(Coprocessor coproc) { 400 os_ << coproc; 401 return *this; 402 } 403 virtual DisassemblerStream& operator<<(CRegister reg) { 404 os_ << reg; 405 return *this; 406 } 407 virtual DisassemblerStream& operator<<(Endianness endian_specifier) { 408 os_ << endian_specifier; 409 return *this; 410 } 411 virtual DisassemblerStream& operator<<(MemoryBarrier option) { 412 os_ << option; 413 return *this; 414 } 415 virtual DisassemblerStream& operator<<(InterruptFlags iflags) { 416 os_ << iflags; 417 return *this; 418 } 419 virtual DisassemblerStream& operator<<(const Operand& operand) { 420 if (operand.IsImmediate()) { 421 if (Has(kBitwise)) { 422 return *this << "#0x" << std::hex << operand.GetImmediate() 423 << std::dec; 424 } 425 return *this << "#" << operand.GetImmediate(); 426 } 427 if (operand.IsImmediateShiftedRegister()) { 428 if ((operand.GetShift().IsLSL() || operand.GetShift().IsROR()) && 429 (operand.GetShiftAmount() == 0)) { 430 return *this << operand.GetBaseRegister(); 431 } 432 if (operand.GetShift().IsRRX()) { 433 return *this << operand.GetBaseRegister() << ", rrx"; 434 } 435 return *this << operand.GetBaseRegister() << ", " << operand.GetShift() 436 << " #" << operand.GetShiftAmount(); 437 } 438 if (operand.IsRegisterShiftedRegister()) { 439 return *this << operand.GetBaseRegister() << ", " << operand.GetShift() 440 << " " << operand.GetShiftRegister(); 441 } 442 VIXL_UNREACHABLE(); 443 return *this; 444 } 445 virtual DisassemblerStream& operator<<(const SOperand& operand) { 446 if (operand.IsImmediate()) { 447 return *this << operand.GetNeonImmediate(); 448 } 449 return *this << operand.GetRegister(); 450 } 451 virtual DisassemblerStream& operator<<(const DOperand& operand) { 452 if (operand.IsImmediate()) { 453 return *this << operand.GetNeonImmediate(); 454 } 455 return *this << operand.GetRegister(); 456 } 457 virtual DisassemblerStream& operator<<(const QOperand& operand) { 458 if (operand.IsImmediate()) { 459 return *this << operand.GetNeonImmediate(); 460 } 461 return *this << operand.GetRegister(); 462 } 463 virtual DisassemblerStream& operator<<(const MemOperand& operand) { 464 *this << "[" << operand.GetBaseRegister(); 465 if (operand.GetAddrMode() == PostIndex) { 466 *this << "]"; 467 if (operand.IsRegisterOnly()) return *this << "!"; 468 } 469 if (operand.IsImmediate()) { 470 if ((operand.GetOffsetImmediate() != 0) || 471 operand.GetSign().IsMinus() || 472 ((operand.GetAddrMode() != Offset) && !operand.IsRegisterOnly())) { 473 if (operand.GetOffsetImmediate() == 0) { 474 *this << ", #" << operand.GetSign() << operand.GetOffsetImmediate(); 475 } else { 476 *this << ", #" << operand.GetOffsetImmediate(); 477 } 478 } 479 } else if (operand.IsPlainRegister()) { 480 *this << ", " << operand.GetSign() << operand.GetOffsetRegister(); 481 } else if (operand.IsShiftedRegister()) { 482 *this << ", " << operand.GetSign() << operand.GetOffsetRegister() 483 << ImmediateShiftOperand(operand.GetShift(), 484 operand.GetShiftAmount()); 485 } else { 486 VIXL_UNREACHABLE(); 487 return *this; 488 } 489 if (operand.GetAddrMode() == Offset) { 490 *this << "]"; 491 } else if (operand.GetAddrMode() == PreIndex) { 492 *this << "]!"; 493 } 494 return *this; 495 } 496 virtual DisassemblerStream& operator<<(const PrintMemOperand& operand) { 497 return *this << operand.GetOperand(); 498 } 499 virtual DisassemblerStream& operator<<(const AlignedMemOperand& operand) { 500 *this << "[" << operand.GetBaseRegister() << operand.GetAlignment() 501 << "]"; 502 if (operand.GetAddrMode() == PostIndex) { 503 if (operand.IsPlainRegister()) { 504 *this << ", " << operand.GetOffsetRegister(); 505 } else { 506 *this << "!"; 507 } 508 } 509 return *this; 510 } 511 virtual DisassemblerStream& operator<<( 512 const PrintAlignedMemOperand& operand) { 513 return *this << operand.GetOperand(); 514 } 515 }; 516 517 private: 518 class ITBlockScope { 519 ITBlock* const it_block_; 520 bool inside_; 521 522 public: ITBlockScope(ITBlock * it_block)523 explicit ITBlockScope(ITBlock* it_block) 524 : it_block_(it_block), inside_(it_block->InITBlock()) {} ~ITBlockScope()525 ~ITBlockScope() { 526 if (inside_) it_block_->Advance(); 527 } 528 }; 529 530 std::optional<AllocatorWrapper> allocator_; 531 ITBlock it_block_; 532 DisassemblerStream* os_; 533 bool owns_os_ {false}; 534 uint32_t code_address_; 535 // True if the disassembler always output instructions with all the 536 // registers (even if two registers are identical and only one could be 537 // output). 538 bool use_short_hand_form_; 539 540 public: 541 #ifndef PANDA_BUILD 542 explicit Disassembler(std::ostream& os, // NOLINT(runtime/references) 543 uint32_t code_address = 0) allocator_(std::make_optional<AllocatorWrapper> ())544 : allocator_(std::make_optional<AllocatorWrapper>()), 545 os_(new DisassemblerStream(os)), 546 #else 547 explicit Disassembler(std::ostream& os, uint32_t code_address = 0) = delete; 548 explicit Disassembler(PandaAllocator* allocator, std::ostream& os, // NOLINT(runtime/references) 549 uint32_t code_address = 0) 550 : allocator_(std::make_optional<AllocatorWrapper>(allocator)), 551 os_(allocator_->New<DisassemblerStream>(os)), 552 #endif 553 owns_os_(true), 554 code_address_(code_address), 555 use_short_hand_form_(true) {} 556 explicit Disassembler(DisassemblerStream* os, uint32_t code_address = 0) os_(os)557 : os_(os), 558 owns_os_(false), 559 code_address_(code_address), 560 use_short_hand_form_(true) {} ~Disassembler()561 virtual ~Disassembler() { 562 if (owns_os_) { 563 allocator_->DeleteObject(os_); 564 } 565 } os()566 DisassemblerStream& os() const { return *os_; } SetIT(Condition first_condition,uint16_t it_mask)567 void SetIT(Condition first_condition, uint16_t it_mask) { 568 it_block_.Set(first_condition, it_mask); 569 } GetITBlock()570 const ITBlock& GetITBlock() const { return it_block_; } InITBlock()571 bool InITBlock() const { return it_block_.InITBlock(); } OutsideITBlock()572 bool OutsideITBlock() const { return it_block_.OutsideITBlock(); } OutsideITBlockOrLast()573 bool OutsideITBlockOrLast() const { return it_block_.OutsideITBlockOrLast(); } CheckNotIT()574 void CheckNotIT() const { VIXL_ASSERT(it_block_.OutsideITBlock()); } 575 // Return the current condition depending on the IT state for T32. CurrentCond()576 Condition CurrentCond() const { 577 if (it_block_.OutsideITBlock()) return al; 578 return it_block_.GetCurrentCondition(); 579 } UseShortHandForm()580 bool UseShortHandForm() const { return use_short_hand_form_; } SetUseShortHandForm(bool use_short_hand_form)581 void SetUseShortHandForm(bool use_short_hand_form) { 582 use_short_hand_form_ = use_short_hand_form; 583 } 584 UnallocatedT32(uint32_t instruction)585 virtual void UnallocatedT32(uint32_t instruction) { 586 if (T32Size(instruction) == 2) { 587 os() << "unallocated " << std::hex << std::setw(4) << std::setfill('0') 588 << (instruction >> 16) << std::dec; 589 } else { 590 os() << "unallocated " << std::hex << std::setw(8) << std::setfill('0') 591 << instruction << std::dec; 592 } 593 } UnallocatedA32(uint32_t instruction)594 virtual void UnallocatedA32(uint32_t instruction) { 595 os() << "unallocated " << std::hex << std::setw(8) << std::setfill('0') 596 << instruction << std::dec; 597 } UnimplementedT32_16(const char * name,uint32_t instruction)598 virtual void UnimplementedT32_16(const char* name, uint32_t instruction) { 599 os() << "unimplemented " << name << " T32:" << std::hex << std::setw(4) 600 << std::setfill('0') << (instruction >> 16) << std::dec; 601 } UnimplementedT32_32(const char * name,uint32_t instruction)602 virtual void UnimplementedT32_32(const char* name, uint32_t instruction) { 603 os() << "unimplemented " << name << " T32:" << std::hex << std::setw(8) 604 << std::setfill('0') << instruction << std::dec; 605 } UnimplementedA32(const char * name,uint32_t instruction)606 virtual void UnimplementedA32(const char* name, uint32_t instruction) { 607 os() << "unimplemented " << name << " ARM:" << std::hex << std::setw(8) 608 << std::setfill('0') << instruction << std::dec; 609 } Unpredictable()610 virtual void Unpredictable() { os() << " ; unpredictable"; } UnpredictableT32(uint32_t)611 virtual void UnpredictableT32(uint32_t /*instr*/) { return Unpredictable(); } UnpredictableA32(uint32_t)612 virtual void UnpredictableA32(uint32_t /*instr*/) { return Unpredictable(); } 613 Is16BitEncoding(uint32_t instr)614 static bool Is16BitEncoding(uint32_t instr) { return instr < 0xe8000000; } GetCodeAddress()615 uint32_t GetCodeAddress() const { return code_address_; } SetCodeAddress(uint32_t code_address)616 void SetCodeAddress(uint32_t code_address) { code_address_ = code_address; } 617 618 // Start of generated code. 619 620 void adc(Condition cond, 621 EncodingSize size, 622 Register rd, 623 Register rn, 624 const Operand& operand); 625 626 void adcs(Condition cond, 627 EncodingSize size, 628 Register rd, 629 Register rn, 630 const Operand& operand); 631 632 void add(Condition cond, 633 EncodingSize size, 634 Register rd, 635 Register rn, 636 const Operand& operand); 637 638 void add(Condition cond, Register rd, const Operand& operand); 639 640 void adds(Condition cond, 641 EncodingSize size, 642 Register rd, 643 Register rn, 644 const Operand& operand); 645 646 void adds(Register rd, const Operand& operand); 647 648 void addw(Condition cond, Register rd, Register rn, const Operand& operand); 649 650 void adr(Condition cond, EncodingSize size, Register rd, Location* location); 651 652 void and_(Condition cond, 653 EncodingSize size, 654 Register rd, 655 Register rn, 656 const Operand& operand); 657 658 void ands(Condition cond, 659 EncodingSize size, 660 Register rd, 661 Register rn, 662 const Operand& operand); 663 664 void asr(Condition cond, 665 EncodingSize size, 666 Register rd, 667 Register rm, 668 const Operand& operand); 669 670 void asrs(Condition cond, 671 EncodingSize size, 672 Register rd, 673 Register rm, 674 const Operand& operand); 675 676 void b(Condition cond, EncodingSize size, Location* location); 677 678 void bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width); 679 680 void bfi( 681 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width); 682 683 void bic(Condition cond, 684 EncodingSize size, 685 Register rd, 686 Register rn, 687 const Operand& operand); 688 689 void bics(Condition cond, 690 EncodingSize size, 691 Register rd, 692 Register rn, 693 const Operand& operand); 694 695 void bkpt(Condition cond, uint32_t imm); 696 697 void bl(Condition cond, Location* location); 698 699 void blx(Condition cond, Location* location); 700 701 void blx(Condition cond, Register rm); 702 703 void bx(Condition cond, Register rm); 704 705 void bxj(Condition cond, Register rm); 706 707 void cbnz(Register rn, Location* location); 708 709 void cbz(Register rn, Location* location); 710 711 void clrex(Condition cond); 712 713 void clz(Condition cond, Register rd, Register rm); 714 715 void cmn(Condition cond, 716 EncodingSize size, 717 Register rn, 718 const Operand& operand); 719 720 void cmp(Condition cond, 721 EncodingSize size, 722 Register rn, 723 const Operand& operand); 724 725 void crc32b(Condition cond, Register rd, Register rn, Register rm); 726 727 void crc32cb(Condition cond, Register rd, Register rn, Register rm); 728 729 void crc32ch(Condition cond, Register rd, Register rn, Register rm); 730 731 void crc32cw(Condition cond, Register rd, Register rn, Register rm); 732 733 void crc32h(Condition cond, Register rd, Register rn, Register rm); 734 735 void crc32w(Condition cond, Register rd, Register rn, Register rm); 736 737 void dmb(Condition cond, MemoryBarrier option); 738 739 void dsb(Condition cond, MemoryBarrier option); 740 741 void eor(Condition cond, 742 EncodingSize size, 743 Register rd, 744 Register rn, 745 const Operand& operand); 746 747 void eors(Condition cond, 748 EncodingSize size, 749 Register rd, 750 Register rn, 751 const Operand& operand); 752 753 void fldmdbx(Condition cond, 754 Register rn, 755 WriteBack write_back, 756 DRegisterList dreglist); 757 758 void fldmiax(Condition cond, 759 Register rn, 760 WriteBack write_back, 761 DRegisterList dreglist); 762 763 void fstmdbx(Condition cond, 764 Register rn, 765 WriteBack write_back, 766 DRegisterList dreglist); 767 768 void fstmiax(Condition cond, 769 Register rn, 770 WriteBack write_back, 771 DRegisterList dreglist); 772 773 void hlt(Condition cond, uint32_t imm); 774 775 void hvc(Condition cond, uint32_t imm); 776 777 void isb(Condition cond, MemoryBarrier option); 778 779 void it(Condition cond, uint16_t mask); 780 781 void lda(Condition cond, Register rt, const MemOperand& operand); 782 783 void ldab(Condition cond, Register rt, const MemOperand& operand); 784 785 void ldaex(Condition cond, Register rt, const MemOperand& operand); 786 787 void ldaexb(Condition cond, Register rt, const MemOperand& operand); 788 789 void ldaexd(Condition cond, 790 Register rt, 791 Register rt2, 792 const MemOperand& operand); 793 794 void ldaexh(Condition cond, Register rt, const MemOperand& operand); 795 796 void ldah(Condition cond, Register rt, const MemOperand& operand); 797 798 void ldm(Condition cond, 799 EncodingSize size, 800 Register rn, 801 WriteBack write_back, 802 RegisterList registers); 803 804 void ldmda(Condition cond, 805 Register rn, 806 WriteBack write_back, 807 RegisterList registers); 808 809 void ldmdb(Condition cond, 810 Register rn, 811 WriteBack write_back, 812 RegisterList registers); 813 814 void ldmea(Condition cond, 815 Register rn, 816 WriteBack write_back, 817 RegisterList registers); 818 819 void ldmed(Condition cond, 820 Register rn, 821 WriteBack write_back, 822 RegisterList registers); 823 824 void ldmfa(Condition cond, 825 Register rn, 826 WriteBack write_back, 827 RegisterList registers); 828 829 void ldmfd(Condition cond, 830 EncodingSize size, 831 Register rn, 832 WriteBack write_back, 833 RegisterList registers); 834 835 void ldmib(Condition cond, 836 Register rn, 837 WriteBack write_back, 838 RegisterList registers); 839 840 void ldr(Condition cond, 841 EncodingSize size, 842 Register rt, 843 const MemOperand& operand); 844 845 void ldr(Condition cond, EncodingSize size, Register rt, Location* location); 846 847 void ldrb(Condition cond, 848 EncodingSize size, 849 Register rt, 850 const MemOperand& operand); 851 852 void ldrb(Condition cond, Register rt, Location* location); 853 854 void ldrd(Condition cond, 855 Register rt, 856 Register rt2, 857 const MemOperand& operand); 858 859 void ldrd(Condition cond, Register rt, Register rt2, Location* location); 860 861 void ldrex(Condition cond, Register rt, const MemOperand& operand); 862 863 void ldrexb(Condition cond, Register rt, const MemOperand& operand); 864 865 void ldrexd(Condition cond, 866 Register rt, 867 Register rt2, 868 const MemOperand& operand); 869 870 void ldrexh(Condition cond, Register rt, const MemOperand& operand); 871 872 void ldrh(Condition cond, 873 EncodingSize size, 874 Register rt, 875 const MemOperand& operand); 876 877 void ldrh(Condition cond, Register rt, Location* location); 878 879 void ldrsb(Condition cond, 880 EncodingSize size, 881 Register rt, 882 const MemOperand& operand); 883 884 void ldrsb(Condition cond, Register rt, Location* location); 885 886 void ldrsh(Condition cond, 887 EncodingSize size, 888 Register rt, 889 const MemOperand& operand); 890 891 void ldrsh(Condition cond, Register rt, Location* location); 892 893 void lsl(Condition cond, 894 EncodingSize size, 895 Register rd, 896 Register rm, 897 const Operand& operand); 898 899 void lsls(Condition cond, 900 EncodingSize size, 901 Register rd, 902 Register rm, 903 const Operand& operand); 904 905 void lsr(Condition cond, 906 EncodingSize size, 907 Register rd, 908 Register rm, 909 const Operand& operand); 910 911 void lsrs(Condition cond, 912 EncodingSize size, 913 Register rd, 914 Register rm, 915 const Operand& operand); 916 917 void mla(Condition cond, Register rd, Register rn, Register rm, Register ra); 918 919 void mlas(Condition cond, Register rd, Register rn, Register rm, Register ra); 920 921 void mls(Condition cond, Register rd, Register rn, Register rm, Register ra); 922 923 void mov(Condition cond, 924 EncodingSize size, 925 Register rd, 926 const Operand& operand); 927 928 void movs(Condition cond, 929 EncodingSize size, 930 Register rd, 931 const Operand& operand); 932 933 void movt(Condition cond, Register rd, const Operand& operand); 934 935 void movw(Condition cond, Register rd, const Operand& operand); 936 937 void mrs(Condition cond, Register rd, SpecialRegister spec_reg); 938 939 void msr(Condition cond, 940 MaskedSpecialRegister spec_reg, 941 const Operand& operand); 942 943 void mul( 944 Condition cond, EncodingSize size, Register rd, Register rn, Register rm); 945 946 void muls(Condition cond, Register rd, Register rn, Register rm); 947 948 void mvn(Condition cond, 949 EncodingSize size, 950 Register rd, 951 const Operand& operand); 952 953 void mvns(Condition cond, 954 EncodingSize size, 955 Register rd, 956 const Operand& operand); 957 958 void nop(Condition cond, EncodingSize size); 959 960 void orn(Condition cond, Register rd, Register rn, const Operand& operand); 961 962 void orns(Condition cond, Register rd, Register rn, const Operand& operand); 963 964 void orr(Condition cond, 965 EncodingSize size, 966 Register rd, 967 Register rn, 968 const Operand& operand); 969 970 void orrs(Condition cond, 971 EncodingSize size, 972 Register rd, 973 Register rn, 974 const Operand& operand); 975 976 void pkhbt(Condition cond, Register rd, Register rn, const Operand& operand); 977 978 void pkhtb(Condition cond, Register rd, Register rn, const Operand& operand); 979 980 void pld(Condition cond, Location* location); 981 982 void pld(Condition cond, const MemOperand& operand); 983 984 void pldw(Condition cond, const MemOperand& operand); 985 986 void pli(Condition cond, const MemOperand& operand); 987 988 void pli(Condition cond, Location* location); 989 990 void pop(Condition cond, EncodingSize size, RegisterList registers); 991 992 void pop(Condition cond, EncodingSize size, Register rt); 993 994 void push(Condition cond, EncodingSize size, RegisterList registers); 995 996 void push(Condition cond, EncodingSize size, Register rt); 997 998 void qadd(Condition cond, Register rd, Register rm, Register rn); 999 1000 void qadd16(Condition cond, Register rd, Register rn, Register rm); 1001 1002 void qadd8(Condition cond, Register rd, Register rn, Register rm); 1003 1004 void qasx(Condition cond, Register rd, Register rn, Register rm); 1005 1006 void qdadd(Condition cond, Register rd, Register rm, Register rn); 1007 1008 void qdsub(Condition cond, Register rd, Register rm, Register rn); 1009 1010 void qsax(Condition cond, Register rd, Register rn, Register rm); 1011 1012 void qsub(Condition cond, Register rd, Register rm, Register rn); 1013 1014 void qsub16(Condition cond, Register rd, Register rn, Register rm); 1015 1016 void qsub8(Condition cond, Register rd, Register rn, Register rm); 1017 1018 void rbit(Condition cond, Register rd, Register rm); 1019 1020 void rev(Condition cond, EncodingSize size, Register rd, Register rm); 1021 1022 void rev16(Condition cond, EncodingSize size, Register rd, Register rm); 1023 1024 void revsh(Condition cond, EncodingSize size, Register rd, Register rm); 1025 1026 void ror(Condition cond, 1027 EncodingSize size, 1028 Register rd, 1029 Register rm, 1030 const Operand& operand); 1031 1032 void rors(Condition cond, 1033 EncodingSize size, 1034 Register rd, 1035 Register rm, 1036 const Operand& operand); 1037 1038 void rrx(Condition cond, Register rd, Register rm); 1039 1040 void rrxs(Condition cond, Register rd, Register rm); 1041 1042 void rsb(Condition cond, 1043 EncodingSize size, 1044 Register rd, 1045 Register rn, 1046 const Operand& operand); 1047 1048 void rsbs(Condition cond, 1049 EncodingSize size, 1050 Register rd, 1051 Register rn, 1052 const Operand& operand); 1053 1054 void rsc(Condition cond, Register rd, Register rn, const Operand& operand); 1055 1056 void rscs(Condition cond, Register rd, Register rn, const Operand& operand); 1057 1058 void sadd16(Condition cond, Register rd, Register rn, Register rm); 1059 1060 void sadd8(Condition cond, Register rd, Register rn, Register rm); 1061 1062 void sasx(Condition cond, Register rd, Register rn, Register rm); 1063 1064 void sbc(Condition cond, 1065 EncodingSize size, 1066 Register rd, 1067 Register rn, 1068 const Operand& operand); 1069 1070 void sbcs(Condition cond, 1071 EncodingSize size, 1072 Register rd, 1073 Register rn, 1074 const Operand& operand); 1075 1076 void sbfx( 1077 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width); 1078 1079 void sdiv(Condition cond, Register rd, Register rn, Register rm); 1080 1081 void sel(Condition cond, Register rd, Register rn, Register rm); 1082 1083 void shadd16(Condition cond, Register rd, Register rn, Register rm); 1084 1085 void shadd8(Condition cond, Register rd, Register rn, Register rm); 1086 1087 void shasx(Condition cond, Register rd, Register rn, Register rm); 1088 1089 void shsax(Condition cond, Register rd, Register rn, Register rm); 1090 1091 void shsub16(Condition cond, Register rd, Register rn, Register rm); 1092 1093 void shsub8(Condition cond, Register rd, Register rn, Register rm); 1094 1095 void smlabb( 1096 Condition cond, Register rd, Register rn, Register rm, Register ra); 1097 1098 void smlabt( 1099 Condition cond, Register rd, Register rn, Register rm, Register ra); 1100 1101 void smlad( 1102 Condition cond, Register rd, Register rn, Register rm, Register ra); 1103 1104 void smladx( 1105 Condition cond, Register rd, Register rn, Register rm, Register ra); 1106 1107 void smlal( 1108 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1109 1110 void smlalbb( 1111 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1112 1113 void smlalbt( 1114 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1115 1116 void smlald( 1117 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1118 1119 void smlaldx( 1120 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1121 1122 void smlals( 1123 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1124 1125 void smlaltb( 1126 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1127 1128 void smlaltt( 1129 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1130 1131 void smlatb( 1132 Condition cond, Register rd, Register rn, Register rm, Register ra); 1133 1134 void smlatt( 1135 Condition cond, Register rd, Register rn, Register rm, Register ra); 1136 1137 void smlawb( 1138 Condition cond, Register rd, Register rn, Register rm, Register ra); 1139 1140 void smlawt( 1141 Condition cond, Register rd, Register rn, Register rm, Register ra); 1142 1143 void smlsd( 1144 Condition cond, Register rd, Register rn, Register rm, Register ra); 1145 1146 void smlsdx( 1147 Condition cond, Register rd, Register rn, Register rm, Register ra); 1148 1149 void smlsld( 1150 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1151 1152 void smlsldx( 1153 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1154 1155 void smmla( 1156 Condition cond, Register rd, Register rn, Register rm, Register ra); 1157 1158 void smmlar( 1159 Condition cond, Register rd, Register rn, Register rm, Register ra); 1160 1161 void smmls( 1162 Condition cond, Register rd, Register rn, Register rm, Register ra); 1163 1164 void smmlsr( 1165 Condition cond, Register rd, Register rn, Register rm, Register ra); 1166 1167 void smmul(Condition cond, Register rd, Register rn, Register rm); 1168 1169 void smmulr(Condition cond, Register rd, Register rn, Register rm); 1170 1171 void smuad(Condition cond, Register rd, Register rn, Register rm); 1172 1173 void smuadx(Condition cond, Register rd, Register rn, Register rm); 1174 1175 void smulbb(Condition cond, Register rd, Register rn, Register rm); 1176 1177 void smulbt(Condition cond, Register rd, Register rn, Register rm); 1178 1179 void smull( 1180 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1181 1182 void smulls( 1183 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1184 1185 void smultb(Condition cond, Register rd, Register rn, Register rm); 1186 1187 void smultt(Condition cond, Register rd, Register rn, Register rm); 1188 1189 void smulwb(Condition cond, Register rd, Register rn, Register rm); 1190 1191 void smulwt(Condition cond, Register rd, Register rn, Register rm); 1192 1193 void smusd(Condition cond, Register rd, Register rn, Register rm); 1194 1195 void smusdx(Condition cond, Register rd, Register rn, Register rm); 1196 1197 void ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand); 1198 1199 void ssat16(Condition cond, Register rd, uint32_t imm, Register rn); 1200 1201 void ssax(Condition cond, Register rd, Register rn, Register rm); 1202 1203 void ssub16(Condition cond, Register rd, Register rn, Register rm); 1204 1205 void ssub8(Condition cond, Register rd, Register rn, Register rm); 1206 1207 void stl(Condition cond, Register rt, const MemOperand& operand); 1208 1209 void stlb(Condition cond, Register rt, const MemOperand& operand); 1210 1211 void stlex(Condition cond, 1212 Register rd, 1213 Register rt, 1214 const MemOperand& operand); 1215 1216 void stlexb(Condition cond, 1217 Register rd, 1218 Register rt, 1219 const MemOperand& operand); 1220 1221 void stlexd(Condition cond, 1222 Register rd, 1223 Register rt, 1224 Register rt2, 1225 const MemOperand& operand); 1226 1227 void stlexh(Condition cond, 1228 Register rd, 1229 Register rt, 1230 const MemOperand& operand); 1231 1232 void stlh(Condition cond, Register rt, const MemOperand& operand); 1233 1234 void stm(Condition cond, 1235 EncodingSize size, 1236 Register rn, 1237 WriteBack write_back, 1238 RegisterList registers); 1239 1240 void stmda(Condition cond, 1241 Register rn, 1242 WriteBack write_back, 1243 RegisterList registers); 1244 1245 void stmdb(Condition cond, 1246 EncodingSize size, 1247 Register rn, 1248 WriteBack write_back, 1249 RegisterList registers); 1250 1251 void stmea(Condition cond, 1252 EncodingSize size, 1253 Register rn, 1254 WriteBack write_back, 1255 RegisterList registers); 1256 1257 void stmed(Condition cond, 1258 Register rn, 1259 WriteBack write_back, 1260 RegisterList registers); 1261 1262 void stmfa(Condition cond, 1263 Register rn, 1264 WriteBack write_back, 1265 RegisterList registers); 1266 1267 void stmfd(Condition cond, 1268 Register rn, 1269 WriteBack write_back, 1270 RegisterList registers); 1271 1272 void stmib(Condition cond, 1273 Register rn, 1274 WriteBack write_back, 1275 RegisterList registers); 1276 1277 void str(Condition cond, 1278 EncodingSize size, 1279 Register rt, 1280 const MemOperand& operand); 1281 1282 void strb(Condition cond, 1283 EncodingSize size, 1284 Register rt, 1285 const MemOperand& operand); 1286 1287 void strd(Condition cond, 1288 Register rt, 1289 Register rt2, 1290 const MemOperand& operand); 1291 1292 void strex(Condition cond, 1293 Register rd, 1294 Register rt, 1295 const MemOperand& operand); 1296 1297 void strexb(Condition cond, 1298 Register rd, 1299 Register rt, 1300 const MemOperand& operand); 1301 1302 void strexd(Condition cond, 1303 Register rd, 1304 Register rt, 1305 Register rt2, 1306 const MemOperand& operand); 1307 1308 void strexh(Condition cond, 1309 Register rd, 1310 Register rt, 1311 const MemOperand& operand); 1312 1313 void strh(Condition cond, 1314 EncodingSize size, 1315 Register rt, 1316 const MemOperand& operand); 1317 1318 void sub(Condition cond, 1319 EncodingSize size, 1320 Register rd, 1321 Register rn, 1322 const Operand& operand); 1323 1324 void sub(Condition cond, Register rd, const Operand& operand); 1325 1326 void subs(Condition cond, 1327 EncodingSize size, 1328 Register rd, 1329 Register rn, 1330 const Operand& operand); 1331 1332 void subs(Register rd, const Operand& operand); 1333 1334 void subw(Condition cond, Register rd, Register rn, const Operand& operand); 1335 1336 void svc(Condition cond, uint32_t imm); 1337 1338 void sxtab(Condition cond, Register rd, Register rn, const Operand& operand); 1339 1340 void sxtab16(Condition cond, 1341 Register rd, 1342 Register rn, 1343 const Operand& operand); 1344 1345 void sxtah(Condition cond, Register rd, Register rn, const Operand& operand); 1346 1347 void sxtb(Condition cond, 1348 EncodingSize size, 1349 Register rd, 1350 const Operand& operand); 1351 1352 void sxtb16(Condition cond, Register rd, const Operand& operand); 1353 1354 void sxth(Condition cond, 1355 EncodingSize size, 1356 Register rd, 1357 const Operand& operand); 1358 1359 void tbb(Condition cond, Register rn, Register rm); 1360 1361 void tbh(Condition cond, Register rn, Register rm); 1362 1363 void teq(Condition cond, Register rn, const Operand& operand); 1364 1365 void tst(Condition cond, 1366 EncodingSize size, 1367 Register rn, 1368 const Operand& operand); 1369 1370 void uadd16(Condition cond, Register rd, Register rn, Register rm); 1371 1372 void uadd8(Condition cond, Register rd, Register rn, Register rm); 1373 1374 void uasx(Condition cond, Register rd, Register rn, Register rm); 1375 1376 void ubfx( 1377 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width); 1378 1379 void udf(Condition cond, EncodingSize size, uint32_t imm); 1380 1381 void udiv(Condition cond, Register rd, Register rn, Register rm); 1382 1383 void uhadd16(Condition cond, Register rd, Register rn, Register rm); 1384 1385 void uhadd8(Condition cond, Register rd, Register rn, Register rm); 1386 1387 void uhasx(Condition cond, Register rd, Register rn, Register rm); 1388 1389 void uhsax(Condition cond, Register rd, Register rn, Register rm); 1390 1391 void uhsub16(Condition cond, Register rd, Register rn, Register rm); 1392 1393 void uhsub8(Condition cond, Register rd, Register rn, Register rm); 1394 1395 void umaal( 1396 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1397 1398 void umlal( 1399 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1400 1401 void umlals( 1402 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1403 1404 void umull( 1405 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1406 1407 void umulls( 1408 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 1409 1410 void uqadd16(Condition cond, Register rd, Register rn, Register rm); 1411 1412 void uqadd8(Condition cond, Register rd, Register rn, Register rm); 1413 1414 void uqasx(Condition cond, Register rd, Register rn, Register rm); 1415 1416 void uqsax(Condition cond, Register rd, Register rn, Register rm); 1417 1418 void uqsub16(Condition cond, Register rd, Register rn, Register rm); 1419 1420 void uqsub8(Condition cond, Register rd, Register rn, Register rm); 1421 1422 void usad8(Condition cond, Register rd, Register rn, Register rm); 1423 1424 void usada8( 1425 Condition cond, Register rd, Register rn, Register rm, Register ra); 1426 1427 void usat(Condition cond, Register rd, uint32_t imm, const Operand& operand); 1428 1429 void usat16(Condition cond, Register rd, uint32_t imm, Register rn); 1430 1431 void usax(Condition cond, Register rd, Register rn, Register rm); 1432 1433 void usub16(Condition cond, Register rd, Register rn, Register rm); 1434 1435 void usub8(Condition cond, Register rd, Register rn, Register rm); 1436 1437 void uxtab(Condition cond, Register rd, Register rn, const Operand& operand); 1438 1439 void uxtab16(Condition cond, 1440 Register rd, 1441 Register rn, 1442 const Operand& operand); 1443 1444 void uxtah(Condition cond, Register rd, Register rn, const Operand& operand); 1445 1446 void uxtb(Condition cond, 1447 EncodingSize size, 1448 Register rd, 1449 const Operand& operand); 1450 1451 void uxtb16(Condition cond, Register rd, const Operand& operand); 1452 1453 void uxth(Condition cond, 1454 EncodingSize size, 1455 Register rd, 1456 const Operand& operand); 1457 1458 void vaba( 1459 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1460 1461 void vaba( 1462 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1463 1464 void vabal( 1465 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 1466 1467 void vabd( 1468 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1469 1470 void vabd( 1471 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1472 1473 void vabdl( 1474 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 1475 1476 void vabs(Condition cond, DataType dt, DRegister rd, DRegister rm); 1477 1478 void vabs(Condition cond, DataType dt, QRegister rd, QRegister rm); 1479 1480 void vabs(Condition cond, DataType dt, SRegister rd, SRegister rm); 1481 1482 void vacge( 1483 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1484 1485 void vacge( 1486 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1487 1488 void vacgt( 1489 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1490 1491 void vacgt( 1492 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1493 1494 void vacle( 1495 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1496 1497 void vacle( 1498 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1499 1500 void vaclt( 1501 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1502 1503 void vaclt( 1504 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1505 1506 void vadd( 1507 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1508 1509 void vadd( 1510 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1511 1512 void vadd( 1513 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 1514 1515 void vaddhn( 1516 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 1517 1518 void vaddl( 1519 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 1520 1521 void vaddw( 1522 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm); 1523 1524 void vand(Condition cond, 1525 DataType dt, 1526 DRegister rd, 1527 DRegister rn, 1528 const DOperand& operand); 1529 1530 void vand(Condition cond, 1531 DataType dt, 1532 QRegister rd, 1533 QRegister rn, 1534 const QOperand& operand); 1535 1536 void vbic(Condition cond, 1537 DataType dt, 1538 DRegister rd, 1539 DRegister rn, 1540 const DOperand& operand); 1541 1542 void vbic(Condition cond, 1543 DataType dt, 1544 QRegister rd, 1545 QRegister rn, 1546 const QOperand& operand); 1547 1548 void vbif( 1549 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1550 1551 void vbif( 1552 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1553 1554 void vbit( 1555 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1556 1557 void vbit( 1558 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1559 1560 void vbsl( 1561 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1562 1563 void vbsl( 1564 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1565 1566 void vceq(Condition cond, 1567 DataType dt, 1568 DRegister rd, 1569 DRegister rm, 1570 const DOperand& operand); 1571 1572 void vceq(Condition cond, 1573 DataType dt, 1574 QRegister rd, 1575 QRegister rm, 1576 const QOperand& operand); 1577 1578 void vceq( 1579 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1580 1581 void vceq( 1582 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1583 1584 void vcge(Condition cond, 1585 DataType dt, 1586 DRegister rd, 1587 DRegister rm, 1588 const DOperand& operand); 1589 1590 void vcge(Condition cond, 1591 DataType dt, 1592 QRegister rd, 1593 QRegister rm, 1594 const QOperand& operand); 1595 1596 void vcge( 1597 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1598 1599 void vcge( 1600 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1601 1602 void vcgt(Condition cond, 1603 DataType dt, 1604 DRegister rd, 1605 DRegister rm, 1606 const DOperand& operand); 1607 1608 void vcgt(Condition cond, 1609 DataType dt, 1610 QRegister rd, 1611 QRegister rm, 1612 const QOperand& operand); 1613 1614 void vcgt( 1615 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1616 1617 void vcgt( 1618 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1619 1620 void vcle(Condition cond, 1621 DataType dt, 1622 DRegister rd, 1623 DRegister rm, 1624 const DOperand& operand); 1625 1626 void vcle(Condition cond, 1627 DataType dt, 1628 QRegister rd, 1629 QRegister rm, 1630 const QOperand& operand); 1631 1632 void vcle( 1633 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1634 1635 void vcle( 1636 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1637 1638 void vcls(Condition cond, DataType dt, DRegister rd, DRegister rm); 1639 1640 void vcls(Condition cond, DataType dt, QRegister rd, QRegister rm); 1641 1642 void vclt(Condition cond, 1643 DataType dt, 1644 DRegister rd, 1645 DRegister rm, 1646 const DOperand& operand); 1647 1648 void vclt(Condition cond, 1649 DataType dt, 1650 QRegister rd, 1651 QRegister rm, 1652 const QOperand& operand); 1653 1654 void vclt( 1655 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1656 1657 void vclt( 1658 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1659 1660 void vclz(Condition cond, DataType dt, DRegister rd, DRegister rm); 1661 1662 void vclz(Condition cond, DataType dt, QRegister rd, QRegister rm); 1663 1664 void vcmp(Condition cond, DataType dt, SRegister rd, const SOperand& operand); 1665 1666 void vcmp(Condition cond, DataType dt, DRegister rd, const DOperand& operand); 1667 1668 void vcmpe(Condition cond, 1669 DataType dt, 1670 SRegister rd, 1671 const SOperand& operand); 1672 1673 void vcmpe(Condition cond, 1674 DataType dt, 1675 DRegister rd, 1676 const DOperand& operand); 1677 1678 void vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm); 1679 1680 void vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm); 1681 1682 void vcvt( 1683 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 1684 1685 void vcvt( 1686 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 1687 1688 void vcvt(Condition cond, 1689 DataType dt1, 1690 DataType dt2, 1691 DRegister rd, 1692 DRegister rm, 1693 int32_t fbits); 1694 1695 void vcvt(Condition cond, 1696 DataType dt1, 1697 DataType dt2, 1698 QRegister rd, 1699 QRegister rm, 1700 int32_t fbits); 1701 1702 void vcvt(Condition cond, 1703 DataType dt1, 1704 DataType dt2, 1705 SRegister rd, 1706 SRegister rm, 1707 int32_t fbits); 1708 1709 void vcvt( 1710 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 1711 1712 void vcvt( 1713 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm); 1714 1715 void vcvt( 1716 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm); 1717 1718 void vcvt( 1719 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm); 1720 1721 void vcvt( 1722 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 1723 1724 void vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 1725 1726 void vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 1727 1728 void vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 1729 1730 void vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 1731 1732 void vcvtb( 1733 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 1734 1735 void vcvtb( 1736 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 1737 1738 void vcvtb( 1739 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 1740 1741 void vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 1742 1743 void vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 1744 1745 void vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 1746 1747 void vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 1748 1749 void vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 1750 1751 void vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 1752 1753 void vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 1754 1755 void vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 1756 1757 void vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 1758 1759 void vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 1760 1761 void vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 1762 1763 void vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 1764 1765 void vcvtr( 1766 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 1767 1768 void vcvtr( 1769 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 1770 1771 void vcvtt( 1772 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 1773 1774 void vcvtt( 1775 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 1776 1777 void vcvtt( 1778 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 1779 1780 void vdiv( 1781 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 1782 1783 void vdiv( 1784 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1785 1786 void vdup(Condition cond, DataType dt, QRegister rd, Register rt); 1787 1788 void vdup(Condition cond, DataType dt, DRegister rd, Register rt); 1789 1790 void vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm); 1791 1792 void vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm); 1793 1794 void veor( 1795 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1796 1797 void veor( 1798 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1799 1800 void vext(Condition cond, 1801 DataType dt, 1802 DRegister rd, 1803 DRegister rn, 1804 DRegister rm, 1805 const DOperand& operand); 1806 1807 void vext(Condition cond, 1808 DataType dt, 1809 QRegister rd, 1810 QRegister rn, 1811 QRegister rm, 1812 const QOperand& operand); 1813 1814 void vfma( 1815 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1816 1817 void vfma( 1818 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1819 1820 void vfma( 1821 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 1822 1823 void vfms( 1824 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1825 1826 void vfms( 1827 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1828 1829 void vfms( 1830 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 1831 1832 void vfnma( 1833 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 1834 1835 void vfnma( 1836 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1837 1838 void vfnms( 1839 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 1840 1841 void vfnms( 1842 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1843 1844 void vhadd( 1845 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1846 1847 void vhadd( 1848 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1849 1850 void vhsub( 1851 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1852 1853 void vhsub( 1854 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1855 1856 void vld1(Condition cond, 1857 DataType dt, 1858 const NeonRegisterList& nreglist, 1859 const AlignedMemOperand& operand); 1860 1861 void vld2(Condition cond, 1862 DataType dt, 1863 const NeonRegisterList& nreglist, 1864 const AlignedMemOperand& operand); 1865 1866 void vld3(Condition cond, 1867 DataType dt, 1868 const NeonRegisterList& nreglist, 1869 const AlignedMemOperand& operand); 1870 1871 void vld3(Condition cond, 1872 DataType dt, 1873 const NeonRegisterList& nreglist, 1874 const MemOperand& operand); 1875 1876 void vld4(Condition cond, 1877 DataType dt, 1878 const NeonRegisterList& nreglist, 1879 const AlignedMemOperand& operand); 1880 1881 void vldm(Condition cond, 1882 DataType dt, 1883 Register rn, 1884 WriteBack write_back, 1885 DRegisterList dreglist); 1886 1887 void vldm(Condition cond, 1888 DataType dt, 1889 Register rn, 1890 WriteBack write_back, 1891 SRegisterList sreglist); 1892 1893 void vldmdb(Condition cond, 1894 DataType dt, 1895 Register rn, 1896 WriteBack write_back, 1897 DRegisterList dreglist); 1898 1899 void vldmdb(Condition cond, 1900 DataType dt, 1901 Register rn, 1902 WriteBack write_back, 1903 SRegisterList sreglist); 1904 1905 void vldmia(Condition cond, 1906 DataType dt, 1907 Register rn, 1908 WriteBack write_back, 1909 DRegisterList dreglist); 1910 1911 void vldmia(Condition cond, 1912 DataType dt, 1913 Register rn, 1914 WriteBack write_back, 1915 SRegisterList sreglist); 1916 1917 void vldr(Condition cond, DataType dt, DRegister rd, Location* location); 1918 1919 void vldr(Condition cond, 1920 DataType dt, 1921 DRegister rd, 1922 const MemOperand& operand); 1923 1924 void vldr(Condition cond, DataType dt, SRegister rd, Location* location); 1925 1926 void vldr(Condition cond, 1927 DataType dt, 1928 SRegister rd, 1929 const MemOperand& operand); 1930 1931 void vmax( 1932 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1933 1934 void vmax( 1935 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1936 1937 void vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm); 1938 1939 void vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm); 1940 1941 void vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm); 1942 1943 void vmin( 1944 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1945 1946 void vmin( 1947 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1948 1949 void vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm); 1950 1951 void vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm); 1952 1953 void vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm); 1954 1955 void vmla(Condition cond, 1956 DataType dt, 1957 DRegister rd, 1958 DRegister rn, 1959 DRegisterLane rm); 1960 1961 void vmla(Condition cond, 1962 DataType dt, 1963 QRegister rd, 1964 QRegister rn, 1965 DRegisterLane rm); 1966 1967 void vmla( 1968 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1969 1970 void vmla( 1971 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 1972 1973 void vmla( 1974 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 1975 1976 void vmlal(Condition cond, 1977 DataType dt, 1978 QRegister rd, 1979 DRegister rn, 1980 DRegisterLane rm); 1981 1982 void vmlal( 1983 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 1984 1985 void vmls(Condition cond, 1986 DataType dt, 1987 DRegister rd, 1988 DRegister rn, 1989 DRegisterLane rm); 1990 1991 void vmls(Condition cond, 1992 DataType dt, 1993 QRegister rd, 1994 QRegister rn, 1995 DRegisterLane rm); 1996 1997 void vmls( 1998 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 1999 2000 void vmls( 2001 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 2002 2003 void vmls( 2004 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 2005 2006 void vmlsl(Condition cond, 2007 DataType dt, 2008 QRegister rd, 2009 DRegister rn, 2010 DRegisterLane rm); 2011 2012 void vmlsl( 2013 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 2014 2015 void vmov(Condition cond, Register rt, SRegister rn); 2016 2017 void vmov(Condition cond, SRegister rn, Register rt); 2018 2019 void vmov(Condition cond, Register rt, Register rt2, DRegister rm); 2020 2021 void vmov(Condition cond, DRegister rm, Register rt, Register rt2); 2022 2023 void vmov( 2024 Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1); 2025 2026 void vmov( 2027 Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2); 2028 2029 void vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt); 2030 2031 void vmov(Condition cond, DataType dt, DRegister rd, const DOperand& operand); 2032 2033 void vmov(Condition cond, DataType dt, QRegister rd, const QOperand& operand); 2034 2035 void vmov(Condition cond, DataType dt, SRegister rd, const SOperand& operand); 2036 2037 void vmov(Condition cond, DataType dt, Register rt, DRegisterLane rn); 2038 2039 void vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm); 2040 2041 void vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm); 2042 2043 void vmrs(Condition cond, RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg); 2044 2045 void vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt); 2046 2047 void vmul(Condition cond, 2048 DataType dt, 2049 DRegister rd, 2050 DRegister rn, 2051 DRegister dm, 2052 unsigned index); 2053 2054 void vmul(Condition cond, 2055 DataType dt, 2056 QRegister rd, 2057 QRegister rn, 2058 DRegister dm, 2059 unsigned index); 2060 2061 void vmul( 2062 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2063 2064 void vmul( 2065 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 2066 2067 void vmul( 2068 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 2069 2070 void vmull(Condition cond, 2071 DataType dt, 2072 QRegister rd, 2073 DRegister rn, 2074 DRegister dm, 2075 unsigned index); 2076 2077 void vmull( 2078 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 2079 2080 void vmvn(Condition cond, DataType dt, DRegister rd, const DOperand& operand); 2081 2082 void vmvn(Condition cond, DataType dt, QRegister rd, const QOperand& operand); 2083 2084 void vneg(Condition cond, DataType dt, DRegister rd, DRegister rm); 2085 2086 void vneg(Condition cond, DataType dt, QRegister rd, QRegister rm); 2087 2088 void vneg(Condition cond, DataType dt, SRegister rd, SRegister rm); 2089 2090 void vnmla( 2091 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 2092 2093 void vnmla( 2094 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2095 2096 void vnmls( 2097 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 2098 2099 void vnmls( 2100 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2101 2102 void vnmul( 2103 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 2104 2105 void vnmul( 2106 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2107 2108 void vorn(Condition cond, 2109 DataType dt, 2110 DRegister rd, 2111 DRegister rn, 2112 const DOperand& operand); 2113 2114 void vorn(Condition cond, 2115 DataType dt, 2116 QRegister rd, 2117 QRegister rn, 2118 const QOperand& operand); 2119 2120 void vorr(Condition cond, 2121 DataType dt, 2122 DRegister rd, 2123 DRegister rn, 2124 const DOperand& operand); 2125 2126 void vorr(Condition cond, 2127 DataType dt, 2128 QRegister rd, 2129 QRegister rn, 2130 const QOperand& operand); 2131 2132 void vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm); 2133 2134 void vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm); 2135 2136 void vpadd( 2137 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2138 2139 void vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm); 2140 2141 void vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm); 2142 2143 void vpmax( 2144 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2145 2146 void vpmin( 2147 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2148 2149 void vpop(Condition cond, DataType dt, DRegisterList dreglist); 2150 2151 void vpop(Condition cond, DataType dt, SRegisterList sreglist); 2152 2153 void vpush(Condition cond, DataType dt, DRegisterList dreglist); 2154 2155 void vpush(Condition cond, DataType dt, SRegisterList sreglist); 2156 2157 void vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm); 2158 2159 void vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm); 2160 2161 void vqadd( 2162 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2163 2164 void vqadd( 2165 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 2166 2167 void vqdmlal( 2168 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 2169 2170 void vqdmlal(Condition cond, 2171 DataType dt, 2172 QRegister rd, 2173 DRegister rn, 2174 DRegister dm, 2175 unsigned index); 2176 2177 void vqdmlsl( 2178 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 2179 2180 void vqdmlsl(Condition cond, 2181 DataType dt, 2182 QRegister rd, 2183 DRegister rn, 2184 DRegister dm, 2185 unsigned index); 2186 2187 void vqdmulh( 2188 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2189 2190 void vqdmulh( 2191 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 2192 2193 void vqdmulh(Condition cond, 2194 DataType dt, 2195 DRegister rd, 2196 DRegister rn, 2197 DRegisterLane rm); 2198 2199 void vqdmulh(Condition cond, 2200 DataType dt, 2201 QRegister rd, 2202 QRegister rn, 2203 DRegisterLane rm); 2204 2205 void vqdmull( 2206 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 2207 2208 void vqdmull(Condition cond, 2209 DataType dt, 2210 QRegister rd, 2211 DRegister rn, 2212 DRegisterLane rm); 2213 2214 void vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm); 2215 2216 void vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm); 2217 2218 void vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm); 2219 2220 void vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm); 2221 2222 void vqrdmulh( 2223 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2224 2225 void vqrdmulh( 2226 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 2227 2228 void vqrdmulh(Condition cond, 2229 DataType dt, 2230 DRegister rd, 2231 DRegister rn, 2232 DRegisterLane rm); 2233 2234 void vqrdmulh(Condition cond, 2235 DataType dt, 2236 QRegister rd, 2237 QRegister rn, 2238 DRegisterLane rm); 2239 2240 void vqrshl( 2241 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn); 2242 2243 void vqrshl( 2244 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn); 2245 2246 void vqrshrn(Condition cond, 2247 DataType dt, 2248 DRegister rd, 2249 QRegister rm, 2250 const QOperand& operand); 2251 2252 void vqrshrun(Condition cond, 2253 DataType dt, 2254 DRegister rd, 2255 QRegister rm, 2256 const QOperand& operand); 2257 2258 void vqshl(Condition cond, 2259 DataType dt, 2260 DRegister rd, 2261 DRegister rm, 2262 const DOperand& operand); 2263 2264 void vqshl(Condition cond, 2265 DataType dt, 2266 QRegister rd, 2267 QRegister rm, 2268 const QOperand& operand); 2269 2270 void vqshlu(Condition cond, 2271 DataType dt, 2272 DRegister rd, 2273 DRegister rm, 2274 const DOperand& operand); 2275 2276 void vqshlu(Condition cond, 2277 DataType dt, 2278 QRegister rd, 2279 QRegister rm, 2280 const QOperand& operand); 2281 2282 void vqshrn(Condition cond, 2283 DataType dt, 2284 DRegister rd, 2285 QRegister rm, 2286 const QOperand& operand); 2287 2288 void vqshrun(Condition cond, 2289 DataType dt, 2290 DRegister rd, 2291 QRegister rm, 2292 const QOperand& operand); 2293 2294 void vqsub( 2295 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2296 2297 void vqsub( 2298 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 2299 2300 void vraddhn( 2301 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 2302 2303 void vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm); 2304 2305 void vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm); 2306 2307 void vrecps( 2308 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2309 2310 void vrecps( 2311 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 2312 2313 void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm); 2314 2315 void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm); 2316 2317 void vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm); 2318 2319 void vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm); 2320 2321 void vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm); 2322 2323 void vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm); 2324 2325 void vrhadd( 2326 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2327 2328 void vrhadd( 2329 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 2330 2331 void vrinta(DataType dt, DRegister rd, DRegister rm); 2332 2333 void vrinta(DataType dt, QRegister rd, QRegister rm); 2334 2335 void vrinta(DataType dt, SRegister rd, SRegister rm); 2336 2337 void vrintm(DataType dt, DRegister rd, DRegister rm); 2338 2339 void vrintm(DataType dt, QRegister rd, QRegister rm); 2340 2341 void vrintm(DataType dt, SRegister rd, SRegister rm); 2342 2343 void vrintn(DataType dt, DRegister rd, DRegister rm); 2344 2345 void vrintn(DataType dt, QRegister rd, QRegister rm); 2346 2347 void vrintn(DataType dt, SRegister rd, SRegister rm); 2348 2349 void vrintp(DataType dt, DRegister rd, DRegister rm); 2350 2351 void vrintp(DataType dt, QRegister rd, QRegister rm); 2352 2353 void vrintp(DataType dt, SRegister rd, SRegister rm); 2354 2355 void vrintr(Condition cond, DataType dt, SRegister rd, SRegister rm); 2356 2357 void vrintr(Condition cond, DataType dt, DRegister rd, DRegister rm); 2358 2359 void vrintx(Condition cond, DataType dt, DRegister rd, DRegister rm); 2360 2361 void vrintx(DataType dt, QRegister rd, QRegister rm); 2362 2363 void vrintx(Condition cond, DataType dt, SRegister rd, SRegister rm); 2364 2365 void vrintz(Condition cond, DataType dt, DRegister rd, DRegister rm); 2366 2367 void vrintz(DataType dt, QRegister rd, QRegister rm); 2368 2369 void vrintz(Condition cond, DataType dt, SRegister rd, SRegister rm); 2370 2371 void vrshl( 2372 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn); 2373 2374 void vrshl( 2375 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn); 2376 2377 void vrshr(Condition cond, 2378 DataType dt, 2379 DRegister rd, 2380 DRegister rm, 2381 const DOperand& operand); 2382 2383 void vrshr(Condition cond, 2384 DataType dt, 2385 QRegister rd, 2386 QRegister rm, 2387 const QOperand& operand); 2388 2389 void vrshrn(Condition cond, 2390 DataType dt, 2391 DRegister rd, 2392 QRegister rm, 2393 const QOperand& operand); 2394 2395 void vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm); 2396 2397 void vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm); 2398 2399 void vrsqrts( 2400 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2401 2402 void vrsqrts( 2403 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 2404 2405 void vrsra(Condition cond, 2406 DataType dt, 2407 DRegister rd, 2408 DRegister rm, 2409 const DOperand& operand); 2410 2411 void vrsra(Condition cond, 2412 DataType dt, 2413 QRegister rd, 2414 QRegister rm, 2415 const QOperand& operand); 2416 2417 void vrsubhn( 2418 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 2419 2420 void vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm); 2421 2422 void vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm); 2423 2424 void vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm); 2425 2426 void vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm); 2427 2428 void vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm); 2429 2430 void vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm); 2431 2432 void vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm); 2433 2434 void vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm); 2435 2436 void vshl(Condition cond, 2437 DataType dt, 2438 DRegister rd, 2439 DRegister rm, 2440 const DOperand& operand); 2441 2442 void vshl(Condition cond, 2443 DataType dt, 2444 QRegister rd, 2445 QRegister rm, 2446 const QOperand& operand); 2447 2448 void vshll(Condition cond, 2449 DataType dt, 2450 QRegister rd, 2451 DRegister rm, 2452 const DOperand& operand); 2453 2454 void vshr(Condition cond, 2455 DataType dt, 2456 DRegister rd, 2457 DRegister rm, 2458 const DOperand& operand); 2459 2460 void vshr(Condition cond, 2461 DataType dt, 2462 QRegister rd, 2463 QRegister rm, 2464 const QOperand& operand); 2465 2466 void vshrn(Condition cond, 2467 DataType dt, 2468 DRegister rd, 2469 QRegister rm, 2470 const QOperand& operand); 2471 2472 void vsli(Condition cond, 2473 DataType dt, 2474 DRegister rd, 2475 DRegister rm, 2476 const DOperand& operand); 2477 2478 void vsli(Condition cond, 2479 DataType dt, 2480 QRegister rd, 2481 QRegister rm, 2482 const QOperand& operand); 2483 2484 void vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm); 2485 2486 void vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm); 2487 2488 void vsra(Condition cond, 2489 DataType dt, 2490 DRegister rd, 2491 DRegister rm, 2492 const DOperand& operand); 2493 2494 void vsra(Condition cond, 2495 DataType dt, 2496 QRegister rd, 2497 QRegister rm, 2498 const QOperand& operand); 2499 2500 void vsri(Condition cond, 2501 DataType dt, 2502 DRegister rd, 2503 DRegister rm, 2504 const DOperand& operand); 2505 2506 void vsri(Condition cond, 2507 DataType dt, 2508 QRegister rd, 2509 QRegister rm, 2510 const QOperand& operand); 2511 2512 void vst1(Condition cond, 2513 DataType dt, 2514 const NeonRegisterList& nreglist, 2515 const AlignedMemOperand& operand); 2516 2517 void vst2(Condition cond, 2518 DataType dt, 2519 const NeonRegisterList& nreglist, 2520 const AlignedMemOperand& operand); 2521 2522 void vst3(Condition cond, 2523 DataType dt, 2524 const NeonRegisterList& nreglist, 2525 const AlignedMemOperand& operand); 2526 2527 void vst3(Condition cond, 2528 DataType dt, 2529 const NeonRegisterList& nreglist, 2530 const MemOperand& operand); 2531 2532 void vst4(Condition cond, 2533 DataType dt, 2534 const NeonRegisterList& nreglist, 2535 const AlignedMemOperand& operand); 2536 2537 void vstm(Condition cond, 2538 DataType dt, 2539 Register rn, 2540 WriteBack write_back, 2541 DRegisterList dreglist); 2542 2543 void vstm(Condition cond, 2544 DataType dt, 2545 Register rn, 2546 WriteBack write_back, 2547 SRegisterList sreglist); 2548 2549 void vstmdb(Condition cond, 2550 DataType dt, 2551 Register rn, 2552 WriteBack write_back, 2553 DRegisterList dreglist); 2554 2555 void vstmdb(Condition cond, 2556 DataType dt, 2557 Register rn, 2558 WriteBack write_back, 2559 SRegisterList sreglist); 2560 2561 void vstmia(Condition cond, 2562 DataType dt, 2563 Register rn, 2564 WriteBack write_back, 2565 DRegisterList dreglist); 2566 2567 void vstmia(Condition cond, 2568 DataType dt, 2569 Register rn, 2570 WriteBack write_back, 2571 SRegisterList sreglist); 2572 2573 void vstr(Condition cond, 2574 DataType dt, 2575 DRegister rd, 2576 const MemOperand& operand); 2577 2578 void vstr(Condition cond, 2579 DataType dt, 2580 SRegister rd, 2581 const MemOperand& operand); 2582 2583 void vsub( 2584 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2585 2586 void vsub( 2587 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 2588 2589 void vsub( 2590 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 2591 2592 void vsubhn( 2593 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 2594 2595 void vsubl( 2596 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 2597 2598 void vsubw( 2599 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm); 2600 2601 void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm); 2602 2603 void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm); 2604 2605 void vtbl(Condition cond, 2606 DataType dt, 2607 DRegister rd, 2608 const NeonRegisterList& nreglist, 2609 DRegister rm); 2610 2611 void vtbx(Condition cond, 2612 DataType dt, 2613 DRegister rd, 2614 const NeonRegisterList& nreglist, 2615 DRegister rm); 2616 2617 void vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm); 2618 2619 void vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm); 2620 2621 void vtst( 2622 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 2623 2624 void vtst( 2625 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 2626 2627 void vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm); 2628 2629 void vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm); 2630 2631 void vzip(Condition cond, DataType dt, DRegister rd, DRegister rm); 2632 2633 void vzip(Condition cond, DataType dt, QRegister rd, QRegister rm); 2634 2635 void yield(Condition cond, EncodingSize size); 2636 2637 int T32Size(uint32_t instr); 2638 void DecodeT32(uint32_t instr); 2639 void DecodeA32(uint32_t instr); 2640 }; 2641 2642 DataTypeValue Dt_L_imm6_1_Decode(uint32_t value, uint32_t type_value); 2643 DataTypeValue Dt_L_imm6_2_Decode(uint32_t value, uint32_t type_value); 2644 DataTypeValue Dt_L_imm6_3_Decode(uint32_t value); 2645 DataTypeValue Dt_L_imm6_4_Decode(uint32_t value); 2646 DataTypeValue Dt_imm6_1_Decode(uint32_t value, uint32_t type_value); 2647 DataTypeValue Dt_imm6_2_Decode(uint32_t value, uint32_t type_value); 2648 DataTypeValue Dt_imm6_3_Decode(uint32_t value); 2649 DataTypeValue Dt_imm6_4_Decode(uint32_t value, uint32_t type_value); 2650 DataTypeValue Dt_op_U_size_1_Decode(uint32_t value); 2651 DataTypeValue Dt_op_size_1_Decode(uint32_t value); 2652 DataTypeValue Dt_op_size_2_Decode(uint32_t value); 2653 DataTypeValue Dt_op_size_3_Decode(uint32_t value); 2654 DataTypeValue Dt_U_imm3H_1_Decode(uint32_t value); 2655 DataTypeValue Dt_U_opc1_opc2_1_Decode(uint32_t value, unsigned* lane); 2656 DataTypeValue Dt_opc1_opc2_1_Decode(uint32_t value, unsigned* lane); 2657 DataTypeValue Dt_imm4_1_Decode(uint32_t value, unsigned* lane); 2658 DataTypeValue Dt_B_E_1_Decode(uint32_t value); 2659 DataTypeValue Dt_op_1_Decode1(uint32_t value); 2660 DataTypeValue Dt_op_1_Decode2(uint32_t value); 2661 DataTypeValue Dt_op_2_Decode(uint32_t value); 2662 DataTypeValue Dt_op_3_Decode(uint32_t value); 2663 DataTypeValue Dt_U_sx_1_Decode(uint32_t value); 2664 DataTypeValue Dt_op_U_1_Decode1(uint32_t value); 2665 DataTypeValue Dt_op_U_1_Decode2(uint32_t value); 2666 DataTypeValue Dt_sz_1_Decode(uint32_t value); 2667 DataTypeValue Dt_F_size_1_Decode(uint32_t value); 2668 DataTypeValue Dt_F_size_2_Decode(uint32_t value); 2669 DataTypeValue Dt_F_size_3_Decode(uint32_t value); 2670 DataTypeValue Dt_F_size_4_Decode(uint32_t value); 2671 DataTypeValue Dt_U_size_1_Decode(uint32_t value); 2672 DataTypeValue Dt_U_size_2_Decode(uint32_t value); 2673 DataTypeValue Dt_U_size_3_Decode(uint32_t value); 2674 DataTypeValue Dt_size_1_Decode(uint32_t value); 2675 DataTypeValue Dt_size_2_Decode(uint32_t value); 2676 DataTypeValue Dt_size_3_Decode(uint32_t value); 2677 DataTypeValue Dt_size_4_Decode(uint32_t value); 2678 DataTypeValue Dt_size_5_Decode(uint32_t value); 2679 DataTypeValue Dt_size_6_Decode(uint32_t value); 2680 DataTypeValue Dt_size_7_Decode(uint32_t value); 2681 DataTypeValue Dt_size_8_Decode(uint32_t value); 2682 DataTypeValue Dt_size_9_Decode(uint32_t value, uint32_t type_value); 2683 DataTypeValue Dt_size_10_Decode(uint32_t value); 2684 DataTypeValue Dt_size_11_Decode(uint32_t value, uint32_t type_value); 2685 DataTypeValue Dt_size_12_Decode(uint32_t value, uint32_t type_value); 2686 DataTypeValue Dt_size_13_Decode(uint32_t value); 2687 DataTypeValue Dt_size_14_Decode(uint32_t value); 2688 DataTypeValue Dt_size_15_Decode(uint32_t value); 2689 DataTypeValue Dt_size_16_Decode(uint32_t value); 2690 DataTypeValue Dt_size_17_Decode(uint32_t value); 2691 // End of generated code. 2692 2693 class PrintDisassembler : public Disassembler { 2694 public: 2695 #ifndef PANDA_BUILD 2696 explicit PrintDisassembler(std::ostream& os, // NOLINT(runtime/references) 2697 uint32_t code_address = 0) Disassembler(os,code_address)2698 : Disassembler(os, code_address) {} 2699 #else 2700 explicit PrintDisassembler(std::ostream& os, // NOLINT(runtime/references) 2701 uint32_t code_address = 0) = delete; 2702 PrintDisassembler(PandaAllocator* allocator, std::ostream& os, // NOLINT(runtime/references) 2703 uint32_t code_address = 0) 2704 : Disassembler(allocator, os, code_address) {} 2705 2706 #endif 2707 explicit PrintDisassembler(DisassemblerStream* os, uint32_t code_address = 0) Disassembler(os,code_address)2708 : Disassembler(os, code_address) {} 2709 PrintCodeAddress(uint32_t code_address)2710 virtual void PrintCodeAddress(uint32_t code_address) { 2711 if (code_address != 0) { 2712 os() << "0x" << std::hex << std::setw(8) << std::setfill('0') 2713 << code_address << "\t"; 2714 } 2715 } 2716 PrintOpcode16(uint32_t opcode)2717 virtual void PrintOpcode16(uint32_t opcode) { 2718 os() << std::hex << std::setw(4) << std::setfill('0') << opcode << " " 2719 << std::dec << "\t"; 2720 } 2721 PrintOpcode32(uint32_t opcode)2722 virtual void PrintOpcode32(uint32_t opcode) { 2723 os() << std::hex << std::setw(8) << std::setfill('0') << opcode << std::dec 2724 << "\t"; 2725 } 2726 DecodeA32At(const uint32_t * instruction_address)2727 const uint32_t* DecodeA32At(const uint32_t* instruction_address) { 2728 DecodeA32(*instruction_address); 2729 return instruction_address + 1; 2730 } 2731 2732 // Returns the address of the next instruction. 2733 const uint16_t* DecodeT32At(const uint16_t* instruction_address, 2734 const uint16_t* buffer_end); 2735 void DecodeT32(uint32_t instruction); 2736 void DecodeA32(uint32_t instruction); 2737 void DisassembleA32Buffer(const uint32_t* buffer, size_t size_in_bytes); 2738 void DisassembleT32Buffer(const uint16_t* buffer, size_t size_in_bytes); 2739 }; 2740 2741 } // namespace aarch32 2742 } // namespace vixl 2743 2744 #endif // VIXL_DISASM_AARCH32_H_ 2745