| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 83 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
292 const unsigned *Regs) { in decodeBDAddr12Operand()
302 const unsigned *Regs) { in decodeBDAddr20Operand()
312 const unsigned *Regs) { in decodeBDXAddr12Operand()
324 const unsigned *Regs) { in decodeBDXAddr20Operand()
336 const unsigned *Regs) { in decodeBDLAddr12Len4Operand()
348 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
360 const unsigned *Regs) { in decodeBDRAddr12Operand()
372 const unsigned *Regs) { in decodeBDVAddr12Operand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 212 [&](ArrayRef<Register> Regs) { in lowerReturn()
357 [&](ArrayRef<Register> Regs) { in lowerFormalArguments()
418 [&](ArrayRef<Register> Regs) { in lowerCall()
468 [&](ArrayRef<Register> Regs) { in lowerCall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 344 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
385 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
412 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
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| D | RegisterPressure.h | 275 RegSet Regs; variable
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/ |
| D | HWEventListener.h | 74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 135 static const unsigned Regs[2][2] = { in getFrameRegister() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUPALMetadata.cpp | 161 auto Regs = getRegisters(); in getRegister() local
555 auto Regs = getRegisters(); in toString() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | RDFRegisters.cpp | 324 auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) { in makeRegRef()
334 BitVector Regs(PRI.getTRI().getNumRegs()); in makeRegRef() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1117 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
1126 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
1135 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1173 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1344 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1366 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1420 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1459 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1514 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1543 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 281 [&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) { in lowerReturnVal()
491 ArrayRef<Register> Regs, in packSplitRegsToOrigType()
653 [&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) { in lowerFormalArguments()
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| D | SILoadStoreOptimizer.cpp | 520 const unsigned Regs = getRegs(I->getOpcode(), TII); in setMI() local
1236 const unsigned Regs = getRegs(Opcode, *TII); in mergeBufferLoadPair() local
1298 const unsigned Regs = getRegs(Opcode, *TII); in mergeTBufferLoadPair() local
1377 const unsigned Regs = getRegs(Opcode, *TII); in mergeTBufferStorePair() local
1539 const unsigned Regs = getRegs(Opcode, *TII); in mergeBufferStorePair() local
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| D | SIMachineFunctionInfo.cpp | 344 auto Regs = RC.getRegisters(); in allocateVGPRSpillToAGPR() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in INITIALIZE_PASS()
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| D | ARMLoadStoreOptimizer.cpp | 612 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, in ContainsReg()
627 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreMulti()
834 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreDouble()
860 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 47 SmallVector<Register, 4> Regs; member
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| D | LegalizationArtifactCombiner.h | 364 SmallVector<Register, 2> Regs; in tryCombineMerges() local
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| D | IRTranslator.h | 566 auto Regs = getOrCreateVRegs(Val); in getOrCreateVReg() local
|
| /third_party/mesa3d/include/android_stub/backtrace/ |
| D | Backtrace.h | 103 class Regs; variable
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ExecutionDomainFix.cpp | 329 SmallVector<int, 4> Regs; in visitSoftInstr() local
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| D | AggressiveAntiDepBreaker.cpp | 85 std::vector<unsigned> &Regs, in GetGroupRegs()
562 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
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| D | CallingConvLower.cpp | 199 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType()
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| D | MachineCopyPropagation.cpp | 99 void markRegsUnavailable(ArrayRef<unsigned> Regs, in markRegsUnavailable()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | IRTranslator.cpp | 164 auto *Regs = VMap.getVRegs(Val); in allocateVRegs() local
870 ArrayRef<Register> Regs = getOrCreateVRegs(LI); in translateLoad() local
1032 auto &Regs = *VMap.getVRegs(U); in translateBitCast() local
1879 auto &Regs = *VMap.getVRegs(U); in translateInsertElement() local
1903 auto &Regs = *VMap.getVRegs(U); in translateExtractElement() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVFrameLowering.cpp | 388 const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs(); in determineCalleeSaves() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 742 const unsigned *Regs, bool IsAddress) { in parseRegister()
759 const unsigned *Regs, RegisterKind Kind) { in parseRegister()
897 const unsigned *Regs, RegisterKind RegKind) { in parseAddress()
|