| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 636 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeDAHIDATIMMR6() local
650 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDAHIDATI() local
675 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
705 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP35GroupBranchMMR6() local
748 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch() local
778 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP37GroupBranchMMR6() local
819 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP65GroupBranchMMR6() local
858 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP75GroupBranchMMR6() local
900 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch() local
945 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/ |
| D | MSP430Disassembler.cpp | 154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode()
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI() local
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 209 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRsRt() local
222 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16() local
237 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16Rel() local
259 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitFtRsImm16() local
285 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRdRsRt() local
528 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "clz"); in clz() local
656 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "jalr"); in jalr() local
822 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "pseudo-move"); in move() local
841 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movf"); in movf() local
876 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movt"); in movt() local
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| D | IceAssemblerARM32.cpp | 344 IValueT Rs) { in encodeShiftRotateReg()
393 IValueT Rs; in encodeOperand() local
1129 IValueT Rn, IValueT Rm, IValueT Rs, in emitMulOp()
1718 IValueT Rs = encodeGPRegister(OpSrc1, "Rs", InstName); in emitShift() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1618 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1638 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1658 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1681 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1714 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1724 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1766 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1783 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1912 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitDouble.cpp | 147 const USet &Rs = I.second; in isInduction() local
375 Register Rs = MI->getOperand(1).getReg(); in profit() local
477 USet &Rs) { in collectIndRegsForLoop()
584 USet Rs; in collectIndRegs() local
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| D | HexagonConstExtenders.cpp | 293 Register Rs; member
446 HCE::Register Rs; member
1504 Register Rs = ExtI.second.Rs; // Only one reg allowed now. in calculatePlacement() local
1783 Register Rs = MI.getOperand(IsSub ? 3 : 2); in replaceInstrExpr() local
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| D | HexagonAsmPrinter.cpp | 409 MCOperand &Rs = Inst.getOperand(1); in HexagonProcessInstruction() local
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| D | HexagonBitTracker.cpp | 297 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
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| D | HexagonBitSimplify.cpp | 1884 const BitTracker::RegisterCell &RC, BitTracker::RegisterRef &Rs, in matchPackhl()
2018 BitTracker::RegisterRef Rs, Rt; in genPackhl() local
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| D | HexagonGenInsert.cpp | 1270 void IFOrdering::stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero, in stats()
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| D | HexagonFrameLowering.cpp | 2407 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); in expandAlloca() local
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| D | HexagonInstrInfo.cpp | 1236 Register Rs = Op2.getReg(); in expandPostRAPseudo() local
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| D | HexagonISelLowering.cpp | 2561 SDValue Rs[8]; in LowerBUILD_VECTOR() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVMergeBaseOffset.cpp | 138 Register Rs = TailAdd.getOperand(1).getReg(); in matchLargeOffset() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 200 MCOperand Rs, Rt; in getCompoundInsn() local
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | assembler-arm64.h | 2143 static Instr Rs(CPURegister rs) { in Rs() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1293 unsigned Rs = fieldFromInstruction(insn, 16, 5); in DecodeExclusiveLdStInstruction() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4086 unsigned Rs = Inst.getOperand(0).getReg(); in validateInstruction() local
4099 unsigned Rs = Inst.getOperand(0).getReg(); in validateInstruction() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 1520 unsigned Rs = MO1.getReg(); in getSORegRegOpValue() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 3528 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); in emitST_F16_PSEUDO() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1492 unsigned Rs = fieldFromInstruction(Val, 8, 4); in DecodeSORegRegOperand() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | ScalarEvolution.cpp | 997 SmallVector<const SCEV *, 2> Qs, Rs; in visitAddExpr() local
|