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1 // Copyright 2021 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #ifndef V8_CODEGEN_RISCV64_CONSTANTS_RISCV64_H_
6 #define V8_CODEGEN_RISCV64_CONSTANTS_RISCV64_H_
7 
8 #include "src/base/logging.h"
9 #include "src/base/macros.h"
10 #include "src/common/globals.h"
11 #include "src/flags/flags.h"
12 
13 // UNIMPLEMENTED_ macro for RISCV.
14 #ifdef DEBUG
15 #define UNIMPLEMENTED_RISCV()                                               \
16   v8::internal::PrintF("%s, \tline %d: \tfunction %s  not implemented. \n", \
17                        __FILE__, __LINE__, __func__);
18 #else
19 #define UNIMPLEMENTED_RISCV()
20 #endif
21 
22 #define UNSUPPORTED_RISCV() \
23   v8::internal::PrintF("Unsupported instruction %d.\n", __LINE__)
24 
25 enum Endianness { kLittle, kBig };
26 
27 #if defined(V8_TARGET_LITTLE_ENDIAN)
28 static const Endianness kArchEndian = kLittle;
29 #elif defined(V8_TARGET_BIG_ENDIAN)
30 static const Endianness kArchEndian = kBig;
31 #else
32 #error Unknown endianness
33 #endif
34 
35 #if defined(V8_TARGET_LITTLE_ENDIAN)
36 const uint32_t kLeastSignificantByteInInt32Offset = 0;
37 const uint32_t kLessSignificantWordInDoublewordOffset = 0;
38 #elif defined(V8_TARGET_BIG_ENDIAN)
39 const uint32_t kLeastSignificantByteInInt32Offset = 3;
40 const uint32_t kLessSignificantWordInDoublewordOffset = 4;
41 #else
42 #error Unknown endianness
43 #endif
44 
45 #ifndef __STDC_FORMAT_MACROS
46 #define __STDC_FORMAT_MACROS
47 #endif
48 #include <inttypes.h>
49 
50 // Defines constants and accessor classes to assemble, disassemble and
51 // simulate RISC-V instructions.
52 //
53 // See: The RISC-V Instruction Set Manual
54 //      Volume I: User-Level ISA
55 // Try https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf.
56 
57 namespace v8 {
58 namespace internal {
59 
60 constexpr size_t kMaxPCRelativeCodeRangeInMB = 4094;
61 
62 // -----------------------------------------------------------------------------
63 // Registers and FPURegisters.
64 
65 // Number of general purpose registers.
66 const int kNumRegisters = 32;
67 const int kInvalidRegister = -1;
68 
69 // Number of registers with pc.
70 const int kNumSimuRegisters = 33;
71 
72 // In the simulator, the PC register is simulated as the 34th register.
73 const int kPCRegister = 34;
74 
75 // Number coprocessor registers.
76 const int kNumFPURegisters = 32;
77 const int kInvalidFPURegister = -1;
78 
79 // Number vectotr registers
80 const int kNumVRegisters = 32;
81 const int kInvalidVRegister = -1;
82 // 'pref' instruction hints
83 const int32_t kPrefHintLoad = 0;
84 const int32_t kPrefHintStore = 1;
85 const int32_t kPrefHintLoadStreamed = 4;
86 const int32_t kPrefHintStoreStreamed = 5;
87 const int32_t kPrefHintLoadRetained = 6;
88 const int32_t kPrefHintStoreRetained = 7;
89 const int32_t kPrefHintWritebackInvalidate = 25;
90 const int32_t kPrefHintPrepareForStore = 30;
91 
92 // Actual value of root register is offset from the root array's start
93 // to take advantage of negative displacement values.
94 // TODO(sigurds): Choose best value.
95 constexpr int kRootRegisterBias = 256;
96 
97 // Helper functions for converting between register numbers and names.
98 class Registers {
99  public:
100   // Return the name of the register.
101   static const char* Name(int reg);
102 
103   // Lookup the register number for the name provided.
104   static int Number(const char* name);
105 
106   struct RegisterAlias {
107     int reg;
108     const char* name;
109   };
110 
111   static const int64_t kMaxValue = 0x7fffffffffffffffl;
112   static const int64_t kMinValue = 0x8000000000000000l;
113 
114  private:
115   static const char* names_[kNumSimuRegisters];
116   static const RegisterAlias aliases_[];
117 };
118 
119 // Helper functions for converting between register numbers and names.
120 class FPURegisters {
121  public:
122   // Return the name of the register.
123   static const char* Name(int reg);
124 
125   // Lookup the register number for the name provided.
126   static int Number(const char* name);
127 
128   struct RegisterAlias {
129     int creg;
130     const char* name;
131   };
132 
133  private:
134   static const char* names_[kNumFPURegisters];
135   static const RegisterAlias aliases_[];
136 };
137 
138 class VRegisters {
139  public:
140   // Return the name of the register.
141   static const char* Name(int reg);
142 
143   // Lookup the register number for the name provided.
144   static int Number(const char* name);
145 
146   struct RegisterAlias {
147     int creg;
148     const char* name;
149   };
150 
151  private:
152   static const char* names_[kNumVRegisters];
153   static const RegisterAlias aliases_[];
154 };
155 
156 // -----------------------------------------------------------------------------
157 // Instructions encoding constants.
158 
159 // On RISCV all instructions are 32 bits, except for RVC.
160 using Instr = int32_t;
161 using ShortInstr = int16_t;
162 
163 // Special Software Interrupt codes when used in the presence of the RISC-V
164 // simulator.
165 enum SoftwareInterruptCodes {
166   // Transition to C code.
167   call_rt_redirected = 0xfffff
168 };
169 
170 // On RISC-V Simulator breakpoints can have different codes:
171 // - Breaks between 0 and kMaxWatchpointCode are treated as simple watchpoints,
172 //   the simulator will run through them and print the registers.
173 // - Breaks between kMaxWatchpointCode and kMaxStopCode are treated as stop()
174 //   instructions (see Assembler::stop()).
175 // - Breaks larger than kMaxStopCode are simple breaks, dropping you into the
176 //   debugger.
177 const uint32_t kMaxWatchpointCode = 31;
178 const uint32_t kMaxStopCode = 127;
179 STATIC_ASSERT(kMaxWatchpointCode < kMaxStopCode);
180 
181 // ----- Fields offset and length.
182 // RISCV constants
183 const int kBaseOpcodeShift = 0;
184 const int kBaseOpcodeBits = 7;
185 const int kFunct7Shift = 25;
186 const int kFunct7Bits = 7;
187 const int kFunct5Shift = 27;
188 const int kFunct5Bits = 5;
189 const int kFunct3Shift = 12;
190 const int kFunct3Bits = 3;
191 const int kFunct2Shift = 25;
192 const int kFunct2Bits = 2;
193 const int kRs1Shift = 15;
194 const int kRs1Bits = 5;
195 const int kVs1Shift = 15;
196 const int kVs1Bits = 5;
197 const int kVs2Shift = 20;
198 const int kVs2Bits = 5;
199 const int kVdShift = 7;
200 const int kVdBits = 5;
201 const int kRs2Shift = 20;
202 const int kRs2Bits = 5;
203 const int kRs3Shift = 27;
204 const int kRs3Bits = 5;
205 const int kRdShift = 7;
206 const int kRdBits = 5;
207 const int kRlShift = 25;
208 const int kAqShift = 26;
209 const int kImm12Shift = 20;
210 const int kImm12Bits = 12;
211 const int kImm11Shift = 2;
212 const int kImm11Bits = 11;
213 const int kShamtShift = 20;
214 const int kShamtBits = 5;
215 const int kShamtWShift = 20;
216 const int kShamtWBits = 6;
217 const int kArithShiftShift = 30;
218 const int kImm20Shift = 12;
219 const int kImm20Bits = 20;
220 const int kCsrShift = 20;
221 const int kCsrBits = 12;
222 const int kMemOrderBits = 4;
223 const int kPredOrderShift = 24;
224 const int kSuccOrderShift = 20;
225 // for C extension
226 const int kRvcFunct4Shift = 12;
227 const int kRvcFunct4Bits = 4;
228 const int kRvcFunct3Shift = 13;
229 const int kRvcFunct3Bits = 3;
230 const int kRvcRs1Shift = 7;
231 const int kRvcRs1Bits = 5;
232 const int kRvcRs2Shift = 2;
233 const int kRvcRs2Bits = 5;
234 const int kRvcRdShift = 7;
235 const int kRvcRdBits = 5;
236 const int kRvcRs1sShift = 7;
237 const int kRvcRs1sBits = 3;
238 const int kRvcRs2sShift = 2;
239 const int kRvcRs2sBits = 3;
240 const int kRvcFunct2Shift = 5;
241 const int kRvcFunct2BShift = 10;
242 const int kRvcFunct2Bits = 2;
243 const int kRvcFunct6Shift = 10;
244 const int kRvcFunct6Bits = 6;
245 
246 // for RVV extension
247 constexpr int kRvvELEN = 64;
248 constexpr int kRvvVLEN = 128;
249 constexpr int kRvvSLEN = kRvvVLEN;
250 const int kRvvFunct6Shift = 26;
251 const int kRvvFunct6Bits = 6;
252 const uint32_t kRvvFunct6Mask =
253     (((1 << kRvvFunct6Bits) - 1) << kRvvFunct6Shift);
254 
255 const int kRvvVmBits = 1;
256 const int kRvvVmShift = 25;
257 const uint32_t kRvvVmMask = (((1 << kRvvVmBits) - 1) << kRvvVmShift);
258 
259 const int kRvvVs2Bits = 5;
260 const int kRvvVs2Shift = 20;
261 const uint32_t kRvvVs2Mask = (((1 << kRvvVs2Bits) - 1) << kRvvVs2Shift);
262 
263 const int kRvvVs1Bits = 5;
264 const int kRvvVs1Shift = 15;
265 const uint32_t kRvvVs1Mask = (((1 << kRvvVs1Bits) - 1) << kRvvVs1Shift);
266 
267 const int kRvvRs1Bits = kRvvVs1Bits;
268 const int kRvvRs1Shift = kRvvVs1Shift;
269 const uint32_t kRvvRs1Mask = (((1 << kRvvRs1Bits) - 1) << kRvvRs1Shift);
270 
271 const int kRvvRs2Bits = 5;
272 const int kRvvRs2Shift = 20;
273 const uint32_t kRvvRs2Mask = (((1 << kRvvRs2Bits) - 1) << kRvvRs2Shift);
274 
275 const int kRvvImm5Bits = kRvvVs1Bits;
276 const int kRvvImm5Shift = kRvvVs1Shift;
277 const uint32_t kRvvImm5Mask = (((1 << kRvvImm5Bits) - 1) << kRvvImm5Shift);
278 
279 const int kRvvVdBits = 5;
280 const int kRvvVdShift = 7;
281 const uint32_t kRvvVdMask = (((1 << kRvvVdBits) - 1) << kRvvVdShift);
282 
283 const int kRvvRdBits = kRvvVdBits;
284 const int kRvvRdShift = kRvvVdShift;
285 const uint32_t kRvvRdMask = (((1 << kRvvRdBits) - 1) << kRvvRdShift);
286 
287 const int kRvvZimmBits = 11;
288 const int kRvvZimmShift = 20;
289 const uint32_t kRvvZimmMask = (((1 << kRvvZimmBits) - 1) << kRvvZimmShift);
290 
291 const int kRvvUimmShift = kRvvRs1Shift;
292 const int kRvvUimmBits = kRvvRs1Bits;
293 const uint32_t kRvvUimmMask = (((1 << kRvvUimmBits) - 1) << kRvvUimmShift);
294 
295 const int kRvvWidthBits = 3;
296 const int kRvvWidthShift = 12;
297 const uint32_t kRvvWidthMask = (((1 << kRvvWidthBits) - 1) << kRvvWidthShift);
298 
299 const int kRvvMopBits = 2;
300 const int kRvvMopShift = 26;
301 const uint32_t kRvvMopMask = (((1 << kRvvMopBits) - 1) << kRvvMopShift);
302 
303 const int kRvvMewBits = 1;
304 const int kRvvMewShift = 28;
305 const uint32_t kRvvMewMask = (((1 << kRvvMewBits) - 1) << kRvvMewShift);
306 
307 const int kRvvNfBits = 3;
308 const int kRvvNfShift = 29;
309 const uint32_t kRvvNfMask = (((1 << kRvvNfBits) - 1) << kRvvNfShift);
310 
311 // RISCV Instruction bit masks
312 const uint32_t kBaseOpcodeMask = ((1 << kBaseOpcodeBits) - 1)
313                                  << kBaseOpcodeShift;
314 const uint32_t kFunct3Mask = ((1 << kFunct3Bits) - 1) << kFunct3Shift;
315 const uint32_t kFunct5Mask = ((1 << kFunct5Bits) - 1) << kFunct5Shift;
316 const uint32_t kFunct7Mask = ((1 << kFunct7Bits) - 1) << kFunct7Shift;
317 const uint32_t kFunct2Mask = 0b11 << kFunct7Shift;
318 const uint32_t kRTypeMask = kBaseOpcodeMask | kFunct3Mask | kFunct7Mask;
319 const uint32_t kRATypeMask = kBaseOpcodeMask | kFunct3Mask | kFunct5Mask;
320 const uint32_t kRFPTypeMask = kBaseOpcodeMask | kFunct7Mask;
321 const uint32_t kR4TypeMask = kBaseOpcodeMask | kFunct3Mask | kFunct2Mask;
322 const uint32_t kITypeMask = kBaseOpcodeMask | kFunct3Mask;
323 const uint32_t kSTypeMask = kBaseOpcodeMask | kFunct3Mask;
324 const uint32_t kBTypeMask = kBaseOpcodeMask | kFunct3Mask;
325 const uint32_t kUTypeMask = kBaseOpcodeMask;
326 const uint32_t kJTypeMask = kBaseOpcodeMask;
327 const uint32_t kVTypeMask = kRvvFunct6Mask | kFunct3Mask | kBaseOpcodeMask;
328 const uint32_t kRs1FieldMask = ((1 << kRs1Bits) - 1) << kRs1Shift;
329 const uint32_t kRs2FieldMask = ((1 << kRs2Bits) - 1) << kRs2Shift;
330 const uint32_t kRs3FieldMask = ((1 << kRs3Bits) - 1) << kRs3Shift;
331 const uint32_t kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift;
332 const uint32_t kBImm12Mask = kFunct7Mask | kRdFieldMask;
333 const uint32_t kImm20Mask = ((1 << kImm20Bits) - 1) << kImm20Shift;
334 const uint32_t kImm12Mask = ((1 << kImm12Bits) - 1) << kImm12Shift;
335 const uint32_t kImm11Mask = ((1 << kImm11Bits) - 1) << kImm11Shift;
336 const uint32_t kImm31_12Mask = ((1 << 20) - 1) << 12;
337 const uint32_t kImm19_0Mask = ((1 << 20) - 1);
338 const uint32_t kRvcOpcodeMask =
339     0b11 | (((1 << kRvcFunct3Bits) - 1) << kRvcFunct3Shift);
340 const uint32_t kRvcFunct3Mask =
341     (((1 << kRvcFunct3Bits) - 1) << kRvcFunct3Shift);
342 const uint32_t kRvcFunct4Mask =
343     (((1 << kRvcFunct4Bits) - 1) << kRvcFunct4Shift);
344 const uint32_t kRvcFunct6Mask =
345     (((1 << kRvcFunct6Bits) - 1) << kRvcFunct6Shift);
346 const uint32_t kRvcFunct2Mask =
347     (((1 << kRvcFunct2Bits) - 1) << kRvcFunct2Shift);
348 const uint32_t kRvcFunct2BMask =
349     (((1 << kRvcFunct2Bits) - 1) << kRvcFunct2BShift);
350 const uint32_t kCRTypeMask = kRvcOpcodeMask | kRvcFunct4Mask;
351 const uint32_t kCSTypeMask = kRvcOpcodeMask | kRvcFunct6Mask;
352 const uint32_t kCATypeMask = kRvcOpcodeMask | kRvcFunct6Mask | kRvcFunct2Mask;
353 const uint32_t kRvcBImm8Mask = (((1 << 5) - 1) << 2) | (((1 << 3) - 1) << 10);
354 
355 // RISCV CSR related bit mask and shift
356 const int kFcsrFlagsBits = 5;
357 const uint32_t kFcsrFlagsMask = (1 << kFcsrFlagsBits) - 1;
358 const int kFcsrFrmBits = 3;
359 const int kFcsrFrmShift = kFcsrFlagsBits;
360 const uint32_t kFcsrFrmMask = ((1 << kFcsrFrmBits) - 1) << kFcsrFrmShift;
361 const int kFcsrBits = kFcsrFlagsBits + kFcsrFrmBits;
362 const uint32_t kFcsrMask = kFcsrFlagsMask | kFcsrFrmMask;
363 
364 const int kNopByte = 0x00000013;
365 // Original MIPS constants
366 // TODO(RISCV): to be cleaned up
367 const int kImm16Shift = 0;
368 const int kImm16Bits = 16;
369 const uint32_t kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift;
370 // end of TODO(RISCV): to be cleaned up
371 
372 // ----- RISCV Base Opcodes
373 
374 enum BaseOpcode : uint32_t {};
375 
376 // ----- RISC-V Opcodes and Function Fields.
377 enum Opcode : uint32_t {
378   LOAD = 0b0000011,      // I form: LB LH LW LBU LHU
379   LOAD_FP = 0b0000111,   // I form: FLW FLD FLQ
380   MISC_MEM = 0b0001111,  // I special form: FENCE FENCE.I
381   OP_IMM = 0b0010011,    // I form: ADDI SLTI SLTIU XORI ORI ANDI SLLI SRLI SARI
382   // Note: SLLI/SRLI/SRAI I form first, then func3 001/101 => R type
383   AUIPC = 0b0010111,      // U form: AUIPC
384   OP_IMM_32 = 0b0011011,  // I form: ADDIW SLLIW SRLIW SRAIW
385   // Note:  SRLIW SRAIW I form first, then func3 101 special shift encoding
386   STORE = 0b0100011,     // S form: SB SH SW SD
387   STORE_FP = 0b0100111,  // S form: FSW FSD FSQ
388   AMO = 0b0101111,       // R form: All A instructions
389   OP = 0b0110011,      // R: ADD SUB SLL SLT SLTU XOR SRL SRA OR AND and 32M set
390   LUI = 0b0110111,     // U form: LUI
391   OP_32 = 0b0111011,   // R: ADDW SUBW SLLW SRLW SRAW MULW DIVW DIVUW REMW REMUW
392   MADD = 0b1000011,    // R4 type: FMADD.S FMADD.D FMADD.Q
393   MSUB = 0b1000111,    // R4 type: FMSUB.S FMSUB.D FMSUB.Q
394   NMSUB = 0b1001011,   // R4 type: FNMSUB.S FNMSUB.D FNMSUB.Q
395   NMADD = 0b1001111,   // R4 type: FNMADD.S FNMADD.D FNMADD.Q
396   OP_FP = 0b1010011,   // R type: Q ext
397   BRANCH = 0b1100011,  // B form: BEQ BNE, BLT, BGE, BLTU BGEU
398   JALR = 0b1100111,    // I form: JALR
399   JAL = 0b1101111,     // J form: JAL
400   SYSTEM = 0b1110011,  // I form: ECALL EBREAK Zicsr ext
401   // C extension
402   C0 = 0b00,
403   C1 = 0b01,
404   C2 = 0b10,
405   FUNCT2_0 = 0b00,
406   FUNCT2_1 = 0b01,
407   FUNCT2_2 = 0b10,
408   FUNCT2_3 = 0b11,
409 
410   // Note use RO (RiscV Opcode) prefix
411   // RV32I Base Instruction Set
412   RO_LUI = LUI,
413   RO_AUIPC = AUIPC,
414   RO_JAL = JAL,
415   RO_JALR = JALR | (0b000 << kFunct3Shift),
416   RO_BEQ = BRANCH | (0b000 << kFunct3Shift),
417   RO_BNE = BRANCH | (0b001 << kFunct3Shift),
418   RO_BLT = BRANCH | (0b100 << kFunct3Shift),
419   RO_BGE = BRANCH | (0b101 << kFunct3Shift),
420   RO_BLTU = BRANCH | (0b110 << kFunct3Shift),
421   RO_BGEU = BRANCH | (0b111 << kFunct3Shift),
422   RO_LB = LOAD | (0b000 << kFunct3Shift),
423   RO_LH = LOAD | (0b001 << kFunct3Shift),
424   RO_LW = LOAD | (0b010 << kFunct3Shift),
425   RO_LBU = LOAD | (0b100 << kFunct3Shift),
426   RO_LHU = LOAD | (0b101 << kFunct3Shift),
427   RO_SB = STORE | (0b000 << kFunct3Shift),
428   RO_SH = STORE | (0b001 << kFunct3Shift),
429   RO_SW = STORE | (0b010 << kFunct3Shift),
430   RO_ADDI = OP_IMM | (0b000 << kFunct3Shift),
431   RO_SLTI = OP_IMM | (0b010 << kFunct3Shift),
432   RO_SLTIU = OP_IMM | (0b011 << kFunct3Shift),
433   RO_XORI = OP_IMM | (0b100 << kFunct3Shift),
434   RO_ORI = OP_IMM | (0b110 << kFunct3Shift),
435   RO_ANDI = OP_IMM | (0b111 << kFunct3Shift),
436   RO_SLLI = OP_IMM | (0b001 << kFunct3Shift),
437   RO_SRLI = OP_IMM | (0b101 << kFunct3Shift),
438   // RO_SRAI = OP_IMM | (0b101 << kFunct3Shift), // Same as SRLI, use func7
439   RO_ADD = OP | (0b000 << kFunct3Shift) | (0b0000000 << kFunct7Shift),
440   RO_SUB = OP | (0b000 << kFunct3Shift) | (0b0100000 << kFunct7Shift),
441   RO_SLL = OP | (0b001 << kFunct3Shift) | (0b0000000 << kFunct7Shift),
442   RO_SLT = OP | (0b010 << kFunct3Shift) | (0b0000000 << kFunct7Shift),
443   RO_SLTU = OP | (0b011 << kFunct3Shift) | (0b0000000 << kFunct7Shift),
444   RO_XOR = OP | (0b100 << kFunct3Shift) | (0b0000000 << kFunct7Shift),
445   RO_SRL = OP | (0b101 << kFunct3Shift) | (0b0000000 << kFunct7Shift),
446   RO_SRA = OP | (0b101 << kFunct3Shift) | (0b0100000 << kFunct7Shift),
447   RO_OR = OP | (0b110 << kFunct3Shift) | (0b0000000 << kFunct7Shift),
448   RO_AND = OP | (0b111 << kFunct3Shift) | (0b0000000 << kFunct7Shift),
449   RO_FENCE = MISC_MEM | (0b000 << kFunct3Shift),
450   RO_ECALL = SYSTEM | (0b000 << kFunct3Shift),
451   // RO_EBREAK = SYSTEM | (0b000 << kFunct3Shift), // Same as ECALL, use imm12
452 
453   // RV64I Base Instruction Set (in addition to RV32I)
454   RO_LWU = LOAD | (0b110 << kFunct3Shift),
455   RO_LD = LOAD | (0b011 << kFunct3Shift),
456   RO_SD = STORE | (0b011 << kFunct3Shift),
457   RO_ADDIW = OP_IMM_32 | (0b000 << kFunct3Shift),
458   RO_SLLIW = OP_IMM_32 | (0b001 << kFunct3Shift),
459   RO_SRLIW = OP_IMM_32 | (0b101 << kFunct3Shift),
460   // RO_SRAIW = OP_IMM_32 | (0b101 << kFunct3Shift), // Same as SRLIW, use func7
461   RO_ADDW = OP_32 | (0b000 << kFunct3Shift) | (0b0000000 << kFunct7Shift),
462   RO_SUBW = OP_32 | (0b000 << kFunct3Shift) | (0b0100000 << kFunct7Shift),
463   RO_SLLW = OP_32 | (0b001 << kFunct3Shift) | (0b0000000 << kFunct7Shift),
464   RO_SRLW = OP_32 | (0b101 << kFunct3Shift) | (0b0000000 << kFunct7Shift),
465   RO_SRAW = OP_32 | (0b101 << kFunct3Shift) | (0b0100000 << kFunct7Shift),
466 
467   // RV32/RV64 Zifencei Standard Extension
468   RO_FENCE_I = MISC_MEM | (0b001 << kFunct3Shift),
469 
470   // RV32/RV64 Zicsr Standard Extension
471   RO_CSRRW = SYSTEM | (0b001 << kFunct3Shift),
472   RO_CSRRS = SYSTEM | (0b010 << kFunct3Shift),
473   RO_CSRRC = SYSTEM | (0b011 << kFunct3Shift),
474   RO_CSRRWI = SYSTEM | (0b101 << kFunct3Shift),
475   RO_CSRRSI = SYSTEM | (0b110 << kFunct3Shift),
476   RO_CSRRCI = SYSTEM | (0b111 << kFunct3Shift),
477 
478   // RV32M Standard Extension
479   RO_MUL = OP | (0b000 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
480   RO_MULH = OP | (0b001 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
481   RO_MULHSU = OP | (0b010 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
482   RO_MULHU = OP | (0b011 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
483   RO_DIV = OP | (0b100 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
484   RO_DIVU = OP | (0b101 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
485   RO_REM = OP | (0b110 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
486   RO_REMU = OP | (0b111 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
487 
488   // RV64M Standard Extension (in addition to RV32M)
489   RO_MULW = OP_32 | (0b000 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
490   RO_DIVW = OP_32 | (0b100 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
491   RO_DIVUW = OP_32 | (0b101 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
492   RO_REMW = OP_32 | (0b110 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
493   RO_REMUW = OP_32 | (0b111 << kFunct3Shift) | (0b0000001 << kFunct7Shift),
494 
495   // RV32A Standard Extension
496   RO_LR_W = AMO | (0b010 << kFunct3Shift) | (0b00010 << kFunct5Shift),
497   RO_SC_W = AMO | (0b010 << kFunct3Shift) | (0b00011 << kFunct5Shift),
498   RO_AMOSWAP_W = AMO | (0b010 << kFunct3Shift) | (0b00001 << kFunct5Shift),
499   RO_AMOADD_W = AMO | (0b010 << kFunct3Shift) | (0b00000 << kFunct5Shift),
500   RO_AMOXOR_W = AMO | (0b010 << kFunct3Shift) | (0b00100 << kFunct5Shift),
501   RO_AMOAND_W = AMO | (0b010 << kFunct3Shift) | (0b01100 << kFunct5Shift),
502   RO_AMOOR_W = AMO | (0b010 << kFunct3Shift) | (0b01000 << kFunct5Shift),
503   RO_AMOMIN_W = AMO | (0b010 << kFunct3Shift) | (0b10000 << kFunct5Shift),
504   RO_AMOMAX_W = AMO | (0b010 << kFunct3Shift) | (0b10100 << kFunct5Shift),
505   RO_AMOMINU_W = AMO | (0b010 << kFunct3Shift) | (0b11000 << kFunct5Shift),
506   RO_AMOMAXU_W = AMO | (0b010 << kFunct3Shift) | (0b11100 << kFunct5Shift),
507 
508   // RV64A Standard Extension (in addition to RV32A)
509   RO_LR_D = AMO | (0b011 << kFunct3Shift) | (0b00010 << kFunct5Shift),
510   RO_SC_D = AMO | (0b011 << kFunct3Shift) | (0b00011 << kFunct5Shift),
511   RO_AMOSWAP_D = AMO | (0b011 << kFunct3Shift) | (0b00001 << kFunct5Shift),
512   RO_AMOADD_D = AMO | (0b011 << kFunct3Shift) | (0b00000 << kFunct5Shift),
513   RO_AMOXOR_D = AMO | (0b011 << kFunct3Shift) | (0b00100 << kFunct5Shift),
514   RO_AMOAND_D = AMO | (0b011 << kFunct3Shift) | (0b01100 << kFunct5Shift),
515   RO_AMOOR_D = AMO | (0b011 << kFunct3Shift) | (0b01000 << kFunct5Shift),
516   RO_AMOMIN_D = AMO | (0b011 << kFunct3Shift) | (0b10000 << kFunct5Shift),
517   RO_AMOMAX_D = AMO | (0b011 << kFunct3Shift) | (0b10100 << kFunct5Shift),
518   RO_AMOMINU_D = AMO | (0b011 << kFunct3Shift) | (0b11000 << kFunct5Shift),
519   RO_AMOMAXU_D = AMO | (0b011 << kFunct3Shift) | (0b11100 << kFunct5Shift),
520 
521   // RV32F Standard Extension
522   RO_FLW = LOAD_FP | (0b010 << kFunct3Shift),
523   RO_FSW = STORE_FP | (0b010 << kFunct3Shift),
524   RO_FMADD_S = MADD | (0b00 << kFunct2Shift),
525   RO_FMSUB_S = MSUB | (0b00 << kFunct2Shift),
526   RO_FNMSUB_S = NMSUB | (0b00 << kFunct2Shift),
527   RO_FNMADD_S = NMADD | (0b00 << kFunct2Shift),
528   RO_FADD_S = OP_FP | (0b0000000 << kFunct7Shift),
529   RO_FSUB_S = OP_FP | (0b0000100 << kFunct7Shift),
530   RO_FMUL_S = OP_FP | (0b0001000 << kFunct7Shift),
531   RO_FDIV_S = OP_FP | (0b0001100 << kFunct7Shift),
532   RO_FSQRT_S = OP_FP | (0b0101100 << kFunct7Shift) | (0b00000 << kRs2Shift),
533   RO_FSGNJ_S = OP_FP | (0b000 << kFunct3Shift) | (0b0010000 << kFunct7Shift),
534   RO_FSGNJN_S = OP_FP | (0b001 << kFunct3Shift) | (0b0010000 << kFunct7Shift),
535   RO_FSQNJX_S = OP_FP | (0b010 << kFunct3Shift) | (0b0010000 << kFunct7Shift),
536   RO_FMIN_S = OP_FP | (0b000 << kFunct3Shift) | (0b0010100 << kFunct7Shift),
537   RO_FMAX_S = OP_FP | (0b001 << kFunct3Shift) | (0b0010100 << kFunct7Shift),
538   RO_FCVT_W_S = OP_FP | (0b1100000 << kFunct7Shift) | (0b00000 << kRs2Shift),
539   RO_FCVT_WU_S = OP_FP | (0b1100000 << kFunct7Shift) | (0b00001 << kRs2Shift),
540   RO_FMV = OP_FP | (0b1110000 << kFunct7Shift) | (0b000 << kFunct3Shift) |
541            (0b00000 << kRs2Shift),
542   RO_FEQ_S = OP_FP | (0b010 << kFunct3Shift) | (0b1010000 << kFunct7Shift),
543   RO_FLT_S = OP_FP | (0b001 << kFunct3Shift) | (0b1010000 << kFunct7Shift),
544   RO_FLE_S = OP_FP | (0b000 << kFunct3Shift) | (0b1010000 << kFunct7Shift),
545   RO_FCLASS_S = OP_FP | (0b001 << kFunct3Shift) | (0b1110000 << kFunct7Shift),
546   RO_FCVT_S_W = OP_FP | (0b1101000 << kFunct7Shift) | (0b00000 << kRs2Shift),
547   RO_FCVT_S_WU = OP_FP | (0b1101000 << kFunct7Shift) | (0b00001 << kRs2Shift),
548   RO_FMV_W_X = OP_FP | (0b000 << kFunct3Shift) | (0b1111000 << kFunct7Shift),
549 
550   // RV64F Standard Extension (in addition to RV32F)
551   RO_FCVT_L_S = OP_FP | (0b1100000 << kFunct7Shift) | (0b00010 << kRs2Shift),
552   RO_FCVT_LU_S = OP_FP | (0b1100000 << kFunct7Shift) | (0b00011 << kRs2Shift),
553   RO_FCVT_S_L = OP_FP | (0b1101000 << kFunct7Shift) | (0b00010 << kRs2Shift),
554   RO_FCVT_S_LU = OP_FP | (0b1101000 << kFunct7Shift) | (0b00011 << kRs2Shift),
555 
556   // RV32D Standard Extension
557   RO_FLD = LOAD_FP | (0b011 << kFunct3Shift),
558   RO_FSD = STORE_FP | (0b011 << kFunct3Shift),
559   RO_FMADD_D = MADD | (0b01 << kFunct2Shift),
560   RO_FMSUB_D = MSUB | (0b01 << kFunct2Shift),
561   RO_FNMSUB_D = NMSUB | (0b01 << kFunct2Shift),
562   RO_FNMADD_D = NMADD | (0b01 << kFunct2Shift),
563   RO_FADD_D = OP_FP | (0b0000001 << kFunct7Shift),
564   RO_FSUB_D = OP_FP | (0b0000101 << kFunct7Shift),
565   RO_FMUL_D = OP_FP | (0b0001001 << kFunct7Shift),
566   RO_FDIV_D = OP_FP | (0b0001101 << kFunct7Shift),
567   RO_FSQRT_D = OP_FP | (0b0101101 << kFunct7Shift) | (0b00000 << kRs2Shift),
568   RO_FSGNJ_D = OP_FP | (0b000 << kFunct3Shift) | (0b0010001 << kFunct7Shift),
569   RO_FSGNJN_D = OP_FP | (0b001 << kFunct3Shift) | (0b0010001 << kFunct7Shift),
570   RO_FSQNJX_D = OP_FP | (0b010 << kFunct3Shift) | (0b0010001 << kFunct7Shift),
571   RO_FMIN_D = OP_FP | (0b000 << kFunct3Shift) | (0b0010101 << kFunct7Shift),
572   RO_FMAX_D = OP_FP | (0b001 << kFunct3Shift) | (0b0010101 << kFunct7Shift),
573   RO_FCVT_S_D = OP_FP | (0b0100000 << kFunct7Shift) | (0b00001 << kRs2Shift),
574   RO_FCVT_D_S = OP_FP | (0b0100001 << kFunct7Shift) | (0b00000 << kRs2Shift),
575   RO_FEQ_D = OP_FP | (0b010 << kFunct3Shift) | (0b1010001 << kFunct7Shift),
576   RO_FLT_D = OP_FP | (0b001 << kFunct3Shift) | (0b1010001 << kFunct7Shift),
577   RO_FLE_D = OP_FP | (0b000 << kFunct3Shift) | (0b1010001 << kFunct7Shift),
578   RO_FCLASS_D = OP_FP | (0b001 << kFunct3Shift) | (0b1110001 << kFunct7Shift) |
579                 (0b00000 << kRs2Shift),
580   RO_FCVT_W_D = OP_FP | (0b1100001 << kFunct7Shift) | (0b00000 << kRs2Shift),
581   RO_FCVT_WU_D = OP_FP | (0b1100001 << kFunct7Shift) | (0b00001 << kRs2Shift),
582   RO_FCVT_D_W = OP_FP | (0b1101001 << kFunct7Shift) | (0b00000 << kRs2Shift),
583   RO_FCVT_D_WU = OP_FP | (0b1101001 << kFunct7Shift) | (0b00001 << kRs2Shift),
584 
585   // RV64D Standard Extension (in addition to RV32D)
586   RO_FCVT_L_D = OP_FP | (0b1100001 << kFunct7Shift) | (0b00010 << kRs2Shift),
587   RO_FCVT_LU_D = OP_FP | (0b1100001 << kFunct7Shift) | (0b00011 << kRs2Shift),
588   RO_FMV_X_D = OP_FP | (0b000 << kFunct3Shift) | (0b1110001 << kFunct7Shift) |
589                (0b00000 << kRs2Shift),
590   RO_FCVT_D_L = OP_FP | (0b1101001 << kFunct7Shift) | (0b00010 << kRs2Shift),
591   RO_FCVT_D_LU = OP_FP | (0b1101001 << kFunct7Shift) | (0b00011 << kRs2Shift),
592   RO_FMV_D_X = OP_FP | (0b000 << kFunct3Shift) | (0b1111001 << kFunct7Shift) |
593                (0b00000 << kRs2Shift),
594 
595   // RV64C Standard Extension
596   RO_C_ADDI4SPN = C0 | (0b000 << kRvcFunct3Shift),
597   RO_C_FLD = C0 | (0b001 << kRvcFunct3Shift),
598   RO_C_LW = C0 | (0b010 << kRvcFunct3Shift),
599   RO_C_LD = C0 | (0b011 << kRvcFunct3Shift),
600   RO_C_FSD = C0 | (0b101 << kRvcFunct3Shift),
601   RO_C_SW = C0 | (0b110 << kRvcFunct3Shift),
602   RO_C_SD = C0 | (0b111 << kRvcFunct3Shift),
603   RO_C_NOP_ADDI = C1 | (0b000 << kRvcFunct3Shift),
604   RO_C_ADDIW = C1 | (0b001 << kRvcFunct3Shift),
605   RO_C_LI = C1 | (0b010 << kRvcFunct3Shift),
606   RO_C_SUB = C1 | (0b100011 << kRvcFunct6Shift) | (FUNCT2_0 << kRvcFunct2Shift),
607   RO_C_XOR = C1 | (0b100011 << kRvcFunct6Shift) | (FUNCT2_1 << kRvcFunct2Shift),
608   RO_C_OR = C1 | (0b100011 << kRvcFunct6Shift) | (FUNCT2_2 << kRvcFunct2Shift),
609   RO_C_AND = C1 | (0b100011 << kRvcFunct6Shift) | (FUNCT2_3 << kRvcFunct2Shift),
610   RO_C_SUBW =
611       C1 | (0b100111 << kRvcFunct6Shift) | (FUNCT2_0 << kRvcFunct2Shift),
612   RO_C_ADDW =
613       C1 | (0b100111 << kRvcFunct6Shift) | (FUNCT2_1 << kRvcFunct2Shift),
614   RO_C_LUI_ADD = C1 | (0b011 << kRvcFunct3Shift),
615   RO_C_MISC_ALU = C1 | (0b100 << kRvcFunct3Shift),
616   RO_C_J = C1 | (0b101 << kRvcFunct3Shift),
617   RO_C_BEQZ = C1 | (0b110 << kRvcFunct3Shift),
618   RO_C_BNEZ = C1 | (0b111 << kRvcFunct3Shift),
619   RO_C_SLLI = C2 | (0b000 << kRvcFunct3Shift),
620   RO_C_FLDSP = C2 | (0b001 << kRvcFunct3Shift),
621   RO_C_LWSP = C2 | (0b010 << kRvcFunct3Shift),
622   RO_C_LDSP = C2 | (0b011 << kRvcFunct3Shift),
623   RO_C_JR_MV_ADD = C2 | (0b100 << kRvcFunct3Shift),
624   RO_C_JR = C2 | (0b1000 << kRvcFunct4Shift),
625   RO_C_MV = C2 | (0b1000 << kRvcFunct4Shift),
626   RO_C_EBREAK = C2 | (0b1001 << kRvcFunct4Shift),
627   RO_C_JALR = C2 | (0b1001 << kRvcFunct4Shift),
628   RO_C_ADD = C2 | (0b1001 << kRvcFunct4Shift),
629   RO_C_FSDSP = C2 | (0b101 << kRvcFunct3Shift),
630   RO_C_SWSP = C2 | (0b110 << kRvcFunct3Shift),
631   RO_C_SDSP = C2 | (0b111 << kRvcFunct3Shift),
632 
633   // RVV Extension
634   OP_V = 0b1010111,
635   OP_IVV = OP_V | (0b000 << kFunct3Shift),
636   OP_FVV = OP_V | (0b001 << kFunct3Shift),
637   OP_MVV = OP_V | (0b010 << kFunct3Shift),
638   OP_IVI = OP_V | (0b011 << kFunct3Shift),
639   OP_IVX = OP_V | (0b100 << kFunct3Shift),
640   OP_FVF = OP_V | (0b101 << kFunct3Shift),
641   OP_MVX = OP_V | (0b110 << kFunct3Shift),
642 
643   RO_V_VSETVLI = OP_V | (0b111 << kFunct3Shift) | 0b0 << 31,
644   RO_V_VSETIVLI = OP_V | (0b111 << kFunct3Shift) | 0b11 << 30,
645   RO_V_VSETVL = OP_V | (0b111 << kFunct3Shift) | 0b1 << 31,
646 
647   // RVV LOAD/STORE
648   RO_V_VL = LOAD_FP | (0b00 << kRvvMopShift) | (0b000 << kRvvNfShift),
649   RO_V_VLS = LOAD_FP | (0b10 << kRvvMopShift) | (0b000 << kRvvNfShift),
650   RO_V_VLX = LOAD_FP | (0b11 << kRvvMopShift) | (0b000 << kRvvNfShift),
651 
652   RO_V_VS = STORE_FP | (0b00 << kRvvMopShift) | (0b000 << kRvvNfShift),
653   RO_V_VSS = STORE_FP | (0b10 << kRvvMopShift) | (0b000 << kRvvNfShift),
654   RO_V_VSX = STORE_FP | (0b11 << kRvvMopShift) | (0b000 << kRvvNfShift),
655   RO_V_VSU = STORE_FP | (0b01 << kRvvMopShift) | (0b000 << kRvvNfShift),
656   // THE kFunct6Shift is mop
657   RO_V_VLSEG2 = LOAD_FP | (0b00 << kRvvMopShift) | (0b001 << kRvvNfShift),
658   RO_V_VLSEG3 = LOAD_FP | (0b00 << kRvvMopShift) | (0b010 << kRvvNfShift),
659   RO_V_VLSEG4 = LOAD_FP | (0b00 << kRvvMopShift) | (0b011 << kRvvNfShift),
660   RO_V_VLSEG5 = LOAD_FP | (0b00 << kRvvMopShift) | (0b100 << kRvvNfShift),
661   RO_V_VLSEG6 = LOAD_FP | (0b00 << kRvvMopShift) | (0b101 << kRvvNfShift),
662   RO_V_VLSEG7 = LOAD_FP | (0b00 << kRvvMopShift) | (0b110 << kRvvNfShift),
663   RO_V_VLSEG8 = LOAD_FP | (0b00 << kRvvMopShift) | (0b111 << kRvvNfShift),
664 
665   RO_V_VSSEG2 = STORE_FP | (0b00 << kRvvMopShift) | (0b001 << kRvvNfShift),
666   RO_V_VSSEG3 = STORE_FP | (0b00 << kRvvMopShift) | (0b010 << kRvvNfShift),
667   RO_V_VSSEG4 = STORE_FP | (0b00 << kRvvMopShift) | (0b011 << kRvvNfShift),
668   RO_V_VSSEG5 = STORE_FP | (0b00 << kRvvMopShift) | (0b100 << kRvvNfShift),
669   RO_V_VSSEG6 = STORE_FP | (0b00 << kRvvMopShift) | (0b101 << kRvvNfShift),
670   RO_V_VSSEG7 = STORE_FP | (0b00 << kRvvMopShift) | (0b110 << kRvvNfShift),
671   RO_V_VSSEG8 = STORE_FP | (0b00 << kRvvMopShift) | (0b111 << kRvvNfShift),
672 
673   RO_V_VLSSEG2 = LOAD_FP | (0b10 << kRvvMopShift) | (0b001 << kRvvNfShift),
674   RO_V_VLSSEG3 = LOAD_FP | (0b10 << kRvvMopShift) | (0b010 << kRvvNfShift),
675   RO_V_VLSSEG4 = LOAD_FP | (0b10 << kRvvMopShift) | (0b011 << kRvvNfShift),
676   RO_V_VLSSEG5 = LOAD_FP | (0b10 << kRvvMopShift) | (0b100 << kRvvNfShift),
677   RO_V_VLSSEG6 = LOAD_FP | (0b10 << kRvvMopShift) | (0b101 << kRvvNfShift),
678   RO_V_VLSSEG7 = LOAD_FP | (0b10 << kRvvMopShift) | (0b110 << kRvvNfShift),
679   RO_V_VLSSEG8 = LOAD_FP | (0b10 << kRvvMopShift) | (0b111 << kRvvNfShift),
680 
681   RO_V_VSSSEG2 = STORE_FP | (0b10 << kRvvMopShift) | (0b001 << kRvvNfShift),
682   RO_V_VSSSEG3 = STORE_FP | (0b10 << kRvvMopShift) | (0b010 << kRvvNfShift),
683   RO_V_VSSSEG4 = STORE_FP | (0b10 << kRvvMopShift) | (0b011 << kRvvNfShift),
684   RO_V_VSSSEG5 = STORE_FP | (0b10 << kRvvMopShift) | (0b100 << kRvvNfShift),
685   RO_V_VSSSEG6 = STORE_FP | (0b10 << kRvvMopShift) | (0b101 << kRvvNfShift),
686   RO_V_VSSSEG7 = STORE_FP | (0b10 << kRvvMopShift) | (0b110 << kRvvNfShift),
687   RO_V_VSSSEG8 = STORE_FP | (0b10 << kRvvMopShift) | (0b111 << kRvvNfShift),
688 
689   RO_V_VLXSEG2 = LOAD_FP | (0b11 << kRvvMopShift) | (0b001 << kRvvNfShift),
690   RO_V_VLXSEG3 = LOAD_FP | (0b11 << kRvvMopShift) | (0b010 << kRvvNfShift),
691   RO_V_VLXSEG4 = LOAD_FP | (0b11 << kRvvMopShift) | (0b011 << kRvvNfShift),
692   RO_V_VLXSEG5 = LOAD_FP | (0b11 << kRvvMopShift) | (0b100 << kRvvNfShift),
693   RO_V_VLXSEG6 = LOAD_FP | (0b11 << kRvvMopShift) | (0b101 << kRvvNfShift),
694   RO_V_VLXSEG7 = LOAD_FP | (0b11 << kRvvMopShift) | (0b110 << kRvvNfShift),
695   RO_V_VLXSEG8 = LOAD_FP | (0b11 << kRvvMopShift) | (0b111 << kRvvNfShift),
696 
697   RO_V_VSXSEG2 = STORE_FP | (0b11 << kRvvMopShift) | (0b001 << kRvvNfShift),
698   RO_V_VSXSEG3 = STORE_FP | (0b11 << kRvvMopShift) | (0b010 << kRvvNfShift),
699   RO_V_VSXSEG4 = STORE_FP | (0b11 << kRvvMopShift) | (0b011 << kRvvNfShift),
700   RO_V_VSXSEG5 = STORE_FP | (0b11 << kRvvMopShift) | (0b100 << kRvvNfShift),
701   RO_V_VSXSEG6 = STORE_FP | (0b11 << kRvvMopShift) | (0b101 << kRvvNfShift),
702   RO_V_VSXSEG7 = STORE_FP | (0b11 << kRvvMopShift) | (0b110 << kRvvNfShift),
703   RO_V_VSXSEG8 = STORE_FP | (0b11 << kRvvMopShift) | (0b111 << kRvvNfShift),
704 
705   // RVV Vector Arithmetic Instruction
706   VADD_FUNCT6 = 0b000000,
707   RO_V_VADD_VI = OP_IVI | (VADD_FUNCT6 << kRvvFunct6Shift),
708   RO_V_VADD_VV = OP_IVV | (VADD_FUNCT6 << kRvvFunct6Shift),
709   RO_V_VADD_VX = OP_IVX | (VADD_FUNCT6 << kRvvFunct6Shift),
710 
711   VSUB_FUNCT6 = 0b000010,
712   RO_V_VSUB_VX = OP_IVX | (VSUB_FUNCT6 << kRvvFunct6Shift),
713   RO_V_VSUB_VV = OP_IVV | (VSUB_FUNCT6 << kRvvFunct6Shift),
714 
715   VDIVU_FUNCT6 = 0b100000,
716   RO_V_VDIVU_VX = OP_MVX | (VDIVU_FUNCT6 << kRvvFunct6Shift),
717   RO_V_VDIVU_VV = OP_MVV | (VDIVU_FUNCT6 << kRvvFunct6Shift),
718 
719   VDIV_FUNCT6 = 0b100001,
720   RO_V_VDIV_VX = OP_MVX | (VDIV_FUNCT6 << kRvvFunct6Shift),
721   RO_V_VDIV_VV = OP_MVV | (VDIV_FUNCT6 << kRvvFunct6Shift),
722 
723   VREMU_FUNCT6 = 0b100010,
724   RO_V_VREMU_VX = OP_MVX | (VREMU_FUNCT6 << kRvvFunct6Shift),
725   RO_V_VREMU_VV = OP_MVV | (VREMU_FUNCT6 << kRvvFunct6Shift),
726 
727   VREM_FUNCT6 = 0b100011,
728   RO_V_VREM_VX = OP_MVX | (VREM_FUNCT6 << kRvvFunct6Shift),
729   RO_V_VREM_VV = OP_MVV | (VREM_FUNCT6 << kRvvFunct6Shift),
730 
731   VMULHU_FUNCT6 = 0b100100,
732   RO_V_VMULHU_VX = OP_MVX | (VMULHU_FUNCT6 << kRvvFunct6Shift),
733   RO_V_VMULHU_VV = OP_MVV | (VMULHU_FUNCT6 << kRvvFunct6Shift),
734 
735   VMUL_FUNCT6 = 0b100101,
736   RO_V_VMUL_VX = OP_MVX | (VMUL_FUNCT6 << kRvvFunct6Shift),
737   RO_V_VMUL_VV = OP_MVV | (VMUL_FUNCT6 << kRvvFunct6Shift),
738 
739   VWMUL_FUNCT6 = 0b111011,
740   RO_V_VWMUL_VX = OP_MVX | (VWMUL_FUNCT6 << kRvvFunct6Shift),
741   RO_V_VWMUL_VV = OP_MVV | (VWMUL_FUNCT6 << kRvvFunct6Shift),
742 
743   VWMULU_FUNCT6 = 0b111000,
744   RO_V_VWMULU_VX = OP_MVX | (VWMULU_FUNCT6 << kRvvFunct6Shift),
745   RO_V_VWMULU_VV = OP_MVV | (VWMULU_FUNCT6 << kRvvFunct6Shift),
746 
747   VMULHSU_FUNCT6 = 0b100110,
748   RO_V_VMULHSU_VX = OP_MVX | (VMULHSU_FUNCT6 << kRvvFunct6Shift),
749   RO_V_VMULHSU_VV = OP_MVV | (VMULHSU_FUNCT6 << kRvvFunct6Shift),
750 
751   VMULH_FUNCT6 = 0b100111,
752   RO_V_VMULH_VX = OP_MVX | (VMULH_FUNCT6 << kRvvFunct6Shift),
753   RO_V_VMULH_VV = OP_MVV | (VMULH_FUNCT6 << kRvvFunct6Shift),
754 
755   VWADD_FUNCT6 = 0b110001,
756   RO_V_VWADD_VV = OP_MVV | (VWADD_FUNCT6 << kRvvFunct6Shift),
757   RO_V_VWADD_VX = OP_MVX | (VWADD_FUNCT6 << kRvvFunct6Shift),
758 
759   VWADDU_FUNCT6 = 0b110000,
760   RO_V_VWADDU_VV = OP_MVV | (VWADDU_FUNCT6 << kRvvFunct6Shift),
761   RO_V_VWADDU_VX = OP_MVX | (VWADDU_FUNCT6 << kRvvFunct6Shift),
762 
763   VWADDUW_FUNCT6 = 0b110101,
764   RO_V_VWADDUW_VX = OP_MVX | (VWADDUW_FUNCT6 << kRvvFunct6Shift),
765   RO_V_VWADDUW_VV = OP_MVV | (VWADDUW_FUNCT6 << kRvvFunct6Shift),
766 
767   VCOMPRESS_FUNCT6 = 0b010111,
768   RO_V_VCOMPRESS_VV = OP_MVV | (VCOMPRESS_FUNCT6 << kRvvFunct6Shift),
769 
770   VSADDU_FUNCT6 = 0b100000,
771   RO_V_VSADDU_VI = OP_IVI | (VSADDU_FUNCT6 << kRvvFunct6Shift),
772   RO_V_VSADDU_VV = OP_IVV | (VSADDU_FUNCT6 << kRvvFunct6Shift),
773   RO_V_VSADDU_VX = OP_IVX | (VSADDU_FUNCT6 << kRvvFunct6Shift),
774 
775   VSADD_FUNCT6 = 0b100001,
776   RO_V_VSADD_VI = OP_IVI | (VSADD_FUNCT6 << kRvvFunct6Shift),
777   RO_V_VSADD_VV = OP_IVV | (VSADD_FUNCT6 << kRvvFunct6Shift),
778   RO_V_VSADD_VX = OP_IVX | (VSADD_FUNCT6 << kRvvFunct6Shift),
779 
780   VSSUB_FUNCT6 = 0b100011,
781   RO_V_VSSUB_VV = OP_IVV | (VSSUB_FUNCT6 << kRvvFunct6Shift),
782   RO_V_VSSUB_VX = OP_IVX | (VSSUB_FUNCT6 << kRvvFunct6Shift),
783 
784   VSSUBU_FUNCT6 = 0b100010,
785   RO_V_VSSUBU_VV = OP_IVV | (VSSUBU_FUNCT6 << kRvvFunct6Shift),
786   RO_V_VSSUBU_VX = OP_IVX | (VSSUBU_FUNCT6 << kRvvFunct6Shift),
787 
788   VRSUB_FUNCT6 = 0b000011,
789   RO_V_VRSUB_VX = OP_IVX | (VRSUB_FUNCT6 << kRvvFunct6Shift),
790   RO_V_VRSUB_VI = OP_IVI | (VRSUB_FUNCT6 << kRvvFunct6Shift),
791 
792   VMINU_FUNCT6 = 0b000100,
793   RO_V_VMINU_VX = OP_IVX | (VMINU_FUNCT6 << kRvvFunct6Shift),
794   RO_V_VMINU_VV = OP_IVV | (VMINU_FUNCT6 << kRvvFunct6Shift),
795 
796   VMIN_FUNCT6 = 0b000101,
797   RO_V_VMIN_VX = OP_IVX | (VMIN_FUNCT6 << kRvvFunct6Shift),
798   RO_V_VMIN_VV = OP_IVV | (VMIN_FUNCT6 << kRvvFunct6Shift),
799 
800   VMAXU_FUNCT6 = 0b000110,
801   RO_V_VMAXU_VX = OP_IVX | (VMAXU_FUNCT6 << kRvvFunct6Shift),
802   RO_V_VMAXU_VV = OP_IVV | (VMAXU_FUNCT6 << kRvvFunct6Shift),
803 
804   VMAX_FUNCT6 = 0b000111,
805   RO_V_VMAX_VX = OP_IVX | (VMAX_FUNCT6 << kRvvFunct6Shift),
806   RO_V_VMAX_VV = OP_IVV | (VMAX_FUNCT6 << kRvvFunct6Shift),
807 
808   VAND_FUNCT6 = 0b001001,
809   RO_V_VAND_VI = OP_IVI | (VAND_FUNCT6 << kRvvFunct6Shift),
810   RO_V_VAND_VV = OP_IVV | (VAND_FUNCT6 << kRvvFunct6Shift),
811   RO_V_VAND_VX = OP_IVX | (VAND_FUNCT6 << kRvvFunct6Shift),
812 
813   VOR_FUNCT6 = 0b001010,
814   RO_V_VOR_VI = OP_IVI | (VOR_FUNCT6 << kRvvFunct6Shift),
815   RO_V_VOR_VV = OP_IVV | (VOR_FUNCT6 << kRvvFunct6Shift),
816   RO_V_VOR_VX = OP_IVX | (VOR_FUNCT6 << kRvvFunct6Shift),
817 
818   VXOR_FUNCT6 = 0b001011,
819   RO_V_VXOR_VI = OP_IVI | (VXOR_FUNCT6 << kRvvFunct6Shift),
820   RO_V_VXOR_VV = OP_IVV | (VXOR_FUNCT6 << kRvvFunct6Shift),
821   RO_V_VXOR_VX = OP_IVX | (VXOR_FUNCT6 << kRvvFunct6Shift),
822 
823   VRGATHER_FUNCT6 = 0b001100,
824   RO_V_VRGATHER_VI = OP_IVI | (VRGATHER_FUNCT6 << kRvvFunct6Shift),
825   RO_V_VRGATHER_VV = OP_IVV | (VRGATHER_FUNCT6 << kRvvFunct6Shift),
826   RO_V_VRGATHER_VX = OP_IVX | (VRGATHER_FUNCT6 << kRvvFunct6Shift),
827 
828   VMV_FUNCT6 = 0b010111,
829   RO_V_VMV_VI = OP_IVI | (VMV_FUNCT6 << kRvvFunct6Shift),
830   RO_V_VMV_VV = OP_IVV | (VMV_FUNCT6 << kRvvFunct6Shift),
831   RO_V_VMV_VX = OP_IVX | (VMV_FUNCT6 << kRvvFunct6Shift),
832   RO_V_VFMV_VF = OP_FVF | (VMV_FUNCT6 << kRvvFunct6Shift),
833 
834   RO_V_VMERGE_VI = RO_V_VMV_VI,
835   RO_V_VMERGE_VV = RO_V_VMV_VV,
836   RO_V_VMERGE_VX = RO_V_VMV_VX,
837 
838   VMSEQ_FUNCT6 = 0b011000,
839   RO_V_VMSEQ_VI = OP_IVI | (VMSEQ_FUNCT6 << kRvvFunct6Shift),
840   RO_V_VMSEQ_VV = OP_IVV | (VMSEQ_FUNCT6 << kRvvFunct6Shift),
841   RO_V_VMSEQ_VX = OP_IVX | (VMSEQ_FUNCT6 << kRvvFunct6Shift),
842 
843   VMSNE_FUNCT6 = 0b011001,
844   RO_V_VMSNE_VI = OP_IVI | (VMSNE_FUNCT6 << kRvvFunct6Shift),
845   RO_V_VMSNE_VV = OP_IVV | (VMSNE_FUNCT6 << kRvvFunct6Shift),
846   RO_V_VMSNE_VX = OP_IVX | (VMSNE_FUNCT6 << kRvvFunct6Shift),
847 
848   VMSLTU_FUNCT6 = 0b011010,
849   RO_V_VMSLTU_VV = OP_IVV | (VMSLTU_FUNCT6 << kRvvFunct6Shift),
850   RO_V_VMSLTU_VX = OP_IVX | (VMSLTU_FUNCT6 << kRvvFunct6Shift),
851 
852   VMSLT_FUNCT6 = 0b011011,
853   RO_V_VMSLT_VV = OP_IVV | (VMSLT_FUNCT6 << kRvvFunct6Shift),
854   RO_V_VMSLT_VX = OP_IVX | (VMSLT_FUNCT6 << kRvvFunct6Shift),
855 
856   VMSLE_FUNCT6 = 0b011101,
857   RO_V_VMSLE_VI = OP_IVI | (VMSLE_FUNCT6 << kRvvFunct6Shift),
858   RO_V_VMSLE_VV = OP_IVV | (VMSLE_FUNCT6 << kRvvFunct6Shift),
859   RO_V_VMSLE_VX = OP_IVX | (VMSLE_FUNCT6 << kRvvFunct6Shift),
860 
861   VMSLEU_FUNCT6 = 0b011100,
862   RO_V_VMSLEU_VI = OP_IVI | (VMSLEU_FUNCT6 << kRvvFunct6Shift),
863   RO_V_VMSLEU_VV = OP_IVV | (VMSLEU_FUNCT6 << kRvvFunct6Shift),
864   RO_V_VMSLEU_VX = OP_IVX | (VMSLEU_FUNCT6 << kRvvFunct6Shift),
865 
866   VMSGTU_FUNCT6 = 0b011110,
867   RO_V_VMSGTU_VI = OP_IVI | (VMSGTU_FUNCT6 << kRvvFunct6Shift),
868   RO_V_VMSGTU_VX = OP_IVX | (VMSGTU_FUNCT6 << kRvvFunct6Shift),
869 
870   VMSGT_FUNCT6 = 0b011111,
871   RO_V_VMSGT_VI = OP_IVI | (VMSGT_FUNCT6 << kRvvFunct6Shift),
872   RO_V_VMSGT_VX = OP_IVX | (VMSGT_FUNCT6 << kRvvFunct6Shift),
873 
874   VSLIDEUP_FUNCT6 = 0b001110,
875   RO_V_VSLIDEUP_VI = OP_IVI | (VSLIDEUP_FUNCT6 << kRvvFunct6Shift),
876   RO_V_VSLIDEUP_VX = OP_IVX | (VSLIDEUP_FUNCT6 << kRvvFunct6Shift),
877 
878   VSLIDEDOWN_FUNCT6 = 0b001111,
879   RO_V_VSLIDEDOWN_VI = OP_IVI | (VSLIDEDOWN_FUNCT6 << kRvvFunct6Shift),
880   RO_V_VSLIDEDOWN_VX = OP_IVX | (VSLIDEDOWN_FUNCT6 << kRvvFunct6Shift),
881 
882   VSRL_FUNCT6 = 0b101000,
883   RO_V_VSRL_VI = OP_IVI | (VSRL_FUNCT6 << kRvvFunct6Shift),
884   RO_V_VSRL_VV = OP_IVV | (VSRL_FUNCT6 << kRvvFunct6Shift),
885   RO_V_VSRL_VX = OP_IVX | (VSRL_FUNCT6 << kRvvFunct6Shift),
886 
887   VSRA_FUNCT6 = 0b101001,
888   RO_V_VSRA_VI = OP_IVI | (VSRA_FUNCT6 << kRvvFunct6Shift),
889   RO_V_VSRA_VV = OP_IVV | (VSRA_FUNCT6 << kRvvFunct6Shift),
890   RO_V_VSRA_VX = OP_IVX | (VSRA_FUNCT6 << kRvvFunct6Shift),
891 
892   VSLL_FUNCT6 = 0b100101,
893   RO_V_VSLL_VI = OP_IVI | (VSLL_FUNCT6 << kRvvFunct6Shift),
894   RO_V_VSLL_VV = OP_IVV | (VSLL_FUNCT6 << kRvvFunct6Shift),
895   RO_V_VSLL_VX = OP_IVX | (VSLL_FUNCT6 << kRvvFunct6Shift),
896 
897   VSMUL_FUNCT6 = 0b100111,
898   RO_V_VSMUL_VV = OP_IVV | (VSMUL_FUNCT6 << kRvvFunct6Shift),
899   RO_V_VSMUL_VX = OP_IVX | (VSMUL_FUNCT6 << kRvvFunct6Shift),
900 
901   VADC_FUNCT6 = 0b010000,
902   RO_V_VADC_VI = OP_IVI | (VADC_FUNCT6 << kRvvFunct6Shift),
903   RO_V_VADC_VV = OP_IVV | (VADC_FUNCT6 << kRvvFunct6Shift),
904   RO_V_VADC_VX = OP_IVX | (VADC_FUNCT6 << kRvvFunct6Shift),
905 
906   VMADC_FUNCT6 = 0b010001,
907   RO_V_VMADC_VI = OP_IVI | (VMADC_FUNCT6 << kRvvFunct6Shift),
908   RO_V_VMADC_VV = OP_IVV | (VMADC_FUNCT6 << kRvvFunct6Shift),
909   RO_V_VMADC_VX = OP_IVX | (VMADC_FUNCT6 << kRvvFunct6Shift),
910 
911   VWXUNARY0_FUNCT6 = 0b010000,
912   VRXUNARY0_FUNCT6 = 0b010000,
913   VMUNARY0_FUNCT6 = 0b010100,
914 
915   RO_V_VWXUNARY0 = OP_MVV | (VWXUNARY0_FUNCT6 << kRvvFunct6Shift),
916   RO_V_VRXUNARY0 = OP_MVX | (VRXUNARY0_FUNCT6 << kRvvFunct6Shift),
917   RO_V_VMUNARY0 = OP_MVV | (VMUNARY0_FUNCT6 << kRvvFunct6Shift),
918 
919   VID_V = 0b10001,
920 
921   VXUNARY0_FUNCT6 = 0b010010,
922   RO_V_VXUNARY0 = OP_MVV | (VXUNARY0_FUNCT6 << kRvvFunct6Shift),
923 
924   VWFUNARY0_FUNCT6 = 0b010000,
925   RO_V_VFMV_FS = OP_FVV | (VWFUNARY0_FUNCT6 << kRvvFunct6Shift),
926 
927   VRFUNARY0_FUNCT6 = 0b010000,
928   RO_V_VFMV_SF = OP_FVF | (VRFUNARY0_FUNCT6 << kRvvFunct6Shift),
929 
930   VREDMAXU_FUNCT6 = 0b000110,
931   RO_V_VREDMAXU = OP_MVV | (VREDMAXU_FUNCT6 << kRvvFunct6Shift),
932   VREDMAX_FUNCT6 = 0b000111,
933   RO_V_VREDMAX = OP_MVV | (VREDMAX_FUNCT6 << kRvvFunct6Shift),
934 
935   VREDMINU_FUNCT6 = 0b000100,
936   RO_V_VREDMINU = OP_MVV | (VREDMINU_FUNCT6 << kRvvFunct6Shift),
937   VREDMIN_FUNCT6 = 0b000101,
938   RO_V_VREDMIN = OP_MVV | (VREDMIN_FUNCT6 << kRvvFunct6Shift),
939 
940   VFUNARY0_FUNCT6 = 0b010010,
941   RO_V_VFUNARY0 = OP_FVV | (VFUNARY0_FUNCT6 << kRvvFunct6Shift),
942   VFUNARY1_FUNCT6 = 0b010011,
943   RO_V_VFUNARY1 = OP_FVV | (VFUNARY1_FUNCT6 << kRvvFunct6Shift),
944 
945   VFCVT_XU_F_V = 0b00000,
946   VFCVT_X_F_V = 0b00001,
947   VFCVT_F_XU_V = 0b00010,
948   VFCVT_F_X_V = 0b00011,
949   VFWCVT_XU_F_V = 0b01000,
950   VFWCVT_X_F_V = 0b01001,
951   VFWCVT_F_XU_V = 0b01010,
952   VFWCVT_F_X_V = 0b01011,
953   VFWCVT_F_F_V = 0b01100,
954   VFNCVT_F_F_W = 0b10100,
955   VFNCVT_X_F_W = 0b10001,
956   VFNCVT_XU_F_W = 0b10000,
957 
958   VFCLASS_V = 0b10000,
959   VFSQRT_V = 0b00000,
960   VFRSQRT7_V = 0b00100,
961   VFREC7_V = 0b00101,
962 
963   VFADD_FUNCT6 = 0b000000,
964   RO_V_VFADD_VV = OP_FVV | (VFADD_FUNCT6 << kRvvFunct6Shift),
965   RO_V_VFADD_VF = OP_FVF | (VFADD_FUNCT6 << kRvvFunct6Shift),
966 
967   VFSUB_FUNCT6 = 0b000010,
968   RO_V_VFSUB_VV = OP_FVV | (VFSUB_FUNCT6 << kRvvFunct6Shift),
969   RO_V_VFSUB_VF = OP_FVF | (VFSUB_FUNCT6 << kRvvFunct6Shift),
970 
971   VFDIV_FUNCT6 = 0b100000,
972   RO_V_VFDIV_VV = OP_FVV | (VFDIV_FUNCT6 << kRvvFunct6Shift),
973   RO_V_VFDIV_VF = OP_FVF | (VFDIV_FUNCT6 << kRvvFunct6Shift),
974 
975   VFMUL_FUNCT6 = 0b100100,
976   RO_V_VFMUL_VV = OP_FVV | (VFMUL_FUNCT6 << kRvvFunct6Shift),
977   RO_V_VFMUL_VF = OP_FVF | (VFMUL_FUNCT6 << kRvvFunct6Shift),
978 
979   // Vector Widening Floating-Point Add/Subtract Instructions
980   VFWADD_FUNCT6 = 0b110000,
981   RO_V_VFWADD_VV = OP_FVV | (VFWADD_FUNCT6 << kRvvFunct6Shift),
982   RO_V_VFWADD_VF = OP_FVF | (VFWADD_FUNCT6 << kRvvFunct6Shift),
983 
984   VFWSUB_FUNCT6 = 0b110010,
985   RO_V_VFWSUB_VV = OP_FVV | (VFWSUB_FUNCT6 << kRvvFunct6Shift),
986   RO_V_VFWSUB_VF = OP_FVF | (VFWSUB_FUNCT6 << kRvvFunct6Shift),
987 
988   VFWADD_W_FUNCT6 = 0b110100,
989   RO_V_VFWADD_W_VV = OP_FVV | (VFWADD_W_FUNCT6 << kRvvFunct6Shift),
990   RO_V_VFWADD_W_VF = OP_FVF | (VFWADD_W_FUNCT6 << kRvvFunct6Shift),
991 
992   VFWSUB_W_FUNCT6 = 0b110110,
993   RO_V_VFWSUB_W_VV = OP_FVV | (VFWSUB_W_FUNCT6 << kRvvFunct6Shift),
994   RO_V_VFWSUB_W_VF = OP_FVF | (VFWSUB_W_FUNCT6 << kRvvFunct6Shift),
995 
996   // Vector Widening Floating-Point Reduction Instructions
997   VFWREDUSUM_FUNCT6 = 0b110001,
998   RO_V_VFWREDUSUM_VV = OP_FVV | (VFWREDUSUM_FUNCT6 << kRvvFunct6Shift),
999 
1000   VFWREDOSUM_FUNCT6 = 0b110011,
1001   RO_V_VFWREDOSUM_VV = OP_FVV | (VFWREDOSUM_FUNCT6 << kRvvFunct6Shift),
1002 
1003   // Vector Widening Floating-Point Multiply
1004   VFWMUL_FUNCT6 = 0b111000,
1005   RO_V_VFWMUL_VV = OP_FVV | (VFWMUL_FUNCT6 << kRvvFunct6Shift),
1006   RO_V_VFWMUL_VF = OP_FVF | (VFWMUL_FUNCT6 << kRvvFunct6Shift),
1007 
1008   VMFEQ_FUNCT6 = 0b011000,
1009   RO_V_VMFEQ_VV = OP_FVV | (VMFEQ_FUNCT6 << kRvvFunct6Shift),
1010   RO_V_VMFEQ_VF = OP_FVF | (VMFEQ_FUNCT6 << kRvvFunct6Shift),
1011 
1012   VMFNE_FUNCT6 = 0b011100,
1013   RO_V_VMFNE_VV = OP_FVV | (VMFNE_FUNCT6 << kRvvFunct6Shift),
1014   RO_V_VMFNE_VF = OP_FVF | (VMFNE_FUNCT6 << kRvvFunct6Shift),
1015 
1016   VMFLT_FUNCT6 = 0b011011,
1017   RO_V_VMFLT_VV = OP_FVV | (VMFLT_FUNCT6 << kRvvFunct6Shift),
1018   RO_V_VMFLT_VF = OP_FVF | (VMFLT_FUNCT6 << kRvvFunct6Shift),
1019 
1020   VMFLE_FUNCT6 = 0b011001,
1021   RO_V_VMFLE_VV = OP_FVV | (VMFLE_FUNCT6 << kRvvFunct6Shift),
1022   RO_V_VMFLE_VF = OP_FVF | (VMFLE_FUNCT6 << kRvvFunct6Shift),
1023 
1024   VMFGE_FUNCT6 = 0b011111,
1025   RO_V_VMFGE_VF = OP_FVF | (VMFGE_FUNCT6 << kRvvFunct6Shift),
1026 
1027   VMFGT_FUNCT6 = 0b011101,
1028   RO_V_VMFGT_VF = OP_FVF | (VMFGT_FUNCT6 << kRvvFunct6Shift),
1029 
1030   VFMAX_FUNCT6 = 0b000110,
1031   RO_V_VFMAX_VV = OP_FVV | (VFMAX_FUNCT6 << kRvvFunct6Shift),
1032   RO_V_VFMAX_VF = OP_FVF | (VFMAX_FUNCT6 << kRvvFunct6Shift),
1033 
1034   VFREDMAX_FUNCT6 = 0b0001111,
1035   RO_V_VFREDMAX_VV = OP_FVV | (VFREDMAX_FUNCT6 << kRvvFunct6Shift),
1036 
1037   VFMIN_FUNCT6 = 0b000100,
1038   RO_V_VFMIN_VV = OP_FVV | (VFMIN_FUNCT6 << kRvvFunct6Shift),
1039   RO_V_VFMIN_VF = OP_FVF | (VFMIN_FUNCT6 << kRvvFunct6Shift),
1040 
1041   VFSGNJ_FUNCT6 = 0b001000,
1042   RO_V_VFSGNJ_VV = OP_FVV | (VFSGNJ_FUNCT6 << kRvvFunct6Shift),
1043   RO_V_VFSGNJ_VF = OP_FVF | (VFSGNJ_FUNCT6 << kRvvFunct6Shift),
1044 
1045   VFSGNJN_FUNCT6 = 0b001001,
1046   RO_V_VFSGNJN_VV = OP_FVV | (VFSGNJN_FUNCT6 << kRvvFunct6Shift),
1047   RO_V_VFSGNJN_VF = OP_FVF | (VFSGNJN_FUNCT6 << kRvvFunct6Shift),
1048 
1049   VFSGNJX_FUNCT6 = 0b001010,
1050   RO_V_VFSGNJX_VV = OP_FVV | (VFSGNJX_FUNCT6 << kRvvFunct6Shift),
1051   RO_V_VFSGNJX_VF = OP_FVF | (VFSGNJX_FUNCT6 << kRvvFunct6Shift),
1052 
1053   VFMADD_FUNCT6 = 0b101000,
1054   RO_V_VFMADD_VV = OP_FVV | (VFMADD_FUNCT6 << kRvvFunct6Shift),
1055   RO_V_VFMADD_VF = OP_FVF | (VFMADD_FUNCT6 << kRvvFunct6Shift),
1056 
1057   VFNMADD_FUNCT6 = 0b101001,
1058   RO_V_VFNMADD_VV = OP_FVV | (VFNMADD_FUNCT6 << kRvvFunct6Shift),
1059   RO_V_VFNMADD_VF = OP_FVF | (VFNMADD_FUNCT6 << kRvvFunct6Shift),
1060 
1061   VFMSUB_FUNCT6 = 0b101010,
1062   RO_V_VFMSUB_VV = OP_FVV | (VFMSUB_FUNCT6 << kRvvFunct6Shift),
1063   RO_V_VFMSUB_VF = OP_FVF | (VFMSUB_FUNCT6 << kRvvFunct6Shift),
1064 
1065   VFNMSUB_FUNCT6 = 0b101011,
1066   RO_V_VFNMSUB_VV = OP_FVV | (VFNMSUB_FUNCT6 << kRvvFunct6Shift),
1067   RO_V_VFNMSUB_VF = OP_FVF | (VFNMSUB_FUNCT6 << kRvvFunct6Shift),
1068 
1069   VFMACC_FUNCT6 = 0b101100,
1070   RO_V_VFMACC_VV = OP_FVV | (VFMACC_FUNCT6 << kRvvFunct6Shift),
1071   RO_V_VFMACC_VF = OP_FVF | (VFMACC_FUNCT6 << kRvvFunct6Shift),
1072 
1073   VFNMACC_FUNCT6 = 0b101101,
1074   RO_V_VFNMACC_VV = OP_FVV | (VFNMACC_FUNCT6 << kRvvFunct6Shift),
1075   RO_V_VFNMACC_VF = OP_FVF | (VFNMACC_FUNCT6 << kRvvFunct6Shift),
1076 
1077   VFMSAC_FUNCT6 = 0b101110,
1078   RO_V_VFMSAC_VV = OP_FVV | (VFMSAC_FUNCT6 << kRvvFunct6Shift),
1079   RO_V_VFMSAC_VF = OP_FVF | (VFMSAC_FUNCT6 << kRvvFunct6Shift),
1080 
1081   VFNMSAC_FUNCT6 = 0b101111,
1082   RO_V_VFNMSAC_VV = OP_FVV | (VFNMSAC_FUNCT6 << kRvvFunct6Shift),
1083   RO_V_VFNMSAC_VF = OP_FVF | (VFNMSAC_FUNCT6 << kRvvFunct6Shift),
1084 
1085   // Vector Widening Floating-Point Fused Multiply-Add Instructions
1086   VFWMACC_FUNCT6 = 0b111100,
1087   RO_V_VFWMACC_VV = OP_FVV | (VFWMACC_FUNCT6 << kRvvFunct6Shift),
1088   RO_V_VFWMACC_VF = OP_FVF | (VFWMACC_FUNCT6 << kRvvFunct6Shift),
1089 
1090   VFWNMACC_FUNCT6 = 0b111101,
1091   RO_V_VFWNMACC_VV = OP_FVV | (VFWNMACC_FUNCT6 << kRvvFunct6Shift),
1092   RO_V_VFWNMACC_VF = OP_FVF | (VFWNMACC_FUNCT6 << kRvvFunct6Shift),
1093 
1094   VFWMSAC_FUNCT6 = 0b111110,
1095   RO_V_VFWMSAC_VV = OP_FVV | (VFWMSAC_FUNCT6 << kRvvFunct6Shift),
1096   RO_V_VFWMSAC_VF = OP_FVF | (VFWMSAC_FUNCT6 << kRvvFunct6Shift),
1097 
1098   VFWNMSAC_FUNCT6 = 0b111111,
1099   RO_V_VFWNMSAC_VV = OP_FVV | (VFWNMSAC_FUNCT6 << kRvvFunct6Shift),
1100   RO_V_VFWNMSAC_VF = OP_FVF | (VFWNMSAC_FUNCT6 << kRvvFunct6Shift),
1101 
1102   VNCLIP_FUNCT6 = 0b101111,
1103   RO_V_VNCLIP_WV = OP_IVV | (VNCLIP_FUNCT6 << kRvvFunct6Shift),
1104   RO_V_VNCLIP_WX = OP_IVX | (VNCLIP_FUNCT6 << kRvvFunct6Shift),
1105   RO_V_VNCLIP_WI = OP_IVI | (VNCLIP_FUNCT6 << kRvvFunct6Shift),
1106 
1107   VNCLIPU_FUNCT6 = 0b101110,
1108   RO_V_VNCLIPU_WV = OP_IVV | (VNCLIPU_FUNCT6 << kRvvFunct6Shift),
1109   RO_V_VNCLIPU_WX = OP_IVX | (VNCLIPU_FUNCT6 << kRvvFunct6Shift),
1110   RO_V_VNCLIPU_WI = OP_IVI | (VNCLIPU_FUNCT6 << kRvvFunct6Shift),
1111 };
1112 
1113 // ----- Emulated conditions.
1114 // On RISC-V we use this enum to abstract from conditional branch instructions.
1115 // The 'U' prefix is used to specify unsigned comparisons.
1116 // Opposite conditions must be paired as odd/even numbers
1117 // because 'NegateCondition' function flips LSB to negate condition.
1118 enum Condition {  // Any value < 0 is considered no_condition.
1119   kNoCondition = -1,
1120   overflow = 0,
1121   no_overflow = 1,
1122   Uless = 2,
1123   Ugreater_equal = 3,
1124   Uless_equal = 4,
1125   Ugreater = 5,
1126   equal = 6,
1127   not_equal = 7,  // Unordered or Not Equal.
1128   less = 8,
1129   greater_equal = 9,
1130   less_equal = 10,
1131   greater = 11,
1132   cc_always = 12,
1133 
1134   // Aliases.
1135   eq = equal,
1136   ne = not_equal,
1137   ge = greater_equal,
1138   lt = less,
1139   gt = greater,
1140   le = less_equal,
1141   al = cc_always,
1142   ult = Uless,
1143   uge = Ugreater_equal,
1144   ule = Uless_equal,
1145   ugt = Ugreater,
1146 };
1147 
1148 // Returns the equivalent of !cc.
1149 // Negation of the default kNoCondition (-1) results in a non-default
1150 // no_condition value (-2). As long as tests for no_condition check
1151 // for condition < 0, this will work as expected.
NegateCondition(Condition cc)1152 inline Condition NegateCondition(Condition cc) {
1153   DCHECK(cc != cc_always);
1154   return static_cast<Condition>(cc ^ 1);
1155 }
1156 
NegateFpuCondition(Condition cc)1157 inline Condition NegateFpuCondition(Condition cc) {
1158   DCHECK(cc != cc_always);
1159   switch (cc) {
1160     case ult:
1161       return ge;
1162     case ugt:
1163       return le;
1164     case uge:
1165       return lt;
1166     case ule:
1167       return gt;
1168     case lt:
1169       return uge;
1170     case gt:
1171       return ule;
1172     case ge:
1173       return ult;
1174     case le:
1175       return ugt;
1176     case eq:
1177       return ne;
1178     case ne:
1179       return eq;
1180     default:
1181       return cc;
1182   }
1183 }
1184 
1185 // ----- Coprocessor conditions.
1186 enum FPUCondition {
1187   kNoFPUCondition = -1,
1188   EQ = 0x02,  // Ordered and Equal
1189   NE = 0x03,  // Unordered or Not Equal
1190   LT = 0x04,  // Ordered and Less Than
1191   GE = 0x05,  // Ordered and Greater Than or Equal
1192   LE = 0x06,  // Ordered and Less Than or Equal
1193   GT = 0x07,  // Ordered and Greater Than
1194 };
1195 
1196 enum CheckForInexactConversion {
1197   kCheckForInexactConversion,
1198   kDontCheckForInexactConversion
1199 };
1200 
1201 enum class MaxMinKind : int { kMin = 0, kMax = 1 };
1202 
1203 // ----------------------------------------------------------------------------
1204 // RISCV flags
1205 
1206 enum ControlStatusReg {
1207   csr_fflags = 0x001,   // Floating-Point Accrued Exceptions (RW)
1208   csr_frm = 0x002,      // Floating-Point Dynamic Rounding Mode (RW)
1209   csr_fcsr = 0x003,     // Floating-Point Control and Status Register (RW)
1210   csr_cycle = 0xc00,    // Cycle counter for RDCYCLE instruction (RO)
1211   csr_time = 0xc01,     // Timer for RDTIME instruction (RO)
1212   csr_instret = 0xc02,  // Insns-retired counter for RDINSTRET instruction (RO)
1213   csr_cycleh = 0xc80,   // Upper 32 bits of cycle, RV32I only (RO)
1214   csr_timeh = 0xc81,    // Upper 32 bits of time, RV32I only (RO)
1215   csr_instreth = 0xc82  // Upper 32 bits of instret, RV32I only (RO)
1216 };
1217 
1218 enum FFlagsMask {
1219   kInvalidOperation = 0b10000,  // NV: Invalid
1220   kDivideByZero = 0b1000,       // DZ:  Divide by Zero
1221   kOverflow = 0b100,            // OF: Overflow
1222   kUnderflow = 0b10,            // UF: Underflow
1223   kInexact = 0b1                // NX:  Inexact
1224 };
1225 
1226 enum RoundingMode {
1227   RNE = 0b000,  // Round to Nearest, ties to Even
1228   RTZ = 0b001,  // Round towards Zero
1229   RDN = 0b010,  // Round Down (towards -infinity)
1230   RUP = 0b011,  // Round Up (towards +infinity)
1231   RMM = 0b100,  // Round to Nearest, tiest to Max Magnitude
1232   DYN = 0b111   // In instruction's rm field, selects dynamic rounding mode;
1233                 // In Rounding Mode register, Invalid
1234 };
1235 
1236 enum MemoryOdering {
1237   PSI = 0b1000,  // PI or SI
1238   PSO = 0b0100,  // PO or SO
1239   PSR = 0b0010,  // PR or SR
1240   PSW = 0b0001,  // PW or SW
1241   PSIORW = PSI | PSO | PSR | PSW
1242 };
1243 
1244 const int kFloat32ExponentBias = 127;
1245 const int kFloat32MantissaBits = 23;
1246 const int kFloat32ExponentBits = 8;
1247 const int kFloat64ExponentBias = 1023;
1248 const int kFloat64MantissaBits = 52;
1249 const int kFloat64ExponentBits = 11;
1250 
1251 enum FClassFlag {
1252   kNegativeInfinity = 1,
1253   kNegativeNormalNumber = 1 << 1,
1254   kNegativeSubnormalNumber = 1 << 2,
1255   kNegativeZero = 1 << 3,
1256   kPositiveZero = 1 << 4,
1257   kPositiveSubnormalNumber = 1 << 5,
1258   kPositiveNormalNumber = 1 << 6,
1259   kPositiveInfinity = 1 << 7,
1260   kSignalingNaN = 1 << 8,
1261   kQuietNaN = 1 << 9
1262 };
1263 
1264 #define RVV_SEW(V) \
1265   V(E8)            \
1266   V(E16)           \
1267   V(E32)           \
1268   V(E64)
1269 
1270 #define DEFINE_FLAG(name) name,
1271 enum VSew {
1272   RVV_SEW(DEFINE_FLAG)
1273 #undef DEFINE_FLAG
1274 };
1275 
1276 #define RVV_LMUL(V) \
1277   V(m1)             \
1278   V(m2)             \
1279   V(m4)             \
1280   V(m8)             \
1281   V(RESERVERD)      \
1282   V(mf8)            \
1283   V(mf4)            \
1284   V(mf2)
1285 
1286 enum Vlmul {
1287 #define DEFINE_FLAG(name) name,
1288   RVV_LMUL(DEFINE_FLAG)
1289 #undef DEFINE_FLAG
1290 };
1291 
1292 enum TailAgnosticType {
1293   ta = 0x1,  // Tail agnostic
1294   tu = 0x0,  // Tail undisturbed
1295 };
1296 
1297 enum MaskAgnosticType {
1298   ma = 0x1,  // Mask agnostic
1299   mu = 0x0,  // Mask undisturbed
1300 };
1301 enum MaskType {
1302   Mask = 0x0,  // use the mask
1303   NoMask = 0x1,
1304 };
1305 
1306 // -----------------------------------------------------------------------------
1307 // Hints.
1308 
1309 // Branch hints are not used on RISC-V.  They are defined so that they can
1310 // appear in shared function signatures, but will be ignored in RISC-V
1311 // implementations.
1312 enum Hint { no_hint = 0 };
1313 
NegateHint(Hint hint)1314 inline Hint NegateHint(Hint hint) { return no_hint; }
1315 
1316 // -----------------------------------------------------------------------------
1317 // Specific instructions, constants, and masks.
1318 // These constants are declared in assembler-riscv64.cc, as they use named
1319 // registers and other constants.
1320 
1321 // An Illegal instruction
1322 const Instr kIllegalInstr = 0;  // All other bits are 0s (i.e., ecall)
1323 // An ECALL instruction, used for redirected real time call
1324 const Instr rtCallRedirInstr = SYSTEM;  // All other bits are 0s (i.e., ecall)
1325 // An EBreak instruction, used for debugging and semi-hosting
1326 const Instr kBreakInstr = SYSTEM | 1 << kImm12Shift;  // ebreak
1327 
1328 constexpr uint8_t kInstrSize = 4;
1329 constexpr uint8_t kShortInstrSize = 2;
1330 constexpr uint8_t kInstrSizeLog2 = 2;
1331 
1332 class InstructionBase {
1333  public:
1334   enum {
1335     // On RISC-V, PC cannot actually be directly accessed. We behave as if PC
1336     // was always the value of the current instruction being executed.
1337     kPCReadOffset = 0
1338   };
1339 
1340   // Instruction type.
1341   enum Type {
1342     kRType,
1343     kR4Type,  // Special R4 for Q extension
1344     kIType,
1345     kSType,
1346     kBType,
1347     kUType,
1348     kJType,
1349     // C extension
1350     kCRType,
1351     kCIType,
1352     kCSSType,
1353     kCIWType,
1354     kCLType,
1355     kCSType,
1356     kCAType,
1357     kCBType,
1358     kCJType,
1359     // V extension
1360     kVType,
1361     kVLType,
1362     kVSType,
1363     kVAMOType,
1364     kVIVVType,
1365     kVFVVType,
1366     kVMVVType,
1367     kVIVIType,
1368     kVIVXType,
1369     kVFVFType,
1370     kVMVXType,
1371     kVSETType,
1372     kUnsupported = -1
1373   };
1374 
IsIllegalInstruction()1375   inline bool IsIllegalInstruction() const {
1376     uint16_t FirstHalfWord = *reinterpret_cast<const uint16_t*>(this);
1377     return FirstHalfWord == 0;
1378   }
1379 
IsShortInstruction()1380   inline bool IsShortInstruction() const {
1381     uint8_t FirstByte = *reinterpret_cast<const uint8_t*>(this);
1382     return (FirstByte & 0x03) <= C2;
1383   }
1384 
InstructionSize()1385   inline uint8_t InstructionSize() const {
1386     return (FLAG_riscv_c_extension && this->IsShortInstruction())
1387                ? kShortInstrSize
1388                : kInstrSize;
1389   }
1390 
1391   // Get the raw instruction bits.
InstructionBits()1392   inline Instr InstructionBits() const {
1393     if (FLAG_riscv_c_extension && this->IsShortInstruction()) {
1394       return 0x0000FFFF & (*reinterpret_cast<const ShortInstr*>(this));
1395     }
1396     return *reinterpret_cast<const Instr*>(this);
1397   }
1398 
1399   // Set the raw instruction bits to value.
SetInstructionBits(Instr value)1400   inline void SetInstructionBits(Instr value) {
1401     *reinterpret_cast<Instr*>(this) = value;
1402   }
1403 
1404   // Read one particular bit out of the instruction bits.
Bit(int nr)1405   inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; }
1406 
1407   // Read a bit field out of the instruction bits.
Bits(int hi,int lo)1408   inline int Bits(int hi, int lo) const {
1409     return (InstructionBits() >> lo) & ((2U << (hi - lo)) - 1);
1410   }
1411 
1412   // Accessors for the different named fields used in the RISC-V encoding.
BaseOpcodeValue()1413   inline Opcode BaseOpcodeValue() const {
1414     return static_cast<Opcode>(
1415         Bits(kBaseOpcodeShift + kBaseOpcodeBits - 1, kBaseOpcodeShift));
1416   }
1417 
1418   // Return the fields at their original place in the instruction encoding.
BaseOpcodeFieldRaw()1419   inline Opcode BaseOpcodeFieldRaw() const {
1420     return static_cast<Opcode>(InstructionBits() & kBaseOpcodeMask);
1421   }
1422 
1423   // Safe to call within R-type instructions
Funct7FieldRaw()1424   inline int Funct7FieldRaw() const { return InstructionBits() & kFunct7Mask; }
1425 
1426   // Safe to call within R-, I-, S-, or B-type instructions
Funct3FieldRaw()1427   inline int Funct3FieldRaw() const { return InstructionBits() & kFunct3Mask; }
1428 
1429   // Safe to call within R-, I-, S-, or B-type instructions
Rs1FieldRawNoAssert()1430   inline int Rs1FieldRawNoAssert() const {
1431     return InstructionBits() & kRs1FieldMask;
1432   }
1433 
1434   // Safe to call within R-, S-, or B-type instructions
Rs2FieldRawNoAssert()1435   inline int Rs2FieldRawNoAssert() const {
1436     return InstructionBits() & kRs2FieldMask;
1437   }
1438 
1439   // Safe to call within R4-type instructions
Rs3FieldRawNoAssert()1440   inline int Rs3FieldRawNoAssert() const {
1441     return InstructionBits() & kRs3FieldMask;
1442   }
1443 
ITypeBits()1444   inline int32_t ITypeBits() const { return InstructionBits() & kITypeMask; }
1445 
InstructionOpcodeType()1446   inline int32_t InstructionOpcodeType() const {
1447     if (IsShortInstruction()) {
1448       return InstructionBits() & kRvcOpcodeMask;
1449     } else {
1450       return InstructionBits() & kBaseOpcodeMask;
1451     }
1452   }
1453 
1454   // Get the encoding type of the instruction.
1455   Type InstructionType() const;
1456 
1457  protected:
InstructionBase()1458   InstructionBase() {}
1459 };
1460 
1461 template <class T>
1462 class InstructionGetters : public T {
1463  public:
BaseOpcode()1464   inline int BaseOpcode() const {
1465     return this->InstructionBits() & kBaseOpcodeMask;
1466   }
1467 
RvcOpcode()1468   inline int RvcOpcode() const {
1469     DCHECK(this->IsShortInstruction());
1470     return this->InstructionBits() & kRvcOpcodeMask;
1471   }
1472 
Rs1Value()1473   inline int Rs1Value() const {
1474     DCHECK(this->InstructionType() == InstructionBase::kRType ||
1475            this->InstructionType() == InstructionBase::kR4Type ||
1476            this->InstructionType() == InstructionBase::kIType ||
1477            this->InstructionType() == InstructionBase::kSType ||
1478            this->InstructionType() == InstructionBase::kBType ||
1479            this->InstructionType() == InstructionBase::kIType ||
1480            this->InstructionType() == InstructionBase::kVType);
1481     return this->Bits(kRs1Shift + kRs1Bits - 1, kRs1Shift);
1482   }
1483 
Rs2Value()1484   inline int Rs2Value() const {
1485     DCHECK(this->InstructionType() == InstructionBase::kRType ||
1486            this->InstructionType() == InstructionBase::kR4Type ||
1487            this->InstructionType() == InstructionBase::kSType ||
1488            this->InstructionType() == InstructionBase::kBType ||
1489            this->InstructionType() == InstructionBase::kIType ||
1490            this->InstructionType() == InstructionBase::kVType);
1491     return this->Bits(kRs2Shift + kRs2Bits - 1, kRs2Shift);
1492   }
1493 
Rs3Value()1494   inline int Rs3Value() const {
1495     DCHECK(this->InstructionType() == InstructionBase::kR4Type);
1496     return this->Bits(kRs3Shift + kRs3Bits - 1, kRs3Shift);
1497   }
1498 
Vs1Value()1499   inline int Vs1Value() const {
1500     DCHECK(this->InstructionType() == InstructionBase::kVType ||
1501            this->InstructionType() == InstructionBase::kIType ||
1502            this->InstructionType() == InstructionBase::kSType);
1503     return this->Bits(kVs1Shift + kVs1Bits - 1, kVs1Shift);
1504   }
1505 
Vs2Value()1506   inline int Vs2Value() const {
1507     DCHECK(this->InstructionType() == InstructionBase::kVType ||
1508            this->InstructionType() == InstructionBase::kIType ||
1509            this->InstructionType() == InstructionBase::kSType);
1510     return this->Bits(kVs2Shift + kVs2Bits - 1, kVs2Shift);
1511   }
1512 
VdValue()1513   inline int VdValue() const {
1514     DCHECK(this->InstructionType() == InstructionBase::kVType ||
1515            this->InstructionType() == InstructionBase::kIType ||
1516            this->InstructionType() == InstructionBase::kSType);
1517     return this->Bits(kVdShift + kVdBits - 1, kVdShift);
1518   }
1519 
RdValue()1520   inline int RdValue() const {
1521     DCHECK(this->InstructionType() == InstructionBase::kRType ||
1522            this->InstructionType() == InstructionBase::kR4Type ||
1523            this->InstructionType() == InstructionBase::kIType ||
1524            this->InstructionType() == InstructionBase::kSType ||
1525            this->InstructionType() == InstructionBase::kUType ||
1526            this->InstructionType() == InstructionBase::kJType ||
1527            this->InstructionType() == InstructionBase::kVType);
1528     return this->Bits(kRdShift + kRdBits - 1, kRdShift);
1529   }
1530 
RvcRdValue()1531   inline int RvcRdValue() const {
1532     DCHECK(this->IsShortInstruction());
1533     return this->Bits(kRvcRdShift + kRvcRdBits - 1, kRvcRdShift);
1534   }
1535 
RvcRs1Value()1536   inline int RvcRs1Value() const { return this->RvcRdValue(); }
1537 
RvcRs2Value()1538   inline int RvcRs2Value() const {
1539     DCHECK(this->IsShortInstruction());
1540     return this->Bits(kRvcRs2Shift + kRvcRs2Bits - 1, kRvcRs2Shift);
1541   }
1542 
RvcRs1sValue()1543   inline int RvcRs1sValue() const {
1544     DCHECK(this->IsShortInstruction());
1545     return 0b1000 + this->Bits(kRvcRs1sShift + kRvcRs1sBits - 1, kRvcRs1sShift);
1546   }
1547 
RvcRs2sValue()1548   inline int RvcRs2sValue() const {
1549     DCHECK(this->IsShortInstruction());
1550     return 0b1000 + this->Bits(kRvcRs2sShift + kRvcRs2sBits - 1, kRvcRs2sShift);
1551   }
1552 
Funct7Value()1553   inline int Funct7Value() const {
1554     DCHECK(this->InstructionType() == InstructionBase::kRType);
1555     return this->Bits(kFunct7Shift + kFunct7Bits - 1, kFunct7Shift);
1556   }
1557 
Funct3Value()1558   inline int Funct3Value() const {
1559     DCHECK(this->InstructionType() == InstructionBase::kRType ||
1560            this->InstructionType() == InstructionBase::kIType ||
1561            this->InstructionType() == InstructionBase::kSType ||
1562            this->InstructionType() == InstructionBase::kBType);
1563     return this->Bits(kFunct3Shift + kFunct3Bits - 1, kFunct3Shift);
1564   }
1565 
Funct5Value()1566   inline int Funct5Value() const {
1567     DCHECK(this->InstructionType() == InstructionBase::kRType &&
1568            this->BaseOpcode() == OP_FP);
1569     return this->Bits(kFunct5Shift + kFunct5Bits - 1, kFunct5Shift);
1570   }
1571 
RvcFunct6Value()1572   inline int RvcFunct6Value() const {
1573     DCHECK(this->IsShortInstruction());
1574     return this->Bits(kRvcFunct6Shift + kRvcFunct6Bits - 1, kRvcFunct6Shift);
1575   }
1576 
RvcFunct4Value()1577   inline int RvcFunct4Value() const {
1578     DCHECK(this->IsShortInstruction());
1579     return this->Bits(kRvcFunct4Shift + kRvcFunct4Bits - 1, kRvcFunct4Shift);
1580   }
1581 
RvcFunct3Value()1582   inline int RvcFunct3Value() const {
1583     DCHECK(this->IsShortInstruction());
1584     return this->Bits(kRvcFunct3Shift + kRvcFunct3Bits - 1, kRvcFunct3Shift);
1585   }
1586 
RvcFunct2Value()1587   inline int RvcFunct2Value() const {
1588     DCHECK(this->IsShortInstruction());
1589     return this->Bits(kRvcFunct2Shift + kRvcFunct2Bits - 1, kRvcFunct2Shift);
1590   }
1591 
RvcFunct2BValue()1592   inline int RvcFunct2BValue() const {
1593     DCHECK(this->IsShortInstruction());
1594     return this->Bits(kRvcFunct2BShift + kRvcFunct2Bits - 1, kRvcFunct2BShift);
1595   }
1596 
CsrValue()1597   inline int CsrValue() const {
1598     DCHECK(this->InstructionType() == InstructionBase::kIType &&
1599            this->BaseOpcode() == SYSTEM);
1600     return (this->Bits(kCsrShift + kCsrBits - 1, kCsrShift));
1601   }
1602 
RoundMode()1603   inline int RoundMode() const {
1604     DCHECK((this->InstructionType() == InstructionBase::kRType ||
1605             this->InstructionType() == InstructionBase::kR4Type) &&
1606            this->BaseOpcode() == OP_FP);
1607     return this->Bits(kFunct3Shift + kFunct3Bits - 1, kFunct3Shift);
1608   }
1609 
MemoryOrder(bool is_pred)1610   inline int MemoryOrder(bool is_pred) const {
1611     DCHECK((this->InstructionType() == InstructionBase::kIType &&
1612             this->BaseOpcode() == MISC_MEM));
1613     if (is_pred) {
1614       return this->Bits(kPredOrderShift + kMemOrderBits - 1, kPredOrderShift);
1615     } else {
1616       return this->Bits(kSuccOrderShift + kMemOrderBits - 1, kSuccOrderShift);
1617     }
1618   }
1619 
Imm12Value()1620   inline int Imm12Value() const {
1621     DCHECK(this->InstructionType() == InstructionBase::kIType);
1622     int Value = this->Bits(kImm12Shift + kImm12Bits - 1, kImm12Shift);
1623     return Value << 20 >> 20;
1624   }
1625 
Imm12SExtValue()1626   inline int32_t Imm12SExtValue() const {
1627     int32_t Value = this->Imm12Value() << 20 >> 20;
1628     return Value;
1629   }
1630 
BranchOffset()1631   inline int BranchOffset() const {
1632     DCHECK(this->InstructionType() == InstructionBase::kBType);
1633     // | imm[12|10:5] | rs2 | rs1 | funct3 | imm[4:1|11] | opcode |
1634     //  31          25                      11          7
1635     uint32_t Bits = this->InstructionBits();
1636     int16_t imm13 = ((Bits & 0xf00) >> 7) | ((Bits & 0x7e000000) >> 20) |
1637                     ((Bits & 0x80) << 4) | ((Bits & 0x80000000) >> 19);
1638     return imm13 << 19 >> 19;
1639   }
1640 
StoreOffset()1641   inline int StoreOffset() const {
1642     DCHECK(this->InstructionType() == InstructionBase::kSType);
1643     // | imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode |
1644     //  31       25                      11       7
1645     uint32_t Bits = this->InstructionBits();
1646     int16_t imm12 = ((Bits & 0xf80) >> 7) | ((Bits & 0xfe000000) >> 20);
1647     return imm12 << 20 >> 20;
1648   }
1649 
Imm20UValue()1650   inline int Imm20UValue() const {
1651     DCHECK(this->InstructionType() == InstructionBase::kUType);
1652     // | imm[31:12] | rd | opcode |
1653     //  31        12
1654     int32_t Bits = this->InstructionBits();
1655     return Bits >> 12;
1656   }
1657 
Imm20JValue()1658   inline int Imm20JValue() const {
1659     DCHECK(this->InstructionType() == InstructionBase::kJType);
1660     // | imm[20|10:1|11|19:12] | rd | opcode |
1661     //  31                   12
1662     uint32_t Bits = this->InstructionBits();
1663     int32_t imm20 = ((Bits & 0x7fe00000) >> 20) | ((Bits & 0x100000) >> 9) |
1664                     (Bits & 0xff000) | ((Bits & 0x80000000) >> 11);
1665     return imm20 << 11 >> 11;
1666   }
1667 
IsArithShift()1668   inline bool IsArithShift() const {
1669     // Valid only for right shift operations
1670     DCHECK((this->BaseOpcode() == OP || this->BaseOpcode() == OP_32 ||
1671             this->BaseOpcode() == OP_IMM || this->BaseOpcode() == OP_IMM_32) &&
1672            this->Funct3Value() == 0b101);
1673     return this->InstructionBits() & 0x40000000;
1674   }
1675 
Shamt()1676   inline int Shamt() const {
1677     // Valid only for shift instructions (SLLI, SRLI, SRAI)
1678     DCHECK((this->InstructionBits() & kBaseOpcodeMask) == OP_IMM &&
1679            (this->Funct3Value() == 0b001 || this->Funct3Value() == 0b101));
1680     // | 0A0000 | shamt | rs1 | funct3 | rd | opcode |
1681     //  31       25    20
1682     return this->Bits(kImm12Shift + 5, kImm12Shift);
1683   }
1684 
Shamt32()1685   inline int Shamt32() const {
1686     // Valid only for shift instructions (SLLIW, SRLIW, SRAIW)
1687     DCHECK((this->InstructionBits() & kBaseOpcodeMask) == OP_IMM_32 &&
1688            (this->Funct3Value() == 0b001 || this->Funct3Value() == 0b101));
1689     // | 0A00000 | shamt | rs1 | funct3 | rd | opcode |
1690     //  31        24   20
1691     return this->Bits(kImm12Shift + 4, kImm12Shift);
1692   }
1693 
RvcImm6Value()1694   inline int RvcImm6Value() const {
1695     DCHECK(this->IsShortInstruction());
1696     // | funct3 | imm[5] | rs1/rd | imm[4:0] | opcode |
1697     //  15         12              6        2
1698     uint32_t Bits = this->InstructionBits();
1699     int32_t imm6 = ((Bits & 0x1000) >> 7) | ((Bits & 0x7c) >> 2);
1700     return imm6 << 26 >> 26;
1701   }
1702 
RvcImm6Addi16spValue()1703   inline int RvcImm6Addi16spValue() const {
1704     DCHECK(this->IsShortInstruction());
1705     // | funct3 | nzimm[9] | 2 | nzimm[4|6|8:7|5] | opcode |
1706     //  15         12           6                2
1707     uint32_t Bits = this->InstructionBits();
1708     int32_t imm10 = ((Bits & 0x1000) >> 3) | ((Bits & 0x40) >> 2) |
1709                     ((Bits & 0x20) << 1) | ((Bits & 0x18) << 4) |
1710                     ((Bits & 0x4) << 3);
1711     DCHECK_NE(imm10, 0);
1712     return imm10 << 22 >> 22;
1713   }
1714 
RvcImm8Addi4spnValue()1715   inline int RvcImm8Addi4spnValue() const {
1716     DCHECK(this->IsShortInstruction());
1717     // | funct3 | nzimm[11]  | rd' | opcode |
1718     //  15      13           5     2
1719     uint32_t Bits = this->InstructionBits();
1720     int32_t uimm10 = ((Bits & 0x20) >> 2) | ((Bits & 0x40) >> 4) |
1721                      ((Bits & 0x780) >> 1) | ((Bits & 0x1800) >> 7);
1722     DCHECK_NE(uimm10, 0);
1723     return uimm10;
1724   }
1725 
RvcShamt6()1726   inline int RvcShamt6() const {
1727     DCHECK(this->IsShortInstruction());
1728     // | funct3 | nzuimm[5] | rs1/rd | nzuimm[4:0] | opcode |
1729     //  15         12                 6           2
1730     int32_t imm6 = this->RvcImm6Value();
1731     return imm6 & 0x3f;
1732   }
1733 
RvcImm6LwspValue()1734   inline int RvcImm6LwspValue() const {
1735     DCHECK(this->IsShortInstruction());
1736     // | funct3 | uimm[5] | rs1 | uimm[4:2|7:6] | opcode |
1737     //  15         12            6             2
1738     uint32_t Bits = this->InstructionBits();
1739     int32_t imm8 =
1740         ((Bits & 0x1000) >> 7) | ((Bits & 0x70) >> 2) | ((Bits & 0xc) << 4);
1741     return imm8;
1742   }
1743 
RvcImm6LdspValue()1744   inline int RvcImm6LdspValue() const {
1745     DCHECK(this->IsShortInstruction());
1746     // | funct3 | uimm[5] | rs1 | uimm[4:3|8:6] | opcode |
1747     //  15         12            6             2
1748     uint32_t Bits = this->InstructionBits();
1749     int32_t imm9 =
1750         ((Bits & 0x1000) >> 7) | ((Bits & 0x60) >> 2) | ((Bits & 0x1c) << 4);
1751     return imm9;
1752   }
1753 
RvcImm6SwspValue()1754   inline int RvcImm6SwspValue() const {
1755     DCHECK(this->IsShortInstruction());
1756     // | funct3 | uimm[5:2|7:6] | rs2 | opcode |
1757     //  15       12            7
1758     uint32_t Bits = this->InstructionBits();
1759     int32_t imm8 = ((Bits & 0x1e00) >> 7) | ((Bits & 0x180) >> 1);
1760     return imm8;
1761   }
1762 
RvcImm6SdspValue()1763   inline int RvcImm6SdspValue() const {
1764     DCHECK(this->IsShortInstruction());
1765     // | funct3 | uimm[5:3|8:6] | rs2 | opcode |
1766     //  15       12            7
1767     uint32_t Bits = this->InstructionBits();
1768     int32_t imm9 = ((Bits & 0x1c00) >> 7) | ((Bits & 0x380) >> 1);
1769     return imm9;
1770   }
1771 
RvcImm5WValue()1772   inline int RvcImm5WValue() const {
1773     DCHECK(this->IsShortInstruction());
1774     // | funct3 | imm[5:3] | rs1 | imm[2|6] | rd | opcode |
1775     //  15       12       10     6          4     2
1776     uint32_t Bits = this->InstructionBits();
1777     int32_t imm7 =
1778         ((Bits & 0x1c00) >> 7) | ((Bits & 0x40) >> 4) | ((Bits & 0x20) << 1);
1779     return imm7;
1780   }
1781 
RvcImm5DValue()1782   inline int RvcImm5DValue() const {
1783     DCHECK(this->IsShortInstruction());
1784     // | funct3 | imm[5:3] | rs1 | imm[7:6] | rd | opcode |
1785     //  15       12        10    6          4     2
1786     uint32_t Bits = this->InstructionBits();
1787     int32_t imm8 = ((Bits & 0x1c00) >> 7) | ((Bits & 0x60) << 1);
1788     return imm8;
1789   }
1790 
RvcImm11CJValue()1791   inline int RvcImm11CJValue() const {
1792     DCHECK(this->IsShortInstruction());
1793     // | funct3 | [11|4|9:8|10|6|7|3:1|5] | opcode |
1794     //  15      12                        2
1795     uint32_t Bits = this->InstructionBits();
1796     int32_t imm12 = ((Bits & 0x4) << 3) | ((Bits & 0x38) >> 2) |
1797                     ((Bits & 0x40) << 1) | ((Bits & 0x80) >> 1) |
1798                     ((Bits & 0x100) << 2) | ((Bits & 0x600) >> 1) |
1799                     ((Bits & 0x800) >> 7) | ((Bits & 0x1000) >> 1);
1800     return imm12 << 20 >> 20;
1801   }
1802 
RvcImm8BValue()1803   inline int RvcImm8BValue() const {
1804     DCHECK(this->IsShortInstruction());
1805     // | funct3 | imm[8|4:3] | rs1` | imm[7:6|2:1|5]  | opcode |
1806     //  15       12        10       7                 2
1807     uint32_t Bits = this->InstructionBits();
1808     int32_t imm9 = ((Bits & 0x4) << 3) | ((Bits & 0x18) >> 2) |
1809                    ((Bits & 0x60) << 1) | ((Bits & 0xc00) >> 7) |
1810                    ((Bits & 0x1000) >> 4);
1811     return imm9 << 23 >> 23;
1812   }
1813 
vl_vs_width()1814   inline int vl_vs_width() {
1815     int width = 0;
1816     if ((this->InstructionBits() & kBaseOpcodeMask) != LOAD_FP &&
1817         (this->InstructionBits() & kBaseOpcodeMask) != STORE_FP)
1818       return -1;
1819     switch (this->InstructionBits() & (kRvvWidthMask | kRvvMewMask)) {
1820       case 0x0:
1821         width = 8;
1822         break;
1823       case 0x00005000:
1824         width = 16;
1825         break;
1826       case 0x00006000:
1827         width = 32;
1828         break;
1829       case 0x00007000:
1830         width = 64;
1831         break;
1832       case 0x10000000:
1833         width = 128;
1834         break;
1835       case 0x10005000:
1836         width = 256;
1837         break;
1838       case 0x10006000:
1839         width = 512;
1840         break;
1841       case 0x10007000:
1842         width = 1024;
1843         break;
1844       default:
1845         width = -1;
1846         break;
1847     }
1848     return width;
1849   }
1850 
Rvvzimm()1851   inline uint32_t Rvvzimm() const {
1852     if ((this->InstructionBits() &
1853          (kBaseOpcodeMask | kFunct3Mask | 0x80000000)) == RO_V_VSETVLI) {
1854       uint32_t Bits = this->InstructionBits();
1855       uint32_t zimm = Bits & kRvvZimmMask;
1856       return zimm >> kRvvZimmShift;
1857     } else {
1858       DCHECK_EQ(this->InstructionBits() &
1859                     (kBaseOpcodeMask | kFunct3Mask | 0xC0000000),
1860                 RO_V_VSETIVLI);
1861       uint32_t Bits = this->InstructionBits();
1862       uint32_t zimm = Bits & kRvvZimmMask;
1863       return (zimm >> kRvvZimmShift) & 0x3FF;
1864     }
1865   }
1866 
Rvvuimm()1867   inline uint32_t Rvvuimm() const {
1868     DCHECK_EQ(
1869         this->InstructionBits() & (kBaseOpcodeMask | kFunct3Mask | 0xC0000000),
1870         RO_V_VSETIVLI);
1871     uint32_t Bits = this->InstructionBits();
1872     uint32_t uimm = Bits & kRvvUimmMask;
1873     return uimm >> kRvvUimmShift;
1874   }
1875 
RvvVsew()1876   inline uint32_t RvvVsew() const {
1877     uint32_t zimm = this->Rvvzimm();
1878     uint32_t vsew = (zimm >> 3) & 0x7;
1879     return vsew;
1880   }
1881 
RvvVlmul()1882   inline uint32_t RvvVlmul() const {
1883     uint32_t zimm = this->Rvvzimm();
1884     uint32_t vlmul = zimm & 0x7;
1885     return vlmul;
1886   }
1887 
RvvVM()1888   inline uint8_t RvvVM() const {
1889     DCHECK(this->InstructionType() == InstructionBase::kVType ||
1890            this->InstructionType() == InstructionBase::kIType ||
1891            this->InstructionType() == InstructionBase::kSType);
1892     return this->Bits(kRvvVmShift + kRvvVmBits - 1, kRvvVmShift);
1893   }
1894 
RvvSEW()1895   inline const char* RvvSEW() const {
1896     uint32_t vsew = this->RvvVsew();
1897     switch (vsew) {
1898 #define CAST_VSEW(name) \
1899   case name:            \
1900     return #name;
1901       RVV_SEW(CAST_VSEW)
1902       default:
1903         return "unknown";
1904 #undef CAST_VSEW
1905     }
1906   }
1907 
RvvLMUL()1908   inline const char* RvvLMUL() const {
1909     uint32_t vlmul = this->RvvVlmul();
1910     switch (vlmul) {
1911 #define CAST_VLMUL(name) \
1912   case name:             \
1913     return #name;
1914       RVV_LMUL(CAST_VLMUL)
1915       default:
1916         return "unknown";
1917 #undef CAST_VLMUL
1918     }
1919   }
1920 
1921 #define sext(x, len) (((int32_t)(x) << (32 - len)) >> (32 - len))
1922 #define zext(x, len) (((uint32_t)(x) << (32 - len)) >> (32 - len))
1923 
RvvSimm5()1924   inline int32_t RvvSimm5() const {
1925     DCHECK(this->InstructionType() == InstructionBase::kVType);
1926     return sext(this->Bits(kRvvImm5Shift + kRvvImm5Bits - 1, kRvvImm5Shift),
1927                 kRvvImm5Bits);
1928   }
1929 
RvvUimm5()1930   inline uint32_t RvvUimm5() const {
1931     DCHECK(this->InstructionType() == InstructionBase::kVType);
1932     uint32_t imm = this->Bits(kRvvImm5Shift + kRvvImm5Bits - 1, kRvvImm5Shift);
1933     return zext(imm, kRvvImm5Bits);
1934   }
1935 #undef sext
1936 #undef zext
AqValue()1937   inline bool AqValue() const { return this->Bits(kAqShift, kAqShift); }
1938 
RlValue()1939   inline bool RlValue() const { return this->Bits(kRlShift, kRlShift); }
1940 
1941   // Say if the instruction is a break or a trap.
1942   bool IsTrap() const;
1943 };
1944 
1945 class Instruction : public InstructionGetters<InstructionBase> {
1946  public:
1947   // Instructions are read of out a code stream. The only way to get a
1948   // reference to an instruction is to convert a pointer. There is no way
1949   // to allocate or create instances of class Instruction.
1950   // Use the At(pc) function to create references to Instruction.
At(byte * pc)1951   static Instruction* At(byte* pc) {
1952     return reinterpret_cast<Instruction*>(pc);
1953   }
1954 
1955  private:
1956   // We need to prevent the creation of instances of class Instruction.
1957   DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
1958 };
1959 
1960 // -----------------------------------------------------------------------------
1961 // RISC-V assembly various constants.
1962 
1963 // C/C++ argument slots size.
1964 const int kCArgSlotCount = 0;
1965 
1966 // TODO(plind): below should be based on kSystemPointerSize
1967 // TODO(plind): find all usages and remove the needless instructions for n64.
1968 const int kCArgsSlotsSize = kCArgSlotCount * kInstrSize * 2;
1969 
1970 const int kInvalidStackOffset = -1;
1971 const int kBranchReturnOffset = 2 * kInstrSize;
1972 
1973 static const int kNegOffset = 0x00008000;
1974 
1975 // -----------------------------------------------------------------------------
1976 // Instructions.
1977 
1978 template <class P>
IsTrap()1979 bool InstructionGetters<P>::IsTrap() const {
1980   return (this->InstructionBits() == kBreakInstr);
1981 }
1982 
1983 }  // namespace internal
1984 }  // namespace v8
1985 
1986 #endif  // V8_CODEGEN_RISCV64_CONSTANTS_RISCV64_H_
1987