| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegAllocFast.cpp | 86 Register VirtReg; ///< Virtual register number. member
203 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg()
248 int RegAllocFast::getStackSpaceFor(Register VirtReg) { in getStackSpaceFor()
267 bool RegAllocFast::mayLiveOut(Register VirtReg) { in mayLiveOut()
296 bool RegAllocFast::mayLiveIn(Register VirtReg) { in mayLiveIn()
315 void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg, in spill()
343 void RegAllocFast::reload(MachineBasicBlock::iterator Before, Register VirtReg, in reload()
397 void RegAllocFast::killVirtReg(Register VirtReg) { in killVirtReg()
408 Register VirtReg) { in spillVirtReg()
524 switch (Register VirtReg = PhysRegState[PhysReg]) { in definePhysReg() local
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| D | LiveRegMatrix.cpp | 104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign()
146 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, in checkRegMaskInterference()
164 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, in checkRegUnitInterference()
186 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
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| D | RegAllocGreedy.cpp | 259 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
636 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg()
651 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
762 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign()
809 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign()
872 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
969 bool RAGreedy::canEvictInterferenceInRange(LiveInterval &VirtReg, in canEvictInterferenceInRange()
1023 LiveInterval &VirtReg, in getCheapestEvicteeWeight()
1048 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
1106 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict()
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| D | RegAllocBasic.cpp | 159 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
204 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
256 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
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| D | LiveIntervalUnion.cpp | 29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract()
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| D | VirtRegMap.cpp | 101 bool VirtRegMap::hasPreferredPhys(Register VirtReg) { in hasPreferredPhys()
110 bool VirtRegMap::hasKnownPreference(Register VirtReg) { in hasKnownPreference()
314 Register VirtReg = Register::index2VirtReg(Idx); in addMBBLiveIns() local
517 Register VirtReg = MO.getReg(); in rewrite() local
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| D | AllocationOrder.cpp | 29 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder()
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| D | RegAllocBase.cpp | 89 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
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| D | RegisterCoalescer.h | 62 CoalescerPair(unsigned VirtReg, unsigned PhysReg, in CoalescerPair()
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| D | LiveDebugVariables.cpp | 603 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { in mapVirtReg()
609 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { in lookupVirtReg()
1193 Register VirtReg = Loc.getReg(); in rewriteLocations() local
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| D | PHIElimination.cpp | 221 static bool isImplicitlyDefined(unsigned VirtReg, in isImplicitlyDefined()
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| D | TargetRegisterInfo.cpp | 383 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints()
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| D | MachineBasicBlock.cpp | 509 Register VirtReg = I->getOperand(0).getReg(); in addLiveIn() local
516 Register VirtReg = MRI.createVirtualRegister(RC); in addLiveIn() local
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| D | InlineSpiller.cpp | 543 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { in reMaterializeFor()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIPreAllocateWWMRegs.cpp | 128 const Register VirtReg = MO.getReg(); in rewriteRegs() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | VirtRegMap.h | 148 unsigned getOriginal(unsigned VirtReg) const { in getOriginal()
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| D | ScheduleDAGInstrs.h | 53 unsigned VirtReg; member
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| D | RegisterPressure.h | 535 bool hasUntiedDef(unsigned VirtReg) const { in hasUntiedDef()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 77 SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 301 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints()
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