• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*!
2  * \copy
3  *     Copyright (c)  2009-2013, Cisco Systems
4  *     All rights reserved.
5  *
6  *     Redistribution and use in source and binary forms, with or without
7  *     modification, are permitted provided that the following conditions
8  *     are met:
9  *
10  *        * Redistributions of source code must retain the above copyright
11  *          notice, this list of conditions and the following disclaimer.
12  *
13  *        * Redistributions in binary form must reproduce the above copyright
14  *          notice, this list of conditions and the following disclaimer in
15  *          the documentation and/or other materials provided with the
16  *          distribution.
17  *
18  *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  *     "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  *     LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21  *     FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22  *     COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23  *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24  *     BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25  *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
26  *     CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  *     LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
28  *     ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  *     POSSIBILITY OF SUCH DAMAGE.
30  *
31  *
32  * \file    cpu_core.h
33  *
34  * \brief   cpu core feature detection
35  *
36  * \date    4/24/2009 Created
37  *
38  *************************************************************************************
39  */
40 #if !defined(WELS_CPU_CORE_FEATURE_DETECTION_H__)
41 #define WELS_CPU_CORE_FEATURE_DETECTION_H__
42 
43 /*
44  *  WELS CPU feature flags
45  */
46 #define WELS_CPU_MMX        0x00000001    /* mmx */
47 #define WELS_CPU_MMXEXT     0x00000002    /* mmx-ext*/
48 #define WELS_CPU_SSE        0x00000004    /* sse */
49 #define WELS_CPU_SSE2       0x00000008    /* sse 2 */
50 #define WELS_CPU_SSE3       0x00000010    /* sse 3 */
51 #define WELS_CPU_SSE41      0x00000020    /* sse 4.1 */
52 #define WELS_CPU_3DNOW      0x00000040    /* 3dnow! */
53 #define WELS_CPU_3DNOWEXT   0x00000080    /* 3dnow! ext */
54 #define WELS_CPU_ALTIVEC    0x00000100    /* altivec */
55 #define WELS_CPU_SSSE3      0x00000200    /* ssse3 */
56 #define WELS_CPU_SSE42      0x00000400    /* sse 4.2 */
57 
58 /* CPU features application extensive */
59 #define WELS_CPU_FPU        0x00001000  /* x87-FPU on chip */
60 #define WELS_CPU_HTT        0x00002000  /* Hyper-Threading Technology (HTT), Multi-threading enabled feature:
61                                            physical processor package is capable of supporting more than one logic processor
62                                         */
63 #define WELS_CPU_CMOV       0x00004000  /* Conditional Move Instructions,
64                                            also if x87-FPU is present at indicated by the CPUID.FPU feature bit, then FCOMI and FCMOV are supported
65                                         */
66 #define WELS_CPU_MOVBE      0x00008000  /* MOVBE instruction */
67 #define WELS_CPU_AES        0x00010000  /* AES instruction extensions */
68 #define WELS_CPU_FMA        0x00020000  /* AVX VEX FMA instruction sets */
69 #define WELS_CPU_AVX        0x00000800  /* Advanced Vector eXtentions */
70 
71 #ifdef HAVE_AVX2
72 #define WELS_CPU_AVX2       0x00040000  /* AVX2 */
73 #else
74 #define WELS_CPU_AVX2       0x00000000  /* !AVX2 */
75 #endif
76 
77 #define WELS_CPU_AVX512F    0x00080000  /* AVX512F */
78 #define WELS_CPU_AVX512CD   0x00100000  /* AVX512CD */
79 #define WELS_CPU_AVX512DQ   0x00200000  /* AVX512DQ */
80 #define WELS_CPU_AVX512BW   0x00400000  /* AVX512BW */
81 #define WELS_CPU_AVX512VL   0x00800000  /* AVX512VL */
82 
83 #define WELS_CPU_CACHELINE_16    0x10000000    /* CacheLine Size 16 */
84 #define WELS_CPU_CACHELINE_32    0x20000000    /* CacheLine Size 32 */
85 #define WELS_CPU_CACHELINE_64    0x40000000    /* CacheLine Size 64 */
86 #define WELS_CPU_CACHELINE_128   0x80000000    /* CacheLine Size 128 */
87 
88 /* For the android OS */
89 #define WELS_CPU_ARMv7      0x000001    /* ARMv7 */
90 #define WELS_CPU_VFPv3      0x000002    /* VFPv3 */
91 #define WELS_CPU_NEON       0x000004    /* NEON */
92 
93 /* For loongson */
94 #define WELS_CPU_MMI        0x00000001  /* mmi */
95 #define WELS_CPU_MSA        0x00000002  /* msa */
96 #define WELS_CPU_LSX        0x00000003  /* lsx */
97 #define WELS_CPU_LASX       0x00000004  /* lasx */
98 
99 /*
100  *  Interfaces for CPU core feature detection as below
101  */
102 
103 #endif//WELS_CPU_CORE_FEATURE_DETECTION_H__
104