1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <assert.h>
35 #include <stdint.h>
36
37 #include "brw_eu_defines.h"
38 #include "brw_isa_info.h"
39 #include "brw_reg_type.h"
40 #include "dev/intel_device_info.h"
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
47 typedef struct brw_inst {
48 uint64_t data[2];
49 } brw_inst;
50
51 static inline uint64_t brw_inst_bits(const brw_inst *inst,
52 unsigned high, unsigned low);
53 static inline void brw_inst_set_bits(brw_inst *inst,
54 unsigned high, unsigned low,
55 uint64_t value);
56
57 #define FC(name, hi4, lo4, hi12, lo12, assertions) \
58 static inline void \
59 brw_inst_set_##name(const struct intel_device_info *devinfo, \
60 brw_inst *inst, uint64_t v) \
61 { \
62 assert(assertions); \
63 if (devinfo->ver >= 12) \
64 brw_inst_set_bits(inst, hi12, lo12, v); \
65 else \
66 brw_inst_set_bits(inst, hi4, lo4, v); \
67 } \
68 static inline uint64_t \
69 brw_inst_##name(const struct intel_device_info *devinfo, \
70 const brw_inst *inst) \
71 { \
72 assert(assertions); \
73 if (devinfo->ver >= 12) \
74 return brw_inst_bits(inst, hi12, lo12); \
75 else \
76 return brw_inst_bits(inst, hi4, lo4); \
77 }
78
79 /* A simple macro for fields which stay in the same place on all generations,
80 * except for Gfx12!
81 */
82 #define F(name, hi4, lo4, hi12, lo12) FC(name, hi4, lo4, hi12, lo12, true)
83
84 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
85 hi7, lo7, hi8, lo8, hi12, lo12) \
86 unsigned high, low; \
87 if (devinfo->ver >= 12) { \
88 high = hi12; low = lo12; \
89 } else if (devinfo->ver >= 8) { \
90 high = hi8; low = lo8; \
91 } else if (devinfo->ver >= 7) { \
92 high = hi7; low = lo7; \
93 } else if (devinfo->ver >= 6) { \
94 high = hi6; low = lo6; \
95 } else if (devinfo->ver >= 5) { \
96 high = hi5; low = lo5; \
97 } else if (devinfo->verx10 >= 45) { \
98 high = hi45; low = lo45; \
99 } else { \
100 high = hi4; low = lo4; \
101 } \
102 assert(((int) high) != -1 && ((int) low) != -1);
103
104 /* A general macro for cases where the field has moved to several different
105 * bit locations across generations. GCC appears to combine cases where the
106 * bits are identical, removing some of the inefficiency.
107 */
108 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
109 hi7, lo7, hi8, lo8, hi12, lo12) \
110 static inline void \
111 brw_inst_set_##name(const struct intel_device_info *devinfo, \
112 brw_inst *inst, uint64_t value) \
113 { \
114 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
115 hi7, lo7, hi8, lo8, hi12, lo12) \
116 brw_inst_set_bits(inst, high, low, value); \
117 } \
118 static inline uint64_t \
119 brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\
120 { \
121 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
122 hi7, lo7, hi8, lo8, hi12, lo12) \
123 return brw_inst_bits(inst, high, low); \
124 }
125
126 /* A macro for fields which moved as of Gfx8+. */
127 #define F8(name, gfx4_high, gfx4_low, gfx8_high, gfx8_low, \
128 gfx12_high, gfx12_low) \
129 FF(name, \
130 /* 4: */ gfx4_high, gfx4_low, \
131 /* 4.5: */ gfx4_high, gfx4_low, \
132 /* 5: */ gfx4_high, gfx4_low, \
133 /* 6: */ gfx4_high, gfx4_low, \
134 /* 7: */ gfx4_high, gfx4_low, \
135 /* 8: */ gfx8_high, gfx8_low, \
136 /* 12: */ gfx12_high, gfx12_low);
137
138 /* Macro for fields that gained extra discontiguous MSBs in Gfx12 (specified
139 * by hi12ex-lo12ex).
140 */
141 #define FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
142 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, assertions) \
143 static inline void \
144 brw_inst_set_##name(const struct intel_device_info *devinfo, \
145 brw_inst *inst, uint64_t value) \
146 { \
147 assert(assertions); \
148 if (devinfo->ver >= 12) { \
149 const unsigned k = hi12 - lo12 + 1; \
150 if (hi12ex != -1 && lo12ex != -1) \
151 brw_inst_set_bits(inst, hi12ex, lo12ex, value >> k); \
152 brw_inst_set_bits(inst, hi12, lo12, value & ((1ull << k) - 1)); \
153 } else { \
154 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
155 hi7, lo7, hi8, lo8, -1, -1); \
156 brw_inst_set_bits(inst, high, low, value); \
157 } \
158 } \
159 static inline uint64_t \
160 brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\
161 { \
162 assert(assertions); \
163 if (devinfo->ver >= 12) { \
164 const unsigned k = hi12 - lo12 + 1; \
165 return (hi12ex == -1 || lo12ex == -1 ? 0 : \
166 brw_inst_bits(inst, hi12ex, lo12ex) << k) | \
167 brw_inst_bits(inst, hi12, lo12); \
168 } else { \
169 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
170 hi7, lo7, hi8, lo8, -1, -1); \
171 return brw_inst_bits(inst, high, low); \
172 } \
173 }
174
175 #define FD(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
176 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12) \
177 FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
178 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, true)
179
180 /* Macro for fields that didn't move across generations until Gfx12, and then
181 * gained extra discontiguous bits.
182 */
183 #define FDC(name, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions) \
184 FFDC(name, hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
185 hi4, lo4, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions)
186
187
188 /* Macro for the 2-bit register file field, which on Gfx12+ is stored as the
189 * variable length combination of an IsImm (hi12) bit and an additional file
190 * (lo12) bit.
191 */
192 #define FI(name, hi4, lo4, hi8, lo8, hi12, lo12) \
193 static inline void \
194 brw_inst_set_##name(const struct intel_device_info *devinfo, \
195 brw_inst *inst, uint64_t value) \
196 { \
197 if (devinfo->ver >= 12) { \
198 brw_inst_set_bits(inst, hi12, hi12, value >> 1); \
199 if ((value >> 1) == 0) \
200 brw_inst_set_bits(inst, lo12, lo12, value & 1); \
201 } else { \
202 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
203 hi4, lo4, hi8, lo8, -1, -1); \
204 brw_inst_set_bits(inst, high, low, value); \
205 } \
206 } \
207 static inline uint64_t \
208 brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\
209 { \
210 if (devinfo->ver >= 12) { \
211 return (brw_inst_bits(inst, hi12, hi12) << 1) | \
212 (brw_inst_bits(inst, hi12, hi12) == 0 ? \
213 brw_inst_bits(inst, lo12, lo12) : 1); \
214 } else { \
215 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
216 hi4, lo4, hi8, lo8, -1, -1); \
217 return brw_inst_bits(inst, high, low); \
218 } \
219 }
220
221 /* Macro for fields that become a constant in Gfx12+ not actually represented
222 * in the instruction.
223 */
224 #define FK(name, hi4, lo4, const12) \
225 static inline void \
226 brw_inst_set_##name(const struct intel_device_info *devinfo, \
227 brw_inst *inst, uint64_t v) \
228 { \
229 if (devinfo->ver >= 12) \
230 assert(v == (const12)); \
231 else \
232 brw_inst_set_bits(inst, hi4, lo4, v); \
233 } \
234 static inline uint64_t \
235 brw_inst_##name(const struct intel_device_info *devinfo, \
236 const brw_inst *inst) \
237 { \
238 if (devinfo->ver >= 12) \
239 return (const12); \
240 else \
241 return brw_inst_bits(inst, hi4, lo4); \
242 }
243
244 F(src1_vstride, /* 4+ */ 120, 117, /* 12+ */ 119, 116)
245 F(src1_width, /* 4+ */ 116, 114, /* 12+ */ 115, 113)
246 F(src1_da16_swiz_w, /* 4+ */ 115, 114, /* 12+ */ -1, -1)
247 F(src1_da16_swiz_z, /* 4+ */ 113, 112, /* 12+ */ -1, -1)
248 F(src1_hstride, /* 4+ */ 113, 112, /* 12+ */ 97, 96)
249 F(src1_address_mode, /* 4+ */ 111, 111, /* 12+ */ 112, 112)
250 /** Src1.SrcMod @{ */
251 F(src1_negate, /* 4+ */ 110, 110, /* 12+ */ 121, 121)
252 F(src1_abs, /* 4+ */ 109, 109, /* 12+ */ 120, 120)
253 /** @} */
254 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105, /* 12+ */ 111, 108)
255 F(src1_da_reg_nr, /* 4+ */ 108, 101, /* 12+ */ 111, 104)
256 F(src1_da16_subreg_nr, /* 4+ */ 100, 100, /* 12+ */ -1, -1)
257 F(src1_da1_subreg_nr, /* 4+ */ 100, 96, /* 12+ */ 103, 99)
258 F(src1_da16_swiz_y, /* 4+ */ 99, 98, /* 12+ */ -1, -1)
259 F(src1_da16_swiz_x, /* 4+ */ 97, 96, /* 12+ */ -1, -1)
260 F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91, /* 12+ */ 91, 88)
261 FI(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89, /* 12+ */ 47, 98)
262 F(src1_is_imm, /* 4+ */ -1, -1, /* 12+ */ 47, 47)
263 F(src0_vstride, /* 4+ */ 88, 85, /* 12+ */ 87, 84)
264 F(src0_width, /* 4+ */ 84, 82, /* 12+ */ 83, 81)
265 F(src0_da16_swiz_w, /* 4+ */ 83, 82, /* 12+ */ -1, -1)
266 F(src0_da16_swiz_z, /* 4+ */ 81, 80, /* 12+ */ -1, -1)
267 F(src0_hstride, /* 4+ */ 81, 80, /* 12+ */ 65, 64)
268 F(src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ 80, 80)
269 /** Src0.SrcMod @{ */
270 F(src0_negate, /* 4+ */ 78, 78, /* 12+ */ 45, 45)
271 F(src0_abs, /* 4+ */ 77, 77, /* 12+ */ 44, 44)
272 /** @} */
273 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73, /* 12+ */ 79, 76)
274 F(src0_da_reg_nr, /* 4+ */ 76, 69, /* 12+ */ 79, 72)
275 F(src0_da16_subreg_nr, /* 4+ */ 68, 68, /* 12+ */ -1, -1)
276 F(src0_da1_subreg_nr, /* 4+ */ 68, 64, /* 12+ */ 71, 67)
277 F(src0_da16_swiz_y, /* 4+ */ 67, 66, /* 12+ */ -1, -1)
278 F(src0_da16_swiz_x, /* 4+ */ 65, 64, /* 12+ */ -1, -1)
279 F(dst_address_mode, /* 4+ */ 63, 63, /* 12+ */ 35, 35)
280 F(dst_hstride, /* 4+ */ 62, 61, /* 12+ */ 49, 48)
281 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57, /* 12+ */ 63, 60)
282 F(dst_da_reg_nr, /* 4+ */ 60, 53, /* 12+ */ 63, 56)
283 F(dst_da16_subreg_nr, /* 4+ */ 52, 52, /* 12+ */ -1, -1)
284 F(dst_da1_subreg_nr, /* 4+ */ 52, 48, /* 12+ */ 55, 51)
285 F(da16_writemask, /* 4+ */ 51, 48, /* 12+ */ -1, -1) /* Dst.ChanEn */
286 F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43, /* 12+ */ 43, 40)
287 FI(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 46, 66)
288 F(src0_is_imm, /* 4+ */ -1, -1, /* 12+ */ 46, 46)
289 F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37, /* 12+ */ 39, 36)
290 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35, /* 12+ */ 50, 50)
291 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31)
292 FF(flag_reg_nr,
293 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
294 /* 7: */ 90, 90,
295 /* 8: */ 33, 33,
296 /* 12: */ 23, 23)
297 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32, /* 12+ */ 22, 22)
298 F(saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34)
299 F(debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
300 F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
301 FC(branch_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver >= 8)
302 FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver >= 6)
303 FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->verx10 == 45 ||
304 devinfo->ver == 5)
305 F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
306 FC(math_function, /* 4+ */ 27, 24, /* 12+ */ 95, 92, devinfo->ver >= 6)
307 F(exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16)
308 F(pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28)
309 F(pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24)
310 F(thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
311 F(atomic_control, /* 4+ */ -1, -1, /* 12+ */ 32, 32)
312 F(qtr_control, /* 4+ */ 13, 12, /* 12+ */ 21, 20)
313 FF(nib_control,
314 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
315 /* 7: */ 47, 47,
316 /* 8: */ 11, 11,
317 /* 12: */ 19, 19)
318 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
319 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
320 F(swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8)
321 FK(access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
322 /* Bit 7 is Reserved (for future Opcode expansion) */
323 F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
324
325 /**
326 * Three-source instructions:
327 * @{
328 */
329 F(3src_src2_reg_nr, /* 4+ */ 125, 118, /* 12+ */ 127, 120) /* same in align1 */
330 F(3src_a16_src2_subreg_nr, /* 4+ */ 117, 115, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
331 F(3src_a16_src2_swizzle, /* 4+ */ 114, 107, /* 12+ */ -1, -1)
332 F(3src_a16_src2_rep_ctrl, /* 4+ */ 106, 106, /* 12+ */ -1, -1)
333 F(3src_src1_reg_nr, /* 4+ */ 104, 97, /* 12+ */ 111, 104) /* same in align1 */
334 F(3src_a16_src1_subreg_nr, /* 4+ */ 96, 94, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
335 F(3src_a16_src1_swizzle, /* 4+ */ 93, 86, /* 12+ */ -1, -1)
336 F(3src_a16_src1_rep_ctrl, /* 4+ */ 85, 85, /* 12+ */ -1, -1)
337 F(3src_src0_reg_nr, /* 4+ */ 83, 76, /* 12+ */ 79, 72) /* same in align1 */
338 F(3src_a16_src0_subreg_nr, /* 4+ */ 75, 73, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
339 F(3src_a16_src0_swizzle, /* 4+ */ 72, 65, /* 12+ */ -1, -1)
340 F(3src_a16_src0_rep_ctrl, /* 4+ */ 64, 64, /* 12+ */ -1, -1)
341 F(3src_dst_reg_nr, /* 4+ */ 63, 56, /* 12+ */ 63, 56) /* same in align1 */
342 F(3src_a16_dst_subreg_nr, /* 4+ */ 55, 53, /* 12+ */ -1, -1)
343 F(3src_a16_dst_writemask, /* 4+ */ 52, 49, /* 12+ */ -1, -1)
344 F8(3src_a16_nib_ctrl, /* 4+ */ 47, 47, /* 8+ */ 11, 11, /* 12+ */ -1, -1) /* only exists on IVB+ */
345 F8(3src_a16_dst_hw_type, /* 4+ */ 45, 44, /* 8+ */ 48, 46, /* 12+ */ -1, -1) /* only exists on IVB+ */
346 F8(3src_a16_src_hw_type, /* 4+ */ 43, 42, /* 8+ */ 45, 43, /* 12+ */ -1, -1)
347 F8(3src_src2_negate, /* 4+ */ 41, 41, /* 8+ */ 42, 42, /* 12+ */ 85, 85)
348 F8(3src_src2_abs, /* 4+ */ 40, 40, /* 8+ */ 41, 41, /* 12+ */ 84, 84)
349 F8(3src_src1_negate, /* 4+ */ 39, 39, /* 8+ */ 40, 40, /* 12+ */ 87, 87)
350 F8(3src_src1_abs, /* 4+ */ 38, 38, /* 8+ */ 39, 39, /* 12+ */ 86, 86)
351 F8(3src_src0_negate, /* 4+ */ 37, 37, /* 8+ */ 38, 38, /* 12+ */ 45, 45)
352 F8(3src_src0_abs, /* 4+ */ 36, 36, /* 8+ */ 37, 37, /* 12+ */ 44, 44)
353 F8(3src_a16_src1_type, /* 4+ */ -1, -1, /* 8+ */ 36, 36, /* 12+ */ -1, -1)
354 F8(3src_a16_src2_type, /* 4+ */ -1, -1, /* 8+ */ 35, 35, /* 12+ */ -1, -1)
355 F8(3src_a16_flag_reg_nr, /* 4+ */ 34, 34, /* 8+ */ 33, 33, /* 12+ */ -1, -1)
356 F8(3src_a16_flag_subreg_nr, /* 4+ */ 33, 33, /* 8+ */ 32, 32, /* 12+ */ -1, -1)
357 FF(3src_a16_dst_reg_file,
358 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
359 /* 6: */ 32, 32,
360 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1,
361 /* 12: */ -1, -1)
362 F(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34)
363 F(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
364 F(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
365 F(3src_acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33)
366 F(3src_cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
367 F(3src_exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16)
368 F(3src_pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28)
369 F(3src_pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24)
370 F(3src_thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
371 F(3src_atomic_control, /* 4+ */ -1, -1, /* 12+ */ 32, 32)
372 F(3src_qtr_control, /* 4+ */ 13, 12, /* 12+ */ 21, 20)
373 F8(3src_no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
374 F8(3src_no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
375 F8(3src_mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31)
376 FK(3src_access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
377 F(3src_swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8)
378 /* Bit 7 is Reserved (for future Opcode expansion) */
379 F(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
380 /** @} */
381
382 #define REG_TYPE(reg) \
383 static inline void \
384 brw_inst_set_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
385 brw_inst *inst, enum brw_reg_type type) \
386 { \
387 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
388 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
389 } \
390 \
391 static inline enum brw_reg_type \
392 brw_inst_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
393 const brw_inst *inst) \
394 { \
395 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
396 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
397 }
398
REG_TYPE(dst)399 REG_TYPE(dst)
400 REG_TYPE(src)
401 #undef REG_TYPE
402
403 /**
404 * Three-source align1 instructions:
405 * @{
406 */
407 /* Reserved 127:126 */
408 /* src2_reg_nr same in align16 */
409 FC(3src_a1_src2_subreg_nr, /* 4+ */ 117, 113, /* 12+ */ 119, 115, devinfo->ver >= 10)
410 FC(3src_a1_src2_hstride, /* 4+ */ 112, 111, /* 12+ */ 113, 112, devinfo->ver >= 10)
411 /* Reserved 110:109. src2 vstride is an implied parameter */
412 FC(3src_a1_src2_hw_type, /* 4+ */ 108, 106, /* 12+ */ 82, 80, devinfo->ver >= 10)
413 /* Reserved 105 */
414 /* src1_reg_nr same in align16 */
415 FC(3src_a1_src1_subreg_nr, /* 4+ */ 96, 92, /* 12+ */ 103, 99, devinfo->ver >= 10)
416 FC(3src_a1_src1_hstride, /* 4+ */ 91, 90, /* 12+ */ 97, 96, devinfo->ver >= 10)
417 FDC(3src_a1_src1_vstride, /* 4+ */ 89, 88, /* 12+ */ 91, 91, 83, 83, devinfo->ver >= 10)
418 FC(3src_a1_src1_hw_type, /* 4+ */ 87, 85, /* 12+ */ 90, 88, devinfo->ver >= 10)
419 /* Reserved 84 */
420 /* src0_reg_nr same in align16 */
421 FC(3src_a1_src0_subreg_nr, /* 4+ */ 75, 71, /* 12+ */ 71, 67, devinfo->ver >= 10)
422 FC(3src_a1_src0_hstride, /* 4+ */ 70, 69, /* 12+ */ 65, 64, devinfo->ver >= 10)
423 FDC(3src_a1_src0_vstride, /* 4+ */ 68, 67, /* 12+ */ 43, 43, 35, 35, devinfo->ver >= 10)
424 FC(3src_a1_src0_hw_type, /* 4+ */ 66, 64, /* 12+ */ 42, 40, devinfo->ver >= 10)
425 /* dst_reg_nr same in align16 */
426 FC(3src_a1_dst_subreg_nr, /* 4+ */ 55, 54, /* 12+ */ 55, 54, devinfo->ver >= 10)
427 FC(3src_a1_special_acc, /* 4+ */ 55, 52, /* 12+ */ 54, 51, devinfo->ver >= 10) /* aliases dst_subreg_nr */
428 /* Reserved 51:50 */
429 FC(3src_a1_dst_hstride, /* 4+ */ 49, 49, /* 12+ */ 48, 48, devinfo->ver >= 10)
430 FC(3src_a1_dst_hw_type, /* 4+ */ 48, 46, /* 12+ */ 38, 36, devinfo->ver >= 10)
431 FI(3src_a1_src2_reg_file, /* 4+ */ -1, -1, /* 8+ */ 45, 45, /* 12+ */ 47, 114)
432 FC(3src_a1_src1_reg_file, /* 4+ */ 44, 44, /* 12+ */ 98, 98, devinfo->ver >= 10)
433 FI(3src_a1_src0_reg_file, /* 4+ */ -1, -1, /* 8+ */ 43, 43, /* 12+ */ 46, 66)
434
435 F(3src_a1_src2_is_imm, /* 4+ */ -1, -1, /* 12+ */ 47, 47)
436 F(3src_a1_src0_is_imm, /* 4+ */ -1, -1, /* 12+ */ 46, 46)
437
438 /* Source Modifier fields same in align16 */
439 FC(3src_a1_dst_reg_file, /* 4+ */ 36, 36, /* 12+ */ 50, 50, devinfo->ver >= 10)
440 FC(3src_a1_exec_type, /* 4+ */ 35, 35, /* 12+ */ 39, 39, devinfo->ver >= 10)
441 /* Fields below this same in align16 */
442 /** @} */
443
444 #define REG_TYPE(reg) \
445 static inline void \
446 brw_inst_set_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
447 brw_inst *inst, enum brw_reg_type type) \
448 { \
449 UNUSED enum gfx10_align1_3src_exec_type exec_type = \
450 (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
451 inst); \
452 if (brw_reg_type_is_floating_point(type)) { \
453 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
454 } else { \
455 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
456 } \
457 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
458 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
459 } \
460 \
461 static inline enum brw_reg_type \
462 brw_inst_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
463 const brw_inst *inst) \
464 { \
465 enum gfx10_align1_3src_exec_type exec_type = \
466 (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
467 inst); \
468 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
469 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
470 }
471
472 REG_TYPE(dst)
473 REG_TYPE(src0)
474 REG_TYPE(src1)
475 REG_TYPE(src2)
476 #undef REG_TYPE
477
478 /**
479 * Three-source align1 instruction immediates:
480 * @{
481 */
482 static inline uint16_t
483 brw_inst_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
484 const brw_inst *insn)
485 {
486 assert(devinfo->ver >= 10);
487 if (devinfo->ver >= 12)
488 return brw_inst_bits(insn, 79, 64);
489 else
490 return brw_inst_bits(insn, 82, 67);
491 }
492
493 static inline uint16_t
brw_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info * devinfo,const brw_inst * insn)494 brw_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
495 const brw_inst *insn)
496 {
497 assert(devinfo->ver >= 10);
498 if (devinfo->ver >= 12)
499 return brw_inst_bits(insn, 127, 112);
500 else
501 return brw_inst_bits(insn, 124, 109);
502 }
503
504 static inline void
brw_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info * devinfo,brw_inst * insn,uint16_t value)505 brw_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
506 brw_inst *insn, uint16_t value)
507 {
508 assert(devinfo->ver >= 10);
509 if (devinfo->ver >= 12)
510 brw_inst_set_bits(insn, 79, 64, value);
511 else
512 brw_inst_set_bits(insn, 82, 67, value);
513 }
514
515 static inline void
brw_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info * devinfo,brw_inst * insn,uint16_t value)516 brw_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
517 brw_inst *insn, uint16_t value)
518 {
519 assert(devinfo->ver >= 10);
520 if (devinfo->ver >= 12)
521 brw_inst_set_bits(insn, 127, 112, value);
522 else
523 brw_inst_set_bits(insn, 124, 109, value);
524 }
525 /** @} */
526
527 /**
528 * Flow control instruction bits:
529 * @{
530 */
531 static inline void
brw_inst_set_uip(const struct intel_device_info * devinfo,brw_inst * inst,int32_t value)532 brw_inst_set_uip(const struct intel_device_info *devinfo,
533 brw_inst *inst, int32_t value)
534 {
535 assert(devinfo->ver >= 6);
536
537 if (devinfo->ver >= 12)
538 brw_inst_set_src1_is_imm(devinfo, inst, 1);
539
540 if (devinfo->ver >= 8) {
541 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
542 } else {
543 assert(value <= (1 << 16) - 1);
544 assert(value > -(1 << 16));
545 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
546 }
547 }
548
549 static inline int32_t
brw_inst_uip(const struct intel_device_info * devinfo,const brw_inst * inst)550 brw_inst_uip(const struct intel_device_info *devinfo, const brw_inst *inst)
551 {
552 assert(devinfo->ver >= 6);
553
554 if (devinfo->ver >= 8) {
555 return brw_inst_bits(inst, 95, 64);
556 } else {
557 return (int16_t)brw_inst_bits(inst, 127, 112);
558 }
559 }
560
561 static inline void
brw_inst_set_jip(const struct intel_device_info * devinfo,brw_inst * inst,int32_t value)562 brw_inst_set_jip(const struct intel_device_info *devinfo,
563 brw_inst *inst, int32_t value)
564 {
565 assert(devinfo->ver >= 6);
566
567 if (devinfo->ver >= 12)
568 brw_inst_set_src0_is_imm(devinfo, inst, 1);
569
570 if (devinfo->ver >= 8) {
571 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
572 } else {
573 assert(value <= (1 << 15) - 1);
574 assert(value >= -(1 << 15));
575 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
576 }
577 }
578
579 static inline int32_t
brw_inst_jip(const struct intel_device_info * devinfo,const brw_inst * inst)580 brw_inst_jip(const struct intel_device_info *devinfo, const brw_inst *inst)
581 {
582 assert(devinfo->ver >= 6);
583
584 if (devinfo->ver >= 8) {
585 return brw_inst_bits(inst, 127, 96);
586 } else {
587 return (int16_t)brw_inst_bits(inst, 111, 96);
588 }
589 }
590
591 /** Like FC, but using int16_t to handle negative jump targets. */
592 #define FJ(name, high, low, assertions) \
593 static inline void \
594 brw_inst_set_##name(const struct intel_device_info *devinfo, brw_inst *inst, int16_t v) \
595 { \
596 assert(assertions); \
597 (void) devinfo; \
598 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
599 } \
600 static inline int16_t \
601 brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\
602 { \
603 assert(assertions); \
604 (void) devinfo; \
605 return brw_inst_bits(inst, high, low); \
606 }
607
608 FJ(gfx6_jump_count, 63, 48, devinfo->ver == 6)
609 FJ(gfx4_jump_count, 111, 96, devinfo->ver < 6)
610 FC(gfx4_pop_count, /* 4+ */ 115, 112, /* 12+ */ -1, -1, devinfo->ver < 6)
611 /** @} */
612
613 /**
614 * SEND instructions:
615 * @{
616 */
617 FC(send_ex_desc_ia_subreg_nr, /* 4+ */ 82, 80, /* 12+ */ 42, 40, devinfo->ver >= 9)
618 FC(send_src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ -1, -1, devinfo->ver >= 9)
619 FC(send_sel_reg32_desc, /* 4+ */ 77, 77, /* 12+ */ 48, 48, devinfo->ver >= 9)
620 FC(send_sel_reg32_ex_desc, /* 4+ */ 61, 61, /* 12+ */ 49, 49, devinfo->ver >= 9)
621 F8(send_src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 66, 66)
622 FC(send_src1_reg_nr, /* 4+ */ 51, 44, /* 12+ */ 111, 104, devinfo->ver >= 9)
623 FC(send_src1_reg_file, /* 4+ */ 36, 36, /* 12+ */ 98, 98, devinfo->ver >= 9)
624 FC(send_dst_reg_file, /* 4+ */ 35, 35, /* 12+ */ 50, 50, devinfo->ver >= 9)
625 /** @} */
626
627 /* Message descriptor bits */
628 #define MD(x) ((x) + 96)
629 #define MD12(x) ((x) >= 30 ? (x) - 30 + 122 : \
630 (x) >= 25 ? (x) - 25 + 67 : \
631 (x) >= 20 ? (x) - 20 + 51 : \
632 (x) >= 11 ? (x) - 11 + 113 : \
633 (x) - 0 + 81)
634
635 /**
636 * Set the SEND(C) message descriptor immediate.
637 *
638 * This doesn't include the SFID nor the EOT field that were considered to be
639 * part of the message descriptor by ancient versions of the BSpec, because
640 * they are present in the instruction even if the message descriptor is
641 * provided indirectly in the address register, so we want to specify them
642 * separately.
643 */
644 static inline void
brw_inst_set_send_desc(const struct intel_device_info * devinfo,brw_inst * inst,uint32_t value)645 brw_inst_set_send_desc(const struct intel_device_info *devinfo,
646 brw_inst *inst, uint32_t value)
647 {
648 if (devinfo->ver >= 12) {
649 brw_inst_set_bits(inst, 123, 122, GET_BITS(value, 31, 30));
650 brw_inst_set_bits(inst, 71, 67, GET_BITS(value, 29, 25));
651 brw_inst_set_bits(inst, 55, 51, GET_BITS(value, 24, 20));
652 brw_inst_set_bits(inst, 121, 113, GET_BITS(value, 19, 11));
653 brw_inst_set_bits(inst, 91, 81, GET_BITS(value, 10, 0));
654 } else if (devinfo->ver >= 9) {
655 brw_inst_set_bits(inst, 126, 96, value);
656 assert(value >> 31 == 0);
657 } else if (devinfo->ver >= 5) {
658 brw_inst_set_bits(inst, 124, 96, value);
659 assert(value >> 29 == 0);
660 } else {
661 brw_inst_set_bits(inst, 119, 96, value);
662 assert(value >> 24 == 0);
663 }
664 }
665
666 /**
667 * Get the SEND(C) message descriptor immediate.
668 *
669 * \sa brw_inst_set_send_desc().
670 */
671 static inline uint32_t
brw_inst_send_desc(const struct intel_device_info * devinfo,const brw_inst * inst)672 brw_inst_send_desc(const struct intel_device_info *devinfo,
673 const brw_inst *inst)
674 {
675 if (devinfo->ver >= 12) {
676 return (brw_inst_bits(inst, 123, 122) << 30 |
677 brw_inst_bits(inst, 71, 67) << 25 |
678 brw_inst_bits(inst, 55, 51) << 20 |
679 brw_inst_bits(inst, 121, 113) << 11 |
680 brw_inst_bits(inst, 91, 81));
681 } else if (devinfo->ver >= 9) {
682 return brw_inst_bits(inst, 126, 96);
683 } else if (devinfo->ver >= 5) {
684 return brw_inst_bits(inst, 124, 96);
685 } else {
686 return brw_inst_bits(inst, 119, 96);
687 }
688 }
689
690 /**
691 * Set the SEND(C) message extended descriptor immediate.
692 *
693 * This doesn't include the SFID nor the EOT field that were considered to be
694 * part of the extended message descriptor by some versions of the BSpec,
695 * because they are present in the instruction even if the extended message
696 * descriptor is provided indirectly in a register, so we want to specify them
697 * separately.
698 */
699 static inline void
brw_inst_set_send_ex_desc(const struct intel_device_info * devinfo,brw_inst * inst,uint32_t value)700 brw_inst_set_send_ex_desc(const struct intel_device_info *devinfo,
701 brw_inst *inst, uint32_t value)
702 {
703 if (devinfo->ver >= 12) {
704 brw_inst_set_bits(inst, 127, 124, GET_BITS(value, 31, 28));
705 brw_inst_set_bits(inst, 97, 96, GET_BITS(value, 27, 26));
706 brw_inst_set_bits(inst, 65, 64, GET_BITS(value, 25, 24));
707 brw_inst_set_bits(inst, 47, 35, GET_BITS(value, 23, 11));
708 brw_inst_set_bits(inst, 103, 99, GET_BITS(value, 10, 6));
709 assert(GET_BITS(value, 5, 0) == 0);
710 } else {
711 assert(devinfo->ver >= 9);
712 brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28));
713 brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24));
714 brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20));
715 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16));
716 assert(GET_BITS(value, 15, 0) == 0);
717 }
718 }
719
720 /**
721 * Set the SENDS(C) message extended descriptor immediate.
722 *
723 * This doesn't include the SFID nor the EOT field that were considered to be
724 * part of the extended message descriptor by some versions of the BSpec,
725 * because they are present in the instruction even if the extended message
726 * descriptor is provided indirectly in a register, so we want to specify them
727 * separately.
728 */
729 static inline void
brw_inst_set_sends_ex_desc(const struct intel_device_info * devinfo,brw_inst * inst,uint32_t value)730 brw_inst_set_sends_ex_desc(const struct intel_device_info *devinfo,
731 brw_inst *inst, uint32_t value)
732 {
733 if (devinfo->ver >= 12) {
734 brw_inst_set_send_ex_desc(devinfo, inst, value);
735 } else {
736 brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16));
737 assert(GET_BITS(value, 15, 10) == 0);
738 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6));
739 assert(GET_BITS(value, 5, 0) == 0);
740 }
741 }
742
743 /**
744 * Get the SEND(C) message extended descriptor immediate.
745 *
746 * \sa brw_inst_set_send_ex_desc().
747 */
748 static inline uint32_t
brw_inst_send_ex_desc(const struct intel_device_info * devinfo,const brw_inst * inst)749 brw_inst_send_ex_desc(const struct intel_device_info *devinfo,
750 const brw_inst *inst)
751 {
752 if (devinfo->ver >= 12) {
753 return (brw_inst_bits(inst, 127, 124) << 28 |
754 brw_inst_bits(inst, 97, 96) << 26 |
755 brw_inst_bits(inst, 65, 64) << 24 |
756 brw_inst_bits(inst, 47, 35) << 11 |
757 brw_inst_bits(inst, 103, 99) << 6);
758 } else {
759 assert(devinfo->ver >= 9);
760 return (brw_inst_bits(inst, 94, 91) << 28 |
761 brw_inst_bits(inst, 88, 85) << 24 |
762 brw_inst_bits(inst, 83, 80) << 20 |
763 brw_inst_bits(inst, 67, 64) << 16);
764 }
765 }
766
767 /**
768 * Get the SENDS(C) message extended descriptor immediate.
769 *
770 * \sa brw_inst_set_send_ex_desc().
771 */
772 static inline uint32_t
brw_inst_sends_ex_desc(const struct intel_device_info * devinfo,const brw_inst * inst)773 brw_inst_sends_ex_desc(const struct intel_device_info *devinfo,
774 const brw_inst *inst)
775 {
776 if (devinfo->ver >= 12) {
777 return brw_inst_send_ex_desc(devinfo, inst);
778 } else {
779 return (brw_inst_bits(inst, 95, 80) << 16 |
780 brw_inst_bits(inst, 67, 64) << 6);
781 }
782 }
783
784 /**
785 * Fields for SEND messages:
786 * @{
787 */
788 F(eot, /* 4+ */ 127, 127, /* 12+ */ 34, 34)
789 FF(mlen,
790 /* 4: */ 119, 116,
791 /* 4.5: */ 119, 116,
792 /* 5: */ 124, 121,
793 /* 6: */ 124, 121,
794 /* 7: */ 124, 121,
795 /* 8: */ 124, 121,
796 /* 12: */ MD12(28), MD12(25));
797 FF(rlen,
798 /* 4: */ 115, 112,
799 /* 4.5: */ 115, 112,
800 /* 5: */ 120, 116,
801 /* 6: */ 120, 116,
802 /* 7: */ 120, 116,
803 /* 8: */ 120, 116,
804 /* 12: */ MD12(24), MD12(20));
805 FF(header_present,
806 /* 4: doesn't exist */ -1, -1, -1, -1,
807 /* 5: */ 115, 115,
808 /* 6: */ 115, 115,
809 /* 7: */ 115, 115,
810 /* 8: */ 115, 115,
811 /* 12: */ MD12(19), MD12(19))
812 F(gateway_notify, /* 4+ */ MD(16), MD(15), /* 12+ */ -1, -1)
813 FD(function_control,
814 /* 4: */ 111, 96,
815 /* 4.5: */ 111, 96,
816 /* 5: */ 114, 96,
817 /* 6: */ 114, 96,
818 /* 7: */ 114, 96,
819 /* 8: */ 114, 96,
820 /* 12: */ MD12(18), MD12(11), MD12(10), MD12(0))
821 FF(gateway_subfuncid,
822 /* 4: */ MD(1), MD(0),
823 /* 4.5: */ MD(1), MD(0),
824 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
825 /* 6: */ MD(2), MD(0),
826 /* 7: */ MD(2), MD(0),
827 /* 8: */ MD(2), MD(0),
828 /* 12: */ MD12(2), MD12(0))
829 FF(sfid,
830 /* 4: */ 123, 120, /* called msg_target */
831 /* 4.5 */ 123, 120,
832 /* 5: */ 95, 92,
833 /* 6: */ 27, 24,
834 /* 7: */ 27, 24,
835 /* 8: */ 27, 24,
836 /* 12: */ 95, 92)
837 FF(null_rt,
838 /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
839 /* 8: */ 80, 80,
840 /* 12: */ 44, 44) /* actually only Gfx11+ */
841 FC(base_mrf, /* 4+ */ 27, 24, /* 12+ */ -1, -1, devinfo->ver < 6);
842 FF(send_rta_index,
843 /* 4: */ -1, -1,
844 /* 4.5 */ -1, -1,
845 /* 5: */ -1, -1,
846 /* 6: */ -1, -1,
847 /* 7: */ -1, -1,
848 /* 8: */ -1, -1,
849 /* 12: */ 38, 36)
850 /** @} */
851
852 /**
853 * URB message function control bits:
854 * @{
855 */
856 FF(urb_per_slot_offset,
857 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
858 /* 7: */ MD(16), MD(16),
859 /* 8: */ MD(17), MD(17),
860 /* 12: */ MD12(17), MD12(17))
861 FC(urb_channel_mask_present, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15), devinfo->ver >= 8)
862 FC(urb_complete, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->ver < 8)
863 FC(urb_used, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1, devinfo->ver < 7)
864 FC(urb_allocate, /* 4+ */ MD(13), MD(13), /* 12+ */ -1, -1, devinfo->ver < 7)
865 FF(urb_swizzle_control,
866 /* 4: */ MD(11), MD(10),
867 /* 4.5: */ MD(11), MD(10),
868 /* 5: */ MD(11), MD(10),
869 /* 6: */ MD(11), MD(10),
870 /* 7: */ MD(14), MD(14),
871 /* 8: */ MD(15), MD(15),
872 /* 12: */ -1, -1)
873 FD(urb_global_offset,
874 /* 4: */ MD( 9), MD(4),
875 /* 4.5: */ MD( 9), MD(4),
876 /* 5: */ MD( 9), MD(4),
877 /* 6: */ MD( 9), MD(4),
878 /* 7: */ MD(13), MD(3),
879 /* 8: */ MD(14), MD(4),
880 /* 12: */ MD12(14), MD12(11), MD12(10), MD12(4))
881 FF(urb_opcode,
882 /* 4: */ MD( 3), MD(0),
883 /* 4.5: */ MD( 3), MD(0),
884 /* 5: */ MD( 3), MD(0),
885 /* 6: */ MD( 3), MD(0),
886 /* 7: */ MD( 2), MD(0),
887 /* 8: */ MD( 3), MD(0),
888 /* 12: */ MD12(3), MD12(0))
889 /** @} */
890
891 /**
892 * Gfx4-5 math messages:
893 * @{
894 */
895 FC(math_msg_data_type, /* 4+ */ MD(7), MD(7), /* 12+ */ -1, -1, devinfo->ver < 6)
896 FC(math_msg_saturate, /* 4+ */ MD(6), MD(6), /* 12+ */ -1, -1, devinfo->ver < 6)
897 FC(math_msg_precision, /* 4+ */ MD(5), MD(5), /* 12+ */ -1, -1, devinfo->ver < 6)
898 FC(math_msg_signed_int, /* 4+ */ MD(4), MD(4), /* 12+ */ -1, -1, devinfo->ver < 6)
899 FC(math_msg_function, /* 4+ */ MD(3), MD(0), /* 12+ */ -1, -1, devinfo->ver < 6)
900 /** @} */
901
902 /**
903 * Sampler message function control bits:
904 * @{
905 */
906 FF(sampler_simd_mode,
907 /* 4: doesn't exist */ -1, -1, -1, -1,
908 /* 5: */ MD(17), MD(16),
909 /* 6: */ MD(17), MD(16),
910 /* 7: */ MD(18), MD(17),
911 /* 8: */ MD(18), MD(17),
912 /* 12: */ MD12(18), MD12(17))
913 FF(sampler_msg_type,
914 /* 4: */ MD(15), MD(14),
915 /* 4.5: */ MD(15), MD(12),
916 /* 5: */ MD(15), MD(12),
917 /* 6: */ MD(15), MD(12),
918 /* 7: */ MD(16), MD(12),
919 /* 8: */ MD(16), MD(12),
920 /* 12: */ MD12(16), MD12(12))
921 FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->verx10 == 40)
922 FD(sampler,
923 /* 4: */ MD(11), MD(8),
924 /* 4.5: */ MD(11), MD(8),
925 /* 5: */ MD(11), MD(8),
926 /* 6: */ MD(11), MD(8),
927 /* 7: */ MD(11), MD(8),
928 /* 8: */ MD(11), MD(8),
929 /* 12: */ MD12(11), MD12(11), MD12(10), MD12(8))
930 F(binding_table_index, /* 4+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0)) /* also used by other messages */
931 /** @} */
932
933 /**
934 * Data port message function control bits:
935 * @{
936 */
937 FC(dp_category, /* 4+ */ MD(18), MD(18), /* 12+ */ MD12(18), MD12(18), devinfo->ver >= 7)
938
939 /* Gfx4-5 store fields in different bits for read/write messages. */
940 FF(dp_read_msg_type,
941 /* 4: */ MD(13), MD(12),
942 /* 4.5: */ MD(13), MD(11),
943 /* 5: */ MD(13), MD(11),
944 /* 6: */ MD(16), MD(13),
945 /* 7: */ MD(17), MD(14),
946 /* 8: */ MD(17), MD(14),
947 /* 12: */ MD12(17), MD12(14))
948 FF(dp_write_msg_type,
949 /* 4: */ MD(14), MD(12),
950 /* 4.5: */ MD(14), MD(12),
951 /* 5: */ MD(14), MD(12),
952 /* 6: */ MD(16), MD(13),
953 /* 7: */ MD(17), MD(14),
954 /* 8: */ MD(17), MD(14),
955 /* 12: */ MD12(17), MD12(14))
956 FD(dp_read_msg_control,
957 /* 4: */ MD(11), MD( 8),
958 /* 4.5: */ MD(10), MD( 8),
959 /* 5: */ MD(10), MD( 8),
960 /* 6: */ MD(12), MD( 8),
961 /* 7: */ MD(13), MD( 8),
962 /* 8: */ MD(13), MD( 8),
963 /* 12: */ MD12(13), MD12(11), MD12(10), MD12(8))
964 FD(dp_write_msg_control,
965 /* 4: */ MD(11), MD( 8),
966 /* 4.5: */ MD(11), MD( 8),
967 /* 5: */ MD(11), MD( 8),
968 /* 6: */ MD(12), MD( 8),
969 /* 7: */ MD(13), MD( 8),
970 /* 8: */ MD(13), MD( 8),
971 /* 12: */ MD12(13), MD12(11), MD12(10), MD12(8))
972 FC(dp_read_target_cache, /* 4+ */ MD(15), MD(14), /* 12+ */ -1, -1, devinfo->ver < 6);
973
974 FF(dp_write_commit,
975 /* 4: */ MD(15), MD(15),
976 /* 4.5: */ MD(15), MD(15),
977 /* 5: */ MD(15), MD(15),
978 /* 6: */ MD(17), MD(17),
979 /* 7+: does not exist */ -1, -1, -1, -1,
980 /* 12: */ -1, -1)
981
982 /* Gfx6+ use the same bit locations for everything. */
983 FF(dp_msg_type,
984 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
985 -1, -1, -1, -1, -1, -1,
986 /* 6: */ MD(16), MD(13),
987 /* 7: */ MD(17), MD(14),
988 /* 8: */ MD(18), MD(14),
989 /* 12: */ MD12(18), MD12(14))
990 FD(dp_msg_control,
991 /* 4: */ MD(11), MD( 8),
992 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
993 /* 6: */ MD(12), MD( 8),
994 /* 7: */ MD(13), MD( 8),
995 /* 8: */ MD(13), MD( 8),
996 /* 12: */ MD12(13), MD12(11), MD12(10), MD12(8))
997 /** @} */
998
999 /**
1000 * Scratch message bits (Gfx7+):
1001 * @{
1002 */
1003 FC(scratch_read_write, /* 4+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17), devinfo->ver >= 7) /* 0 = read, 1 = write */
1004 FC(scratch_type, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1, devinfo->ver >= 7) /* 0 = OWord, 1 = DWord */
1005 FC(scratch_invalidate_after_read, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15), devinfo->ver >= 7)
1006 FC(scratch_block_size, /* 4+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12), devinfo->ver >= 7)
1007 FD(scratch_addr_offset,
1008 /* 4: */ -1, -1,
1009 /* 4.5: */ -1, -1,
1010 /* 5: */ -1, -1,
1011 /* 6: */ -1, -1,
1012 /* 7: */ MD(11), MD(0),
1013 /* 8: */ MD(11), MD(0),
1014 /* 12: */ MD12(11), MD12(11), MD12(10), MD12(0))
1015 /** @} */
1016
1017 /**
1018 * Render Target message function control bits:
1019 * @{
1020 */
1021 FF(rt_last,
1022 /* 4: */ MD(11), MD(11),
1023 /* 4.5: */ MD(11), MD(11),
1024 /* 5: */ MD(11), MD(11),
1025 /* 6: */ MD(12), MD(12),
1026 /* 7: */ MD(12), MD(12),
1027 /* 8: */ MD(12), MD(12),
1028 /* 12: */ MD12(12), MD12(12))
1029 FC(rt_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11), devinfo->ver >= 6)
1030 F(rt_message_type, /* 4+ */ MD(10), MD( 8), /* 12+ */ MD12(10), MD12(8))
1031 /** @} */
1032
1033 /**
1034 * Thread Spawn message function control bits:
1035 * @{
1036 */
1037 FC(ts_resource_select, /* 4+ */ MD( 4), MD( 4), /* 12+ */ -1, -1, devinfo->ver < 11)
1038 FC(ts_request_type, /* 4+ */ MD( 1), MD( 1), /* 12+ */ -1, -1, devinfo->ver < 11)
1039 F(ts_opcode, /* 4+ */ MD( 0), MD( 0), /* 12+ */ MD12(0), MD12(0))
1040 /** @} */
1041
1042 /**
1043 * Pixel Interpolator message function control bits:
1044 * @{
1045 */
1046 F(pi_simd_mode, /* 4+ */ MD(16), MD(16), /* 12+ */ MD12(16), MD12(16))
1047 F(pi_nopersp, /* 4+ */ MD(14), MD(14), /* 12+ */ MD12(14), MD12(14))
1048 F(pi_message_type, /* 4+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12))
1049 F(pi_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11))
1050 F(pi_message_data, /* 4+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0))
1051 /** @} */
1052
1053 /**
1054 * Immediates:
1055 * @{
1056 */
1057 static inline int
brw_inst_imm_d(const struct intel_device_info * devinfo,const brw_inst * insn)1058 brw_inst_imm_d(const struct intel_device_info *devinfo, const brw_inst *insn)
1059 {
1060 (void) devinfo;
1061 return brw_inst_bits(insn, 127, 96);
1062 }
1063
1064 static inline unsigned
brw_inst_imm_ud(const struct intel_device_info * devinfo,const brw_inst * insn)1065 brw_inst_imm_ud(const struct intel_device_info *devinfo, const brw_inst *insn)
1066 {
1067 (void) devinfo;
1068 return brw_inst_bits(insn, 127, 96);
1069 }
1070
1071 static inline uint64_t
brw_inst_imm_uq(ASSERTED const struct intel_device_info * devinfo,const brw_inst * insn)1072 brw_inst_imm_uq(ASSERTED const struct intel_device_info *devinfo,
1073 const brw_inst *insn)
1074 {
1075 assert(devinfo->ver >= 8);
1076 return brw_inst_bits(insn, 127, 64);
1077 }
1078
1079 static inline float
brw_inst_imm_f(const struct intel_device_info * devinfo,const brw_inst * insn)1080 brw_inst_imm_f(const struct intel_device_info *devinfo, const brw_inst *insn)
1081 {
1082 union {
1083 float f;
1084 uint32_t u;
1085 } ft;
1086 (void) devinfo;
1087 ft.u = brw_inst_bits(insn, 127, 96);
1088 return ft.f;
1089 }
1090
1091 static inline double
brw_inst_imm_df(const struct intel_device_info * devinfo,const brw_inst * insn)1092 brw_inst_imm_df(const struct intel_device_info *devinfo, const brw_inst *insn)
1093 {
1094 union {
1095 double d;
1096 uint64_t u;
1097 } dt;
1098 (void) devinfo;
1099 dt.u = brw_inst_bits(insn, 127, 64);
1100 return dt.d;
1101 }
1102
1103 static inline void
brw_inst_set_imm_d(const struct intel_device_info * devinfo,brw_inst * insn,int value)1104 brw_inst_set_imm_d(const struct intel_device_info *devinfo,
1105 brw_inst *insn, int value)
1106 {
1107 (void) devinfo;
1108 return brw_inst_set_bits(insn, 127, 96, value);
1109 }
1110
1111 static inline void
brw_inst_set_imm_ud(const struct intel_device_info * devinfo,brw_inst * insn,unsigned value)1112 brw_inst_set_imm_ud(const struct intel_device_info *devinfo,
1113 brw_inst *insn, unsigned value)
1114 {
1115 (void) devinfo;
1116 return brw_inst_set_bits(insn, 127, 96, value);
1117 }
1118
1119 static inline void
brw_inst_set_imm_f(const struct intel_device_info * devinfo,brw_inst * insn,float value)1120 brw_inst_set_imm_f(const struct intel_device_info *devinfo,
1121 brw_inst *insn, float value)
1122 {
1123 union {
1124 float f;
1125 uint32_t u;
1126 } ft;
1127 (void) devinfo;
1128 ft.f = value;
1129 brw_inst_set_bits(insn, 127, 96, ft.u);
1130 }
1131
1132 static inline void
brw_inst_set_imm_df(const struct intel_device_info * devinfo,brw_inst * insn,double value)1133 brw_inst_set_imm_df(const struct intel_device_info *devinfo,
1134 brw_inst *insn, double value)
1135 {
1136 union {
1137 double d;
1138 uint64_t u;
1139 } dt;
1140 (void) devinfo;
1141 dt.d = value;
1142
1143 if (devinfo->ver >= 12) {
1144 brw_inst_set_bits(insn, 95, 64, dt.u >> 32);
1145 brw_inst_set_bits(insn, 127, 96, dt.u & 0xFFFFFFFF);
1146 } else {
1147 brw_inst_set_bits(insn, 127, 64, dt.u);
1148 }
1149 }
1150
1151 static inline void
brw_inst_set_imm_uq(const struct intel_device_info * devinfo,brw_inst * insn,uint64_t value)1152 brw_inst_set_imm_uq(const struct intel_device_info *devinfo,
1153 brw_inst *insn, uint64_t value)
1154 {
1155 (void) devinfo;
1156 if (devinfo->ver >= 12) {
1157 brw_inst_set_bits(insn, 95, 64, value >> 32);
1158 brw_inst_set_bits(insn, 127, 96, value & 0xFFFFFFFF);
1159 } else {
1160 brw_inst_set_bits(insn, 127, 64, value);
1161 }
1162 }
1163
1164 /** @} */
1165
1166 #define REG_TYPE(reg) \
1167 static inline void \
1168 brw_inst_set_##reg##_file_type(const struct intel_device_info *devinfo, \
1169 brw_inst *inst, enum brw_reg_file file, \
1170 enum brw_reg_type type) \
1171 { \
1172 assert(file <= BRW_IMMEDIATE_VALUE); \
1173 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
1174 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
1175 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
1176 } \
1177 \
1178 static inline enum brw_reg_type \
1179 brw_inst_##reg##_type(const struct intel_device_info *devinfo, \
1180 const brw_inst *inst) \
1181 { \
1182 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
1183 (unsigned) BRW_GENERAL_REGISTER_FILE : \
1184 brw_inst_##reg##_reg_file(devinfo, inst); \
1185 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
1186 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
1187 }
1188
1189 REG_TYPE(dst)
REG_TYPE(src0)1190 REG_TYPE(src0)
1191 REG_TYPE(src1)
1192 #undef REG_TYPE
1193
1194
1195 /* The AddrImm fields are split into two discontiguous sections on Gfx8+ */
1196 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low, \
1197 g12_high, g12_low) \
1198 static inline void \
1199 brw_inst_set_##reg##_ia1_addr_imm(const struct \
1200 intel_device_info *devinfo, \
1201 brw_inst *inst, \
1202 unsigned value) \
1203 { \
1204 assert((value & ~0x3ff) == 0); \
1205 if (devinfo->ver >= 12) { \
1206 brw_inst_set_bits(inst, g12_high, g12_low, value); \
1207 } else if (devinfo->ver >= 8) { \
1208 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
1209 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
1210 } else { \
1211 brw_inst_set_bits(inst, g4_high, g4_low, value); \
1212 } \
1213 } \
1214 static inline unsigned \
1215 brw_inst_##reg##_ia1_addr_imm(const struct intel_device_info *devinfo, \
1216 const brw_inst *inst) \
1217 { \
1218 if (devinfo->ver >= 12) { \
1219 return brw_inst_bits(inst, g12_high, g12_low); \
1220 } else if (devinfo->ver >= 8) { \
1221 return brw_inst_bits(inst, g8_high, g8_low) | \
1222 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
1223 } else { \
1224 return brw_inst_bits(inst, g4_high, g4_low); \
1225 } \
1226 }
1227
1228 /* AddrImm[9:0] for Align1 Indirect Addressing */
1229 /* -Gen 4- ----Gfx8---- -Gfx12- */
1230 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96, 107, 98)
1231 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64, 75, 66)
1232 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48, 59, 50)
1233
1234 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
1235 static inline void \
1236 brw_inst_set_##reg##_ia16_addr_imm(const struct \
1237 intel_device_info *devinfo, \
1238 brw_inst *inst, unsigned value) \
1239 { \
1240 assert(devinfo->ver < 12); \
1241 assert((value & ~0x3ff) == 0); \
1242 if (devinfo->ver >= 8) { \
1243 assert(GET_BITS(value, 3, 0) == 0); \
1244 brw_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \
1245 brw_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \
1246 } else { \
1247 brw_inst_set_bits(inst, g4_high, g4_low, value); \
1248 } \
1249 } \
1250 static inline unsigned \
1251 brw_inst_##reg##_ia16_addr_imm(const struct intel_device_info *devinfo, \
1252 const brw_inst *inst) \
1253 { \
1254 assert(devinfo->ver < 12); \
1255 if (devinfo->ver >= 8) { \
1256 return (brw_inst_bits(inst, g8_high, g8_low) << 4) | \
1257 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
1258 } else { \
1259 return brw_inst_bits(inst, g4_high, g4_low); \
1260 } \
1261 }
1262
1263 /* AddrImm[9:0] for Align16 Indirect Addressing:
1264 * Compared to Align1, these are missing the low 4 bits.
1265 * -Gen 4- ----Gfx8----
1266 */
1267 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
1268 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
1269 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
1270 BRW_IA16_ADDR_IMM(send_src0, -1, -1, 78, 72, 68)
1271 BRW_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52)
1272
1273 /**
1274 * Fetch a set of contiguous bits from the instruction.
1275 *
1276 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1277 */
1278 static inline uint64_t
1279 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
1280 {
1281 assume(high < 128);
1282 assume(high >= low);
1283 /* We assume the field doesn't cross 64-bit boundaries. */
1284 const unsigned word = high / 64;
1285 assert(word == low / 64);
1286
1287 high %= 64;
1288 low %= 64;
1289
1290 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
1291
1292 return (inst->data[word] >> low) & mask;
1293 }
1294
1295 /**
1296 * Set bits in the instruction, with proper shifting and masking.
1297 *
1298 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1299 */
1300 static inline void
brw_inst_set_bits(brw_inst * inst,unsigned high,unsigned low,uint64_t value)1301 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
1302 {
1303 assume(high < 128);
1304 assume(high >= low);
1305 const unsigned word = high / 64;
1306 assert(word == low / 64);
1307
1308 high %= 64;
1309 low %= 64;
1310
1311 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
1312
1313 /* Make sure the supplied value actually fits in the given bitfield. */
1314 assert((value & (mask >> low)) == value);
1315
1316 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
1317 }
1318
1319 #undef BRW_IA16_ADDR_IMM
1320 #undef BRW_IA1_ADDR_IMM
1321 #undef MD
1322 #undef F8
1323 #undef FF
1324 #undef BOUNDS
1325 #undef F
1326 #undef FC
1327
1328 typedef struct {
1329 uint64_t data;
1330 } brw_compact_inst;
1331
1332 /**
1333 * Fetch a set of contiguous bits from the compacted instruction.
1334 *
1335 * Bits indices range from 0..63.
1336 */
1337 static inline unsigned
brw_compact_inst_bits(const brw_compact_inst * inst,unsigned high,unsigned low)1338 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
1339 {
1340 const uint64_t mask = (1ull << (high - low + 1)) - 1;
1341
1342 return (inst->data >> low) & mask;
1343 }
1344
1345 /**
1346 * Set bits in the compacted instruction.
1347 *
1348 * Bits indices range from 0..63.
1349 */
1350 static inline void
brw_compact_inst_set_bits(brw_compact_inst * inst,unsigned high,unsigned low,uint64_t value)1351 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
1352 uint64_t value)
1353 {
1354 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
1355
1356 /* Make sure the supplied value actually fits in the given bitfield. */
1357 assert((value & (mask >> low)) == value);
1358
1359 inst->data = (inst->data & ~mask) | (value << low);
1360 }
1361
1362 #define FC(name, high, low, gfx12_high, gfx12_low, assertions) \
1363 static inline void \
1364 brw_compact_inst_set_##name(const struct \
1365 intel_device_info *devinfo, \
1366 brw_compact_inst *inst, unsigned v) \
1367 { \
1368 assert(assertions); \
1369 if (devinfo->ver >= 12) \
1370 brw_compact_inst_set_bits(inst, gfx12_high, gfx12_low, v); \
1371 else \
1372 brw_compact_inst_set_bits(inst, high, low, v); \
1373 } \
1374 static inline unsigned \
1375 brw_compact_inst_##name(const struct intel_device_info *devinfo, \
1376 const brw_compact_inst *inst) \
1377 { \
1378 assert(assertions); \
1379 if (devinfo->ver >= 12) \
1380 return brw_compact_inst_bits(inst, gfx12_high, gfx12_low); \
1381 else \
1382 return brw_compact_inst_bits(inst, high, low); \
1383 }
1384
1385 /* A simple macro for fields which stay in the same place on all generations
1386 * except for Gfx12.
1387 */
1388 #define F(name, high, low, gfx12_high, gfx12_low) \
1389 FC(name, high, low, gfx12_high, gfx12_low, true)
1390
1391 F(src1_reg_nr, /* 4+ */ 63, 56, /* 12+ */ 63, 56)
1392 F(src0_reg_nr, /* 4+ */ 55, 48, /* 12+ */ 47, 40)
1393 F(dst_reg_nr, /* 4+ */ 47, 40, /* 12+ */ 23, 16)
1394 F(src1_index, /* 4+ */ 39, 35, /* 12+ */ 55, 52)
1395 F(src0_index, /* 4+ */ 34, 30, /* 12+ */ 51, 48)
1396 F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) /* Same location as brw_inst */
1397 FC(flag_subreg_nr, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->ver <= 6)
1398 F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ -1, -1) /* Same location as brw_inst */
1399 FC(acc_wr_control, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->ver >= 6)
1400 FC(mask_control_ex, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->verx10 == 45 || devinfo->ver == 5)
1401 F(subreg_index, /* 4+ */ 22, 18, /* 12+ */ 39, 35)
1402 F(datatype_index, /* 4+ */ 17, 13, /* 12+ */ 34, 30)
1403 F(control_index, /* 4+ */ 12, 8, /* 12+ */ 28, 24)
1404 FC(swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8, devinfo->ver >= 12)
1405 F(debug_control, /* 4+ */ 7, 7, /* 12+ */ 7, 7)
1406 F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) /* Same location as brw_inst */
1407
1408 static inline unsigned
brw_compact_inst_imm(const struct intel_device_info * devinfo,const brw_compact_inst * inst)1409 brw_compact_inst_imm(const struct intel_device_info *devinfo,
1410 const brw_compact_inst *inst)
1411 {
1412 if (devinfo->ver >= 12) {
1413 return brw_compact_inst_bits(inst, 63, 52);
1414 } else {
1415 return (brw_compact_inst_bits(inst, 39, 35) << 8) |
1416 (brw_compact_inst_bits(inst, 63, 56));
1417 }
1418 }
1419
1420 /**
1421 * (Gfx8+) Compacted three-source instructions:
1422 * @{
1423 */
1424 FC(3src_src2_reg_nr, /* 4+ */ 63, 57, /* 12+ */ 55, 48, devinfo->ver >= 8)
1425 FC(3src_src1_reg_nr, /* 4+ */ 56, 50, /* 12+ */ 63, 56, devinfo->ver >= 8)
1426 FC(3src_src0_reg_nr, /* 4+ */ 49, 43, /* 12+ */ 47, 40, devinfo->ver >= 8)
1427 FC(3src_src2_subreg_nr, /* 4+ */ 42, 40, /* 12+ */ -1, -1, devinfo->ver >= 8)
1428 FC(3src_src1_subreg_nr, /* 4+ */ 39, 37, /* 12+ */ -1, -1, devinfo->ver >= 8)
1429 FC(3src_src0_subreg_nr, /* 4+ */ 36, 34, /* 12+ */ -1, -1, devinfo->ver >= 8)
1430 FC(3src_src2_rep_ctrl, /* 4+ */ 33, 33, /* 12+ */ -1, -1, devinfo->ver >= 8)
1431 FC(3src_src1_rep_ctrl, /* 4+ */ 32, 32, /* 12+ */ -1, -1, devinfo->ver >= 8)
1432 FC(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ -1, -1, devinfo->ver >= 8)
1433 FC(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 7, 7, devinfo->ver >= 8)
1434 FC(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29, devinfo->ver >= 8)
1435 FC(3src_src0_rep_ctrl, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->ver >= 8)
1436 /* Reserved */
1437 FC(3src_dst_reg_nr, /* 4+ */ 18, 12, /* 12+ */ 23, 16, devinfo->ver >= 8)
1438 FC(3src_source_index, /* 4+ */ 11, 10, /* 12+ */ 34, 30, devinfo->ver >= 8)
1439 FC(3src_subreg_index, /* 4+ */ -1, -1, /* 12+ */ 39, 35, devinfo->ver >= 12)
1440 FC(3src_control_index, /* 4+ */ 9, 8, /* 12+ */ 28, 24, devinfo->ver >= 8)
1441 FC(3src_swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8, devinfo->ver >= 8)
1442 /* Bit 7 is Reserved (for future Opcode expansion) */
1443 FC(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0, devinfo->ver >= 8)
1444 /** @} */
1445
1446 #undef F
1447
1448 static inline void
brw_inst_set_opcode(const struct brw_isa_info * isa,struct brw_inst * inst,enum opcode opcode)1449 brw_inst_set_opcode(const struct brw_isa_info *isa,
1450 struct brw_inst *inst, enum opcode opcode)
1451 {
1452 brw_inst_set_hw_opcode(isa->devinfo, inst, brw_opcode_encode(isa, opcode));
1453 }
1454
1455 static inline enum opcode
brw_inst_opcode(const struct brw_isa_info * isa,const struct brw_inst * inst)1456 brw_inst_opcode(const struct brw_isa_info *isa,
1457 const struct brw_inst *inst)
1458 {
1459 return brw_opcode_decode(isa, brw_inst_hw_opcode(isa->devinfo, inst));
1460 }
1461
1462 #ifdef __cplusplus
1463 }
1464 #endif
1465
1466 #endif
1467