1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * (C) Copyright 2020 Hewlett Packard Enterprise Development LP
9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
10 */
11 #include <linux/crash_dump.h>
12 #include <linux/cpuhotplug.h>
13 #include <linux/cpumask.h>
14 #include <linux/proc_fs.h>
15 #include <linux/memory.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/acpi.h>
19 #include <linux/efi.h>
20
21 #include <asm/e820/api.h>
22 #include <asm/uv/uv_mmrs.h>
23 #include <asm/uv/uv_hub.h>
24 #include <asm/uv/bios.h>
25 #include <asm/uv/uv.h>
26 #include <asm/apic.h>
27
28 static enum uv_system_type uv_system_type;
29 static int uv_hubbed_system;
30 static int uv_hubless_system;
31 static u64 gru_start_paddr, gru_end_paddr;
32 static union uvh_apicid uvh_apicid;
33 static int uv_node_id;
34
35 /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */
36 static u8 uv_archtype[UV_AT_SIZE + 1];
37 static u8 oem_id[ACPI_OEM_ID_SIZE + 1];
38 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
39
40 /* Information derived from CPUID and some UV MMRs */
41 static struct {
42 unsigned int apicid_shift;
43 unsigned int apicid_mask;
44 unsigned int socketid_shift; /* aka pnode_shift for UV2/3 */
45 unsigned int pnode_mask;
46 unsigned int nasid_shift;
47 unsigned int gpa_shift;
48 unsigned int gnode_shift;
49 unsigned int m_skt;
50 unsigned int n_skt;
51 } uv_cpuid;
52
53 static int uv_min_hub_revision_id;
54
55 static struct apic apic_x2apic_uv_x;
56 static struct uv_hub_info_s uv_hub_info_node0;
57
58 /* Set this to use hardware error handler instead of kernel panic: */
59 static int disable_uv_undefined_panic = 1;
60
uv_undefined(char * str)61 unsigned long uv_undefined(char *str)
62 {
63 if (likely(!disable_uv_undefined_panic))
64 panic("UV: error: undefined MMR: %s\n", str);
65 else
66 pr_crit("UV: error: undefined MMR: %s\n", str);
67
68 /* Cause a machine fault: */
69 return ~0ul;
70 }
71 EXPORT_SYMBOL(uv_undefined);
72
uv_early_read_mmr(unsigned long addr)73 static unsigned long __init uv_early_read_mmr(unsigned long addr)
74 {
75 unsigned long val, *mmr;
76
77 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
78 val = *mmr;
79 early_iounmap(mmr, sizeof(*mmr));
80
81 return val;
82 }
83
is_GRU_range(u64 start,u64 end)84 static inline bool is_GRU_range(u64 start, u64 end)
85 {
86 if (!gru_start_paddr)
87 return false;
88
89 return start >= gru_start_paddr && end <= gru_end_paddr;
90 }
91
uv_is_untracked_pat_range(u64 start,u64 end)92 static bool uv_is_untracked_pat_range(u64 start, u64 end)
93 {
94 return is_ISA_range(start, end) || is_GRU_range(start, end);
95 }
96
early_get_pnodeid(void)97 static void __init early_get_pnodeid(void)
98 {
99 int pnode;
100
101 uv_cpuid.m_skt = 0;
102 if (UVH_RH10_GAM_ADDR_MAP_CONFIG) {
103 union uvh_rh10_gam_addr_map_config_u m_n_config;
104
105 m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG);
106 uv_cpuid.n_skt = m_n_config.s.n_skt;
107 uv_cpuid.nasid_shift = 0;
108 } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) {
109 union uvh_rh_gam_addr_map_config_u m_n_config;
110
111 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG);
112 uv_cpuid.n_skt = m_n_config.s.n_skt;
113 if (is_uv(UV3))
114 uv_cpuid.m_skt = m_n_config.s3.m_skt;
115 if (is_uv(UV2))
116 uv_cpuid.m_skt = m_n_config.s2.m_skt;
117 uv_cpuid.nasid_shift = 1;
118 } else {
119 unsigned long GAM_ADDR_MAP_CONFIG = 0;
120
121 WARN(GAM_ADDR_MAP_CONFIG == 0,
122 "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n");
123 uv_cpuid.n_skt = 0;
124 uv_cpuid.nasid_shift = 0;
125 }
126
127 if (is_uv(UV4|UVY))
128 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
129
130 uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1;
131 pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask;
132 uv_cpuid.gpa_shift = 46; /* Default unless changed */
133
134 pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n",
135 uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode);
136 }
137
138 /* Running on a UV Hubbed system, determine which UV Hub Type it is */
early_set_hub_type(void)139 static int __init early_set_hub_type(void)
140 {
141 union uvh_node_id_u node_id;
142
143 /*
144 * The NODE_ID MMR is always at offset 0.
145 * Contains the chip part # + revision.
146 * Node_id field started with 15 bits,
147 * ... now 7 but upper 8 are masked to 0.
148 * All blades/nodes have the same part # and hub revision.
149 */
150 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
151 uv_node_id = node_id.sx.node_id;
152
153 switch (node_id.s.part_number) {
154
155 case UV5_HUB_PART_NUMBER:
156 uv_min_hub_revision_id = node_id.s.revision
157 + UV5_HUB_REVISION_BASE;
158 uv_hub_type_set(UV5);
159 break;
160
161 /* UV4/4A only have a revision difference */
162 case UV4_HUB_PART_NUMBER:
163 uv_min_hub_revision_id = node_id.s.revision
164 + UV4_HUB_REVISION_BASE - 1;
165 uv_hub_type_set(UV4);
166 if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE)
167 uv_hub_type_set(UV4|UV4A);
168 break;
169
170 case UV3_HUB_PART_NUMBER:
171 case UV3_HUB_PART_NUMBER_X:
172 uv_min_hub_revision_id = node_id.s.revision
173 + UV3_HUB_REVISION_BASE;
174 uv_hub_type_set(UV3);
175 break;
176
177 case UV2_HUB_PART_NUMBER:
178 case UV2_HUB_PART_NUMBER_X:
179 uv_min_hub_revision_id = node_id.s.revision
180 + UV2_HUB_REVISION_BASE - 1;
181 uv_hub_type_set(UV2);
182 break;
183
184 default:
185 return 0;
186 }
187
188 pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n",
189 node_id.s.part_number, node_id.s.revision,
190 uv_min_hub_revision_id, is_uv(~0));
191
192 return 1;
193 }
194
uv_tsc_check_sync(void)195 static void __init uv_tsc_check_sync(void)
196 {
197 u64 mmr;
198 int sync_state;
199 int mmr_shift;
200 char *state;
201
202 /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */
203 if (!is_uv(UV2|UV3|UV4)) {
204 mark_tsc_async_resets("UV5+");
205 return;
206 }
207
208 /* UV2,3,4, UV BIOS TSC sync state available */
209 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
210 mmr_shift =
211 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
212 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
213
214 /* Check if TSC is valid for all sockets */
215 switch (sync_state) {
216 case UVH_TSC_SYNC_VALID:
217 state = "in sync";
218 mark_tsc_async_resets("UV BIOS");
219 break;
220
221 /* If BIOS state unknown, don't do anything */
222 case UVH_TSC_SYNC_UNKNOWN:
223 state = "unknown";
224 break;
225
226 /* Otherwise, BIOS indicates problem with TSC */
227 default:
228 state = "unstable";
229 mark_tsc_unstable("UV BIOS");
230 break;
231 }
232 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
233 }
234
235 /* Selector for (4|4A|5) structs */
236 #define uvxy_field(sname, field, undef) ( \
237 is_uv(UV4A) ? sname.s4a.field : \
238 is_uv(UV4) ? sname.s4.field : \
239 is_uv(UV3) ? sname.s3.field : \
240 undef)
241
242 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
243
244 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */
245 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */
246 #define SMT_TYPE 1
247 #define CORE_TYPE 2
248 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
249 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
250
set_x2apic_bits(void)251 static void set_x2apic_bits(void)
252 {
253 unsigned int eax, ebx, ecx, edx, sub_index;
254 unsigned int sid_shift;
255
256 cpuid(0, &eax, &ebx, &ecx, &edx);
257 if (eax < 0xb) {
258 pr_info("UV: CPU does not have CPUID.11\n");
259 return;
260 }
261
262 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
263 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
264 pr_info("UV: CPUID.11 not implemented\n");
265 return;
266 }
267
268 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
269 sub_index = 1;
270 do {
271 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
272 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
273 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
274 break;
275 }
276 sub_index++;
277 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
278
279 uv_cpuid.apicid_shift = 0;
280 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
281 uv_cpuid.socketid_shift = sid_shift;
282 }
283
early_get_apic_socketid_shift(void)284 static void __init early_get_apic_socketid_shift(void)
285 {
286 if (is_uv2_hub() || is_uv3_hub())
287 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
288
289 set_x2apic_bits();
290
291 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
292 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
293 }
294
uv_stringify(int len,char * to,char * from)295 static void __init uv_stringify(int len, char *to, char *from)
296 {
297 /* Relies on 'to' being NULL chars so result will be NULL terminated */
298 strncpy(to, from, len-1);
299
300 /* Trim trailing spaces */
301 (void)strim(to);
302 }
303
304 /* Find UV arch type entry in UVsystab */
early_find_archtype(struct uv_systab * st)305 static unsigned long __init early_find_archtype(struct uv_systab *st)
306 {
307 int i;
308
309 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
310 unsigned long ptr = st->entry[i].offset;
311
312 if (!ptr)
313 continue;
314 ptr += (unsigned long)st;
315 if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE)
316 return ptr;
317 }
318 return 0;
319 }
320
321 /* Validate UV arch type field in UVsystab */
decode_arch_type(unsigned long ptr)322 static int __init decode_arch_type(unsigned long ptr)
323 {
324 struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr;
325 int n = strlen(uv_ate->archtype);
326
327 if (n > 0 && n < sizeof(uv_ate->archtype)) {
328 pr_info("UV: UVarchtype received from BIOS\n");
329 uv_stringify(sizeof(uv_archtype), uv_archtype, uv_ate->archtype);
330 return 1;
331 }
332 return 0;
333 }
334
335 /* Determine if UV arch type entry might exist in UVsystab */
early_get_arch_type(void)336 static int __init early_get_arch_type(void)
337 {
338 unsigned long uvst_physaddr, uvst_size, ptr;
339 struct uv_systab *st;
340 u32 rev;
341 int ret;
342
343 uvst_physaddr = get_uv_systab_phys(0);
344 if (!uvst_physaddr)
345 return 0;
346
347 st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab));
348 if (!st) {
349 pr_err("UV: Cannot access UVsystab, remap failed\n");
350 return 0;
351 }
352
353 rev = st->revision;
354 if (rev < UV_SYSTAB_VERSION_UV5) {
355 early_memunmap(st, sizeof(struct uv_systab));
356 return 0;
357 }
358
359 uvst_size = st->size;
360 early_memunmap(st, sizeof(struct uv_systab));
361 st = early_memremap_ro(uvst_physaddr, uvst_size);
362 if (!st) {
363 pr_err("UV: Cannot access UVarchtype, remap failed\n");
364 return 0;
365 }
366
367 ptr = early_find_archtype(st);
368 if (!ptr) {
369 early_memunmap(st, uvst_size);
370 return 0;
371 }
372
373 ret = decode_arch_type(ptr);
374 early_memunmap(st, uvst_size);
375 return ret;
376 }
377
uv_set_system_type(char * _oem_id,char * _oem_table_id)378 static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id)
379 {
380 /* Save OEM_ID passed from ACPI MADT */
381 uv_stringify(sizeof(oem_id), oem_id, _oem_id);
382
383 /* Check if BIOS sent us a UVarchtype */
384 if (!early_get_arch_type())
385
386 /* If not use OEM ID for UVarchtype */
387 uv_stringify(sizeof(uv_archtype), uv_archtype, oem_id);
388
389 /* Check if not hubbed */
390 if (strncmp(uv_archtype, "SGI", 3) != 0) {
391
392 /* (Not hubbed), check if not hubless */
393 if (strncmp(uv_archtype, "NSGI", 4) != 0)
394
395 /* (Not hubless), not a UV */
396 return 0;
397
398 /* Is UV hubless system */
399 uv_hubless_system = 0x01;
400
401 /* UV5 Hubless */
402 if (strncmp(uv_archtype, "NSGI5", 5) == 0)
403 uv_hubless_system |= 0x20;
404
405 /* UV4 Hubless: CH */
406 else if (strncmp(uv_archtype, "NSGI4", 5) == 0)
407 uv_hubless_system |= 0x10;
408
409 /* UV3 Hubless: UV300/MC990X w/o hub */
410 else
411 uv_hubless_system |= 0x8;
412
413 /* Copy APIC type */
414 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
415
416 pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n",
417 oem_id, oem_table_id, uv_system_type, uv_hubless_system);
418 return 0;
419 }
420
421 if (numa_off) {
422 pr_err("UV: NUMA is off, disabling UV support\n");
423 return 0;
424 }
425
426 /* Set hubbed type if true */
427 uv_hub_info->hub_revision =
428 !strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE :
429 !strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
430 !strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
431 !strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0;
432
433 switch (uv_hub_info->hub_revision) {
434 case UV5_HUB_REVISION_BASE:
435 uv_hubbed_system = 0x21;
436 uv_hub_type_set(UV5);
437 break;
438
439 case UV4_HUB_REVISION_BASE:
440 uv_hubbed_system = 0x11;
441 uv_hub_type_set(UV4);
442 break;
443
444 case UV3_HUB_REVISION_BASE:
445 uv_hubbed_system = 0x9;
446 uv_hub_type_set(UV3);
447 break;
448
449 case UV2_HUB_REVISION_BASE:
450 uv_hubbed_system = 0x5;
451 uv_hub_type_set(UV2);
452 break;
453
454 default:
455 return 0;
456 }
457
458 /* Get UV hub chip part number & revision */
459 early_set_hub_type();
460
461 /* Other UV setup functions */
462 early_get_pnodeid();
463 early_get_apic_socketid_shift();
464 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
465 x86_platform.nmi_init = uv_nmi_init;
466 uv_tsc_check_sync();
467
468 return 1;
469 }
470
471 /* Called early to probe for the correct APIC driver */
uv_acpi_madt_oem_check(char * _oem_id,char * _oem_table_id)472 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
473 {
474 /* Set up early hub info fields for Node 0 */
475 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
476
477 /* If not UV, return. */
478 if (uv_set_system_type(_oem_id, _oem_table_id) == 0)
479 return 0;
480
481 /* Save and Decode OEM Table ID */
482 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
483
484 /* This is the most common hardware variant, x2apic mode */
485 if (!strcmp(oem_table_id, "UVX"))
486 uv_system_type = UV_X2APIC;
487
488 /* Only used for very small systems, usually 1 chassis, legacy mode */
489 else if (!strcmp(oem_table_id, "UVL"))
490 uv_system_type = UV_LEGACY_APIC;
491
492 else
493 goto badbios;
494
495 pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n",
496 oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY),
497 uv_min_hub_revision_id);
498
499 return 0;
500
501 badbios:
502 pr_err("UV: UVarchtype:%s not supported\n", uv_archtype);
503 BUG();
504 }
505
get_uv_system_type(void)506 enum uv_system_type get_uv_system_type(void)
507 {
508 return uv_system_type;
509 }
510
is_uv_system(void)511 int is_uv_system(void)
512 {
513 return uv_system_type != UV_NONE;
514 }
515 EXPORT_SYMBOL_GPL(is_uv_system);
516
is_uv_hubbed(int uvtype)517 int is_uv_hubbed(int uvtype)
518 {
519 return (uv_hubbed_system & uvtype);
520 }
521 EXPORT_SYMBOL_GPL(is_uv_hubbed);
522
is_uv_hubless(int uvtype)523 static int is_uv_hubless(int uvtype)
524 {
525 return (uv_hubless_system & uvtype);
526 }
527
528 void **__uv_hub_info_list;
529 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
530
531 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
532 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
533
534 short uv_possible_blades;
535 EXPORT_SYMBOL_GPL(uv_possible_blades);
536
537 unsigned long sn_rtc_cycles_per_second;
538 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
539
540 /* The following values are used for the per node hub info struct */
541 static __initdata unsigned short *_node_to_pnode;
542 static __initdata unsigned short _min_socket, _max_socket;
543 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
544 static __initdata struct uv_gam_range_entry *uv_gre_table;
545 static __initdata struct uv_gam_parameters *uv_gp_table;
546 static __initdata unsigned short *_socket_to_node;
547 static __initdata unsigned short *_socket_to_pnode;
548 static __initdata unsigned short *_pnode_to_socket;
549
550 static __initdata struct uv_gam_range_s *_gr_table;
551
552 #define SOCK_EMPTY ((unsigned short)~0)
553
554 /* Default UV memory block size is 2GB */
555 static unsigned long mem_block_size __initdata = (2UL << 30);
556
557 /* Kernel parameter to specify UV mem block size */
parse_mem_block_size(char * ptr)558 static int __init parse_mem_block_size(char *ptr)
559 {
560 unsigned long size = memparse(ptr, NULL);
561
562 /* Size will be rounded down by set_block_size() below */
563 mem_block_size = size;
564 return 0;
565 }
566 early_param("uv_memblksize", parse_mem_block_size);
567
adj_blksize(u32 lgre)568 static __init int adj_blksize(u32 lgre)
569 {
570 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
571 unsigned long size;
572
573 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
574 if (IS_ALIGNED(base, size))
575 break;
576
577 if (size >= mem_block_size)
578 return 0;
579
580 mem_block_size = size;
581 return 1;
582 }
583
set_block_size(void)584 static __init void set_block_size(void)
585 {
586 unsigned int order = ffs(mem_block_size);
587
588 if (order) {
589 /* adjust for ffs return of 1..64 */
590 set_memory_block_size_order(order - 1);
591 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
592 } else {
593 /* bad or zero value, default to 1UL << 31 (2GB) */
594 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
595 set_memory_block_size_order(31);
596 }
597 }
598
599 /* Build GAM range lookup table: */
build_uv_gr_table(void)600 static __init void build_uv_gr_table(void)
601 {
602 struct uv_gam_range_entry *gre = uv_gre_table;
603 struct uv_gam_range_s *grt;
604 unsigned long last_limit = 0, ram_limit = 0;
605 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
606
607 if (!gre)
608 return;
609
610 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
611 grt = kzalloc(bytes, GFP_KERNEL);
612 BUG_ON(!grt);
613 _gr_table = grt;
614
615 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
616 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
617 if (!ram_limit) {
618 /* Mark hole between RAM/non-RAM: */
619 ram_limit = last_limit;
620 last_limit = gre->limit;
621 lsid++;
622 continue;
623 }
624 last_limit = gre->limit;
625 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
626 continue;
627 }
628 if (_max_socket < gre->sockid) {
629 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
630 continue;
631 }
632 sid = gre->sockid - _min_socket;
633 if (lsid < sid) {
634 /* New range: */
635 grt = &_gr_table[indx];
636 grt->base = lindx;
637 grt->nasid = gre->nasid;
638 grt->limit = last_limit = gre->limit;
639 lsid = sid;
640 lindx = indx++;
641 continue;
642 }
643 /* Update range: */
644 if (lsid == sid && !ram_limit) {
645 /* .. if contiguous: */
646 if (grt->limit == last_limit) {
647 grt->limit = last_limit = gre->limit;
648 continue;
649 }
650 }
651 /* Non-contiguous RAM range: */
652 if (!ram_limit) {
653 grt++;
654 grt->base = lindx;
655 grt->nasid = gre->nasid;
656 grt->limit = last_limit = gre->limit;
657 continue;
658 }
659 /* Non-contiguous/non-RAM: */
660 grt++;
661 /* base is this entry */
662 grt->base = grt - _gr_table;
663 grt->nasid = gre->nasid;
664 grt->limit = last_limit = gre->limit;
665 lsid++;
666 }
667
668 /* Shorten table if possible */
669 grt++;
670 i = grt - _gr_table;
671 if (i < _gr_table_len) {
672 void *ret;
673
674 bytes = i * sizeof(struct uv_gam_range_s);
675 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
676 if (ret) {
677 _gr_table = ret;
678 _gr_table_len = i;
679 }
680 }
681
682 /* Display resultant GAM range table: */
683 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
684 unsigned long start, end;
685 int gb = grt->base;
686
687 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
688 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
689
690 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
691 }
692 }
693
uv_wakeup_secondary(int phys_apicid,unsigned long start_rip)694 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
695 {
696 unsigned long val;
697 int pnode;
698
699 pnode = uv_apicid_to_pnode(phys_apicid);
700
701 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
702 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
703 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
704 APIC_DM_INIT;
705
706 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
707
708 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
709 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
710 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
711 APIC_DM_STARTUP;
712
713 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
714
715 return 0;
716 }
717
uv_send_IPI_one(int cpu,int vector)718 static void uv_send_IPI_one(int cpu, int vector)
719 {
720 unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu);
721 int pnode = uv_apicid_to_pnode(apicid);
722 unsigned long dmode, val;
723
724 if (vector == NMI_VECTOR)
725 dmode = dest_NMI;
726 else
727 dmode = dest_Fixed;
728
729 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
730 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
731 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
732 (vector << UVH_IPI_INT_VECTOR_SHFT);
733
734 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
735 }
736
uv_send_IPI_mask(const struct cpumask * mask,int vector)737 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
738 {
739 unsigned int cpu;
740
741 for_each_cpu(cpu, mask)
742 uv_send_IPI_one(cpu, vector);
743 }
744
uv_send_IPI_mask_allbutself(const struct cpumask * mask,int vector)745 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
746 {
747 unsigned int this_cpu = smp_processor_id();
748 unsigned int cpu;
749
750 for_each_cpu(cpu, mask) {
751 if (cpu != this_cpu)
752 uv_send_IPI_one(cpu, vector);
753 }
754 }
755
uv_send_IPI_allbutself(int vector)756 static void uv_send_IPI_allbutself(int vector)
757 {
758 unsigned int this_cpu = smp_processor_id();
759 unsigned int cpu;
760
761 for_each_online_cpu(cpu) {
762 if (cpu != this_cpu)
763 uv_send_IPI_one(cpu, vector);
764 }
765 }
766
uv_send_IPI_all(int vector)767 static void uv_send_IPI_all(int vector)
768 {
769 uv_send_IPI_mask(cpu_online_mask, vector);
770 }
771
uv_apic_id_valid(u32 apicid)772 static int uv_apic_id_valid(u32 apicid)
773 {
774 return 1;
775 }
776
uv_apic_id_registered(void)777 static int uv_apic_id_registered(void)
778 {
779 return 1;
780 }
781
uv_init_apic_ldr(void)782 static void uv_init_apic_ldr(void)
783 {
784 }
785
apic_uv_calc_apicid(unsigned int cpu)786 static u32 apic_uv_calc_apicid(unsigned int cpu)
787 {
788 return apic_default_calc_apicid(cpu);
789 }
790
x2apic_get_apic_id(unsigned long id)791 static unsigned int x2apic_get_apic_id(unsigned long id)
792 {
793 return id;
794 }
795
set_apic_id(unsigned int id)796 static u32 set_apic_id(unsigned int id)
797 {
798 return id;
799 }
800
uv_read_apic_id(void)801 static unsigned int uv_read_apic_id(void)
802 {
803 return x2apic_get_apic_id(apic_read(APIC_ID));
804 }
805
uv_phys_pkg_id(int initial_apicid,int index_msb)806 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
807 {
808 return uv_read_apic_id() >> index_msb;
809 }
810
uv_send_IPI_self(int vector)811 static void uv_send_IPI_self(int vector)
812 {
813 apic_write(APIC_SELF_IPI, vector);
814 }
815
uv_probe(void)816 static int uv_probe(void)
817 {
818 return apic == &apic_x2apic_uv_x;
819 }
820
821 static struct apic apic_x2apic_uv_x __ro_after_init = {
822
823 .name = "UV large system",
824 .probe = uv_probe,
825 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
826 .apic_id_valid = uv_apic_id_valid,
827 .apic_id_registered = uv_apic_id_registered,
828
829 .irq_delivery_mode = dest_Fixed,
830 .irq_dest_mode = 0, /* Physical */
831
832 .disable_esr = 0,
833 .dest_logical = APIC_DEST_LOGICAL,
834 .check_apicid_used = NULL,
835
836 .init_apic_ldr = uv_init_apic_ldr,
837
838 .ioapic_phys_id_map = NULL,
839 .setup_apic_routing = NULL,
840 .cpu_present_to_apicid = default_cpu_present_to_apicid,
841 .apicid_to_cpu_present = NULL,
842 .check_phys_apicid_present = default_check_phys_apicid_present,
843 .phys_pkg_id = uv_phys_pkg_id,
844
845 .get_apic_id = x2apic_get_apic_id,
846 .set_apic_id = set_apic_id,
847
848 .calc_dest_apicid = apic_uv_calc_apicid,
849
850 .send_IPI = uv_send_IPI_one,
851 .send_IPI_mask = uv_send_IPI_mask,
852 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
853 .send_IPI_allbutself = uv_send_IPI_allbutself,
854 .send_IPI_all = uv_send_IPI_all,
855 .send_IPI_self = uv_send_IPI_self,
856
857 .wakeup_secondary_cpu = uv_wakeup_secondary,
858 .inquire_remote_apic = NULL,
859
860 .read = native_apic_msr_read,
861 .write = native_apic_msr_write,
862 .eoi_write = native_apic_msr_eoi_write,
863 .icr_read = native_x2apic_icr_read,
864 .icr_write = native_x2apic_icr_write,
865 .wait_icr_idle = native_x2apic_wait_icr_idle,
866 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
867 };
868
869 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
870 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT
871
get_lowmem_redirect(unsigned long * base,unsigned long * size)872 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
873 {
874 union uvh_rh_gam_alias_2_overlay_config_u alias;
875 union uvh_rh_gam_alias_2_redirect_config_u redirect;
876 unsigned long m_redirect;
877 unsigned long m_overlay;
878 int i;
879
880 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
881 switch (i) {
882 case 0:
883 m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG;
884 m_overlay = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG;
885 break;
886 case 1:
887 m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG;
888 m_overlay = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG;
889 break;
890 case 2:
891 m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG;
892 m_overlay = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG;
893 break;
894 }
895 alias.v = uv_read_local_mmr(m_overlay);
896 if (alias.s.enable && alias.s.base == 0) {
897 *size = (1UL << alias.s.m_alias);
898 redirect.v = uv_read_local_mmr(m_redirect);
899 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
900 return;
901 }
902 }
903 *base = *size = 0;
904 }
905
906 enum map_type {map_wb, map_uc};
907 static const char * const mt[] = { "WB", "UC" };
908
map_high(char * id,unsigned long base,int pshift,int bshift,int max_pnode,enum map_type map_type)909 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
910 {
911 unsigned long bytes, paddr;
912
913 paddr = base << pshift;
914 bytes = (1UL << bshift) * (max_pnode + 1);
915 if (!paddr) {
916 pr_info("UV: Map %s_HI base address NULL\n", id);
917 return;
918 }
919 if (map_type == map_uc)
920 init_extra_mapping_uc(paddr, bytes);
921 else
922 init_extra_mapping_wb(paddr, bytes);
923
924 pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n",
925 id, paddr, paddr + bytes, mt[map_type], max_pnode + 1);
926 }
927
map_gru_high(int max_pnode)928 static __init void map_gru_high(int max_pnode)
929 {
930 union uvh_rh_gam_gru_overlay_config_u gru;
931 unsigned long mask, base;
932 int shift;
933
934 if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) {
935 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG);
936 shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
937 mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
938 } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) {
939 gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG);
940 shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
941 mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
942 } else {
943 pr_err("UV: GRU unavailable (no MMR)\n");
944 return;
945 }
946
947 if (!gru.s.enable) {
948 pr_info("UV: GRU disabled (by BIOS)\n");
949 return;
950 }
951
952 base = (gru.v & mask) >> shift;
953 map_high("GRU", base, shift, shift, max_pnode, map_wb);
954 gru_start_paddr = ((u64)base << shift);
955 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
956 }
957
map_mmr_high(int max_pnode)958 static __init void map_mmr_high(int max_pnode)
959 {
960 unsigned long base;
961 int shift;
962 bool enable;
963
964 if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) {
965 union uvh_rh10_gam_mmr_overlay_config_u mmr;
966
967 mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG);
968 enable = mmr.s.enable;
969 base = mmr.s.base;
970 shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
971 } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) {
972 union uvh_rh_gam_mmr_overlay_config_u mmr;
973
974 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG);
975 enable = mmr.s.enable;
976 base = mmr.s.base;
977 shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
978 } else {
979 pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n",
980 __func__);
981 return;
982 }
983
984 if (enable)
985 map_high("MMR", base, shift, shift, max_pnode, map_uc);
986 else
987 pr_info("UV: MMR disabled\n");
988 }
989
990 /* Arch specific ENUM cases */
991 enum mmioh_arch {
992 UV2_MMIOH = -1,
993 UVY_MMIOH0, UVY_MMIOH1,
994 UVX_MMIOH0, UVX_MMIOH1,
995 };
996
997 /* Calculate and Map MMIOH Regions */
calc_mmioh_map(enum mmioh_arch index,int min_pnode,int max_pnode,int shift,unsigned long base,int m_io,int n_io)998 static void __init calc_mmioh_map(enum mmioh_arch index,
999 int min_pnode, int max_pnode,
1000 int shift, unsigned long base, int m_io, int n_io)
1001 {
1002 unsigned long mmr, nasid_mask;
1003 int nasid, min_nasid, max_nasid, lnasid, mapped;
1004 int i, fi, li, n, max_io;
1005 char id[8];
1006
1007 /* One (UV2) mapping */
1008 if (index == UV2_MMIOH) {
1009 strncpy(id, "MMIOH", sizeof(id));
1010 max_io = max_pnode;
1011 mapped = 0;
1012 goto map_exit;
1013 }
1014
1015 /* small and large MMIOH mappings */
1016 switch (index) {
1017 case UVY_MMIOH0:
1018 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0;
1019 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
1020 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1021 min_nasid = min_pnode;
1022 max_nasid = max_pnode;
1023 mapped = 1;
1024 break;
1025 case UVY_MMIOH1:
1026 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1;
1027 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
1028 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1029 min_nasid = min_pnode;
1030 max_nasid = max_pnode;
1031 mapped = 1;
1032 break;
1033 case UVX_MMIOH0:
1034 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0;
1035 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
1036 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1037 min_nasid = min_pnode * 2;
1038 max_nasid = max_pnode * 2;
1039 mapped = 1;
1040 break;
1041 case UVX_MMIOH1:
1042 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1;
1043 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
1044 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1045 min_nasid = min_pnode * 2;
1046 max_nasid = max_pnode * 2;
1047 mapped = 1;
1048 break;
1049 default:
1050 pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index);
1051 return;
1052 }
1053
1054 /* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */
1055 snprintf(id, sizeof(id), "MMIOH%d", index%2);
1056
1057 max_io = lnasid = fi = li = -1;
1058 for (i = 0; i < n; i++) {
1059 unsigned long m_redirect = mmr + i * 8;
1060 unsigned long redirect = uv_read_local_mmr(m_redirect);
1061
1062 nasid = redirect & nasid_mask;
1063 if (i == 0)
1064 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
1065 id, redirect, m_redirect, nasid);
1066
1067 /* Invalid NASID check */
1068 if (nasid < min_nasid || max_nasid < nasid) {
1069 pr_err("UV:%s:Invalid NASID:%x (range:%x..%x)\n",
1070 __func__, index, min_nasid, max_nasid);
1071 nasid = -1;
1072 }
1073
1074 if (nasid == lnasid) {
1075 li = i;
1076 /* Last entry check: */
1077 if (i != n-1)
1078 continue;
1079 }
1080
1081 /* Check if we have a cached (or last) redirect to print: */
1082 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
1083 unsigned long addr1, addr2;
1084 int f, l;
1085
1086 if (lnasid == -1) {
1087 f = l = i;
1088 lnasid = nasid;
1089 } else {
1090 f = fi;
1091 l = li;
1092 }
1093 addr1 = (base << shift) + f * (1ULL << m_io);
1094 addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
1095 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
1096 id, fi, li, lnasid, addr1, addr2);
1097 if (max_io < l)
1098 max_io = l;
1099 }
1100 fi = li = i;
1101 lnasid = nasid;
1102 }
1103
1104 map_exit:
1105 pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n",
1106 id, base, shift, m_io, max_io, max_pnode);
1107
1108 if (max_io >= 0 && !mapped)
1109 map_high(id, base, shift, m_io, max_io, map_uc);
1110 }
1111
map_mmioh_high(int min_pnode,int max_pnode)1112 static __init void map_mmioh_high(int min_pnode, int max_pnode)
1113 {
1114 /* UVY flavor */
1115 if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) {
1116 union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0;
1117 union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1;
1118
1119 mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0);
1120 if (unlikely(mmioh0.s.enable == 0))
1121 pr_info("UV: MMIOH0 disabled\n");
1122 else
1123 calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode,
1124 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1125 mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io);
1126
1127 mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1);
1128 if (unlikely(mmioh1.s.enable == 0))
1129 pr_info("UV: MMIOH1 disabled\n");
1130 else
1131 calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode,
1132 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1133 mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io);
1134 return;
1135 }
1136 /* UVX flavor */
1137 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) {
1138 union uvh_rh_gam_mmioh_overlay_config0_u mmioh0;
1139 union uvh_rh_gam_mmioh_overlay_config1_u mmioh1;
1140
1141 mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0);
1142 if (unlikely(mmioh0.s.enable == 0))
1143 pr_info("UV: MMIOH0 disabled\n");
1144 else {
1145 unsigned long base = uvxy_field(mmioh0, base, 0);
1146 int m_io = uvxy_field(mmioh0, m_io, 0);
1147 int n_io = uvxy_field(mmioh0, n_io, 0);
1148
1149 calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode,
1150 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1151 base, m_io, n_io);
1152 }
1153
1154 mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1);
1155 if (unlikely(mmioh1.s.enable == 0))
1156 pr_info("UV: MMIOH1 disabled\n");
1157 else {
1158 unsigned long base = uvxy_field(mmioh1, base, 0);
1159 int m_io = uvxy_field(mmioh1, m_io, 0);
1160 int n_io = uvxy_field(mmioh1, n_io, 0);
1161
1162 calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode,
1163 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1164 base, m_io, n_io);
1165 }
1166 return;
1167 }
1168
1169 /* UV2 flavor */
1170 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) {
1171 union uvh_rh_gam_mmioh_overlay_config_u mmioh;
1172
1173 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG);
1174 if (unlikely(mmioh.s2.enable == 0))
1175 pr_info("UV: MMIOH disabled\n");
1176 else
1177 calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode,
1178 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT,
1179 mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io);
1180 return;
1181 }
1182 }
1183
map_low_mmrs(void)1184 static __init void map_low_mmrs(void)
1185 {
1186 if (UV_GLOBAL_MMR32_BASE)
1187 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
1188
1189 if (UV_LOCAL_MMR_BASE)
1190 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
1191 }
1192
uv_rtc_init(void)1193 static __init void uv_rtc_init(void)
1194 {
1195 long status;
1196 u64 ticks_per_sec;
1197
1198 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
1199
1200 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
1201 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
1202
1203 /* BIOS gives wrong value for clock frequency, so guess: */
1204 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
1205 } else {
1206 sn_rtc_cycles_per_second = ticks_per_sec;
1207 }
1208 }
1209
1210 /* Direct Legacy VGA I/O traffic to designated IOH */
uv_set_vga_state(struct pci_dev * pdev,bool decode,unsigned int command_bits,u32 flags)1211 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1212 {
1213 int domain, bus, rc;
1214
1215 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1216 return 0;
1217
1218 if ((command_bits & PCI_COMMAND_IO) == 0)
1219 return 0;
1220
1221 domain = pci_domain_nr(pdev->bus);
1222 bus = pdev->bus->number;
1223
1224 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1225
1226 return rc;
1227 }
1228
1229 /*
1230 * Called on each CPU to initialize the per_cpu UV data area.
1231 * FIXME: hotplug not supported yet
1232 */
uv_cpu_init(void)1233 void uv_cpu_init(void)
1234 {
1235 /* CPU 0 initialization will be done via uv_system_init. */
1236 if (smp_processor_id() == 0)
1237 return;
1238
1239 uv_hub_info->nr_online_cpus++;
1240 }
1241
1242 struct mn {
1243 unsigned char m_val;
1244 unsigned char n_val;
1245 unsigned char m_shift;
1246 unsigned char n_lshift;
1247 };
1248
1249 /* Initialize caller's MN struct and fill in values */
get_mn(struct mn * mnp)1250 static void get_mn(struct mn *mnp)
1251 {
1252 memset(mnp, 0, sizeof(*mnp));
1253 mnp->n_val = uv_cpuid.n_skt;
1254 if (is_uv(UV4|UVY)) {
1255 mnp->m_val = 0;
1256 mnp->n_lshift = 0;
1257 } else if (is_uv3_hub()) {
1258 union uvyh_gr0_gam_gr_config_u m_gr_config;
1259
1260 mnp->m_val = uv_cpuid.m_skt;
1261 m_gr_config.v = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG);
1262 mnp->n_lshift = m_gr_config.s3.m_skt;
1263 } else if (is_uv2_hub()) {
1264 mnp->m_val = uv_cpuid.m_skt;
1265 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1266 }
1267 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1268 }
1269
uv_init_hub_info(struct uv_hub_info_s * hi)1270 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1271 {
1272 struct mn mn;
1273
1274 get_mn(&mn);
1275 hi->gpa_mask = mn.m_val ?
1276 (1UL << (mn.m_val + mn.n_val)) - 1 :
1277 (1UL << uv_cpuid.gpa_shift) - 1;
1278
1279 hi->m_val = mn.m_val;
1280 hi->n_val = mn.n_val;
1281 hi->m_shift = mn.m_shift;
1282 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1283 hi->hub_revision = uv_hub_info->hub_revision;
1284 hi->hub_type = uv_hub_info->hub_type;
1285 hi->pnode_mask = uv_cpuid.pnode_mask;
1286 hi->nasid_shift = uv_cpuid.nasid_shift;
1287 hi->min_pnode = _min_pnode;
1288 hi->min_socket = _min_socket;
1289 hi->pnode_to_socket = _pnode_to_socket;
1290 hi->socket_to_node = _socket_to_node;
1291 hi->socket_to_pnode = _socket_to_pnode;
1292 hi->gr_table_len = _gr_table_len;
1293 hi->gr_table = _gr_table;
1294
1295 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1296 hi->gnode_extra = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1297 if (mn.m_val)
1298 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1299
1300 if (uv_gp_table) {
1301 hi->global_mmr_base = uv_gp_table->mmr_base;
1302 hi->global_mmr_shift = uv_gp_table->mmr_shift;
1303 hi->global_gru_base = uv_gp_table->gru_base;
1304 hi->global_gru_shift = uv_gp_table->gru_shift;
1305 hi->gpa_shift = uv_gp_table->gpa_shift;
1306 hi->gpa_mask = (1UL << hi->gpa_shift) - 1;
1307 } else {
1308 hi->global_mmr_base =
1309 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) &
1310 ~UV_MMR_ENABLE;
1311 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1312 }
1313
1314 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1315
1316 hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1317
1318 /* Show system specific info: */
1319 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1320 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1321 pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift);
1322 if (hi->global_gru_base)
1323 pr_info("UV: gru_base/shift:0x%lx/%ld\n",
1324 hi->global_gru_base, hi->global_gru_shift);
1325
1326 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1327 }
1328
decode_gam_params(unsigned long ptr)1329 static void __init decode_gam_params(unsigned long ptr)
1330 {
1331 uv_gp_table = (struct uv_gam_parameters *)ptr;
1332
1333 pr_info("UV: GAM Params...\n");
1334 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1335 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1336 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1337 uv_gp_table->gpa_shift);
1338 }
1339
decode_gam_rng_tbl(unsigned long ptr)1340 static void __init decode_gam_rng_tbl(unsigned long ptr)
1341 {
1342 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1343 unsigned long lgre = 0;
1344 int index = 0;
1345 int sock_min = 999999, pnode_min = 99999;
1346 int sock_max = -1, pnode_max = -1;
1347
1348 uv_gre_table = gre;
1349 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1350 unsigned long size = ((unsigned long)(gre->limit - lgre)
1351 << UV_GAM_RANGE_SHFT);
1352 int order = 0;
1353 char suffix[] = " KMGTPE";
1354 int flag = ' ';
1355
1356 while (size > 9999 && order < sizeof(suffix)) {
1357 size /= 1024;
1358 order++;
1359 }
1360
1361 /* adjust max block size to current range start */
1362 if (gre->type == 1 || gre->type == 2)
1363 if (adj_blksize(lgre))
1364 flag = '*';
1365
1366 if (!index) {
1367 pr_info("UV: GAM Range Table...\n");
1368 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1369 }
1370 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n",
1371 index++,
1372 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1373 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1374 flag, size, suffix[order],
1375 gre->type, gre->nasid, gre->sockid, gre->pnode);
1376
1377 /* update to next range start */
1378 lgre = gre->limit;
1379 if (sock_min > gre->sockid)
1380 sock_min = gre->sockid;
1381 if (sock_max < gre->sockid)
1382 sock_max = gre->sockid;
1383 if (pnode_min > gre->pnode)
1384 pnode_min = gre->pnode;
1385 if (pnode_max < gre->pnode)
1386 pnode_max = gre->pnode;
1387 }
1388 _min_socket = sock_min;
1389 _max_socket = sock_max;
1390 _min_pnode = pnode_min;
1391 _max_pnode = pnode_max;
1392 _gr_table_len = index;
1393
1394 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1395 }
1396
1397 /* Walk through UVsystab decoding the fields */
decode_uv_systab(void)1398 static int __init decode_uv_systab(void)
1399 {
1400 struct uv_systab *st;
1401 int i;
1402
1403 /* Get mapped UVsystab pointer */
1404 st = uv_systab;
1405
1406 /* If UVsystab is version 1, there is no extended UVsystab */
1407 if (st && st->revision == UV_SYSTAB_VERSION_1)
1408 return 0;
1409
1410 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1411 int rev = st ? st->revision : 0;
1412
1413 pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n",
1414 rev, UV_SYSTAB_VERSION_UV4_LATEST);
1415 pr_err("UV: Does not support UV, switch to non-UV x86_64\n");
1416 uv_system_type = UV_NONE;
1417
1418 return -EINVAL;
1419 }
1420
1421 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1422 unsigned long ptr = st->entry[i].offset;
1423
1424 if (!ptr)
1425 continue;
1426
1427 /* point to payload */
1428 ptr += (unsigned long)st;
1429
1430 switch (st->entry[i].type) {
1431 case UV_SYSTAB_TYPE_GAM_PARAMS:
1432 decode_gam_params(ptr);
1433 break;
1434
1435 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1436 decode_gam_rng_tbl(ptr);
1437 break;
1438
1439 case UV_SYSTAB_TYPE_ARCH_TYPE:
1440 /* already processed in early startup */
1441 break;
1442
1443 default:
1444 pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n",
1445 __func__, st->entry[i].type);
1446 break;
1447 }
1448 }
1449 return 0;
1450 }
1451
1452 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */
boot_init_possible_blades(struct uv_hub_info_s * hub_info)1453 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1454 {
1455 unsigned long np;
1456 int i, uv_pb = 0;
1457
1458 if (UVH_NODE_PRESENT_TABLE) {
1459 pr_info("UV: NODE_PRESENT_DEPTH = %d\n",
1460 UVH_NODE_PRESENT_TABLE_DEPTH);
1461 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1462 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1463 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1464 uv_pb += hweight64(np);
1465 }
1466 }
1467 if (UVH_NODE_PRESENT_0) {
1468 np = uv_read_local_mmr(UVH_NODE_PRESENT_0);
1469 pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np);
1470 uv_pb += hweight64(np);
1471 }
1472 if (UVH_NODE_PRESENT_1) {
1473 np = uv_read_local_mmr(UVH_NODE_PRESENT_1);
1474 pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np);
1475 uv_pb += hweight64(np);
1476 }
1477 if (uv_possible_blades != uv_pb)
1478 uv_possible_blades = uv_pb;
1479
1480 pr_info("UV: number nodes/possible blades %d\n", uv_pb);
1481 }
1482
build_socket_tables(void)1483 static void __init build_socket_tables(void)
1484 {
1485 struct uv_gam_range_entry *gre = uv_gre_table;
1486 int num, nump;
1487 int cpu, i, lnid;
1488 int minsock = _min_socket;
1489 int maxsock = _max_socket;
1490 int minpnode = _min_pnode;
1491 int maxpnode = _max_pnode;
1492 size_t bytes;
1493
1494 if (!gre) {
1495 if (is_uv2_hub() || is_uv3_hub()) {
1496 pr_info("UV: No UVsystab socket table, ignoring\n");
1497 return;
1498 }
1499 pr_err("UV: Error: UVsystab address translations not available!\n");
1500 BUG();
1501 }
1502
1503 /* Build socket id -> node id, pnode */
1504 num = maxsock - minsock + 1;
1505 bytes = num * sizeof(_socket_to_node[0]);
1506 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1507 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1508
1509 nump = maxpnode - minpnode + 1;
1510 bytes = nump * sizeof(_pnode_to_socket[0]);
1511 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1512 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1513
1514 for (i = 0; i < num; i++)
1515 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1516
1517 for (i = 0; i < nump; i++)
1518 _pnode_to_socket[i] = SOCK_EMPTY;
1519
1520 /* Fill in pnode/node/addr conversion list values: */
1521 pr_info("UV: GAM Building socket/pnode conversion tables\n");
1522 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1523 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1524 continue;
1525 i = gre->sockid - minsock;
1526 /* Duplicate: */
1527 if (_socket_to_pnode[i] != SOCK_EMPTY)
1528 continue;
1529 _socket_to_pnode[i] = gre->pnode;
1530
1531 i = gre->pnode - minpnode;
1532 _pnode_to_socket[i] = gre->sockid;
1533
1534 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1535 gre->sockid, gre->type, gre->nasid,
1536 _socket_to_pnode[gre->sockid - minsock],
1537 _pnode_to_socket[gre->pnode - minpnode]);
1538 }
1539
1540 /* Set socket -> node values: */
1541 lnid = NUMA_NO_NODE;
1542 for_each_present_cpu(cpu) {
1543 int nid = cpu_to_node(cpu);
1544 int apicid, sockid;
1545
1546 if (lnid == nid)
1547 continue;
1548 lnid = nid;
1549 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1550 sockid = apicid >> uv_cpuid.socketid_shift;
1551 _socket_to_node[sockid - minsock] = nid;
1552 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1553 sockid, apicid, nid);
1554 }
1555
1556 /* Set up physical blade to pnode translation from GAM Range Table: */
1557 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1558 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1559 BUG_ON(!_node_to_pnode);
1560
1561 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1562 unsigned short sockid;
1563
1564 for (sockid = minsock; sockid <= maxsock; sockid++) {
1565 if (lnid == _socket_to_node[sockid - minsock]) {
1566 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1567 break;
1568 }
1569 }
1570 if (sockid > maxsock) {
1571 pr_err("UV: socket for node %d not found!\n", lnid);
1572 BUG();
1573 }
1574 }
1575
1576 /*
1577 * If socket id == pnode or socket id == node for all nodes,
1578 * system runs faster by removing corresponding conversion table.
1579 */
1580 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1581 if (minsock == 0) {
1582 for (i = 0; i < num; i++)
1583 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1584 break;
1585 if (i >= num) {
1586 kfree(_socket_to_node);
1587 _socket_to_node = NULL;
1588 pr_info("UV: 1:1 socket_to_node table removed\n");
1589 }
1590 }
1591 if (minsock == minpnode) {
1592 for (i = 0; i < num; i++)
1593 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1594 _socket_to_pnode[i] != i + minpnode)
1595 break;
1596 if (i >= num) {
1597 kfree(_socket_to_pnode);
1598 _socket_to_pnode = NULL;
1599 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1600 }
1601 }
1602 }
1603
1604 /* Check which reboot to use */
check_efi_reboot(void)1605 static void check_efi_reboot(void)
1606 {
1607 /* If EFI reboot not available, use ACPI reboot */
1608 if (!efi_enabled(EFI_BOOT))
1609 reboot_type = BOOT_ACPI;
1610 }
1611
1612 /* Setup user proc fs files */
proc_hubbed_show(struct seq_file * file,void * data)1613 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data)
1614 {
1615 seq_printf(file, "0x%x\n", uv_hubbed_system);
1616 return 0;
1617 }
1618
proc_hubless_show(struct seq_file * file,void * data)1619 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data)
1620 {
1621 seq_printf(file, "0x%x\n", uv_hubless_system);
1622 return 0;
1623 }
1624
proc_archtype_show(struct seq_file * file,void * data)1625 static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data)
1626 {
1627 seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id);
1628 return 0;
1629 }
1630
uv_setup_proc_files(int hubless)1631 static __init void uv_setup_proc_files(int hubless)
1632 {
1633 struct proc_dir_entry *pde;
1634
1635 pde = proc_mkdir(UV_PROC_NODE, NULL);
1636 proc_create_single("archtype", 0, pde, proc_archtype_show);
1637 if (hubless)
1638 proc_create_single("hubless", 0, pde, proc_hubless_show);
1639 else
1640 proc_create_single("hubbed", 0, pde, proc_hubbed_show);
1641 }
1642
1643 /* Initialize UV hubless systems */
uv_system_init_hubless(void)1644 static __init int uv_system_init_hubless(void)
1645 {
1646 int rc;
1647
1648 /* Setup PCH NMI handler */
1649 uv_nmi_setup_hubless();
1650
1651 /* Init kernel/BIOS interface */
1652 rc = uv_bios_init();
1653 if (rc < 0)
1654 return rc;
1655
1656 /* Process UVsystab */
1657 rc = decode_uv_systab();
1658 if (rc < 0)
1659 return rc;
1660
1661 /* Set section block size for current node memory */
1662 set_block_size();
1663
1664 /* Create user access node */
1665 if (rc >= 0)
1666 uv_setup_proc_files(1);
1667
1668 check_efi_reboot();
1669
1670 return rc;
1671 }
1672
uv_system_init_hub(void)1673 static void __init uv_system_init_hub(void)
1674 {
1675 struct uv_hub_info_s hub_info = {0};
1676 int bytes, cpu, nodeid;
1677 unsigned short min_pnode = 9999, max_pnode = 0;
1678 char *hub = is_uv5_hub() ? "UV500" :
1679 is_uv4_hub() ? "UV400" :
1680 is_uv3_hub() ? "UV300" :
1681 is_uv2_hub() ? "UV2000/3000" : NULL;
1682
1683 if (!hub) {
1684 pr_err("UV: Unknown/unsupported UV hub\n");
1685 return;
1686 }
1687 pr_info("UV: Found %s hub\n", hub);
1688
1689 map_low_mmrs();
1690
1691 /* Get uv_systab for decoding, setup UV BIOS calls */
1692 uv_bios_init();
1693
1694 /* If there's an UVsystab problem then abort UV init: */
1695 if (decode_uv_systab() < 0) {
1696 pr_err("UV: Mangled UVsystab format\n");
1697 return;
1698 }
1699
1700 build_socket_tables();
1701 build_uv_gr_table();
1702 set_block_size();
1703 uv_init_hub_info(&hub_info);
1704 uv_possible_blades = num_possible_nodes();
1705 if (!_node_to_pnode)
1706 boot_init_possible_blades(&hub_info);
1707
1708 /* uv_num_possible_blades() is really the hub count: */
1709 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1710
1711 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1712 hub_info.coherency_domain_number = sn_coherency_id;
1713 uv_rtc_init();
1714
1715 bytes = sizeof(void *) * uv_num_possible_blades();
1716 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1717 BUG_ON(!__uv_hub_info_list);
1718
1719 bytes = sizeof(struct uv_hub_info_s);
1720 for_each_node(nodeid) {
1721 struct uv_hub_info_s *new_hub;
1722
1723 if (__uv_hub_info_list[nodeid]) {
1724 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1725 BUG();
1726 }
1727
1728 /* Allocate new per hub info list */
1729 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1730 BUG_ON(!new_hub);
1731 __uv_hub_info_list[nodeid] = new_hub;
1732 new_hub = uv_hub_info_list(nodeid);
1733 BUG_ON(!new_hub);
1734 *new_hub = hub_info;
1735
1736 /* Use information from GAM table if available: */
1737 if (_node_to_pnode)
1738 new_hub->pnode = _node_to_pnode[nodeid];
1739 else /* Or fill in during CPU loop: */
1740 new_hub->pnode = 0xffff;
1741
1742 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1743 new_hub->memory_nid = NUMA_NO_NODE;
1744 new_hub->nr_possible_cpus = 0;
1745 new_hub->nr_online_cpus = 0;
1746 }
1747
1748 /* Initialize per CPU info: */
1749 for_each_possible_cpu(cpu) {
1750 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1751 int numa_node_id;
1752 unsigned short pnode;
1753
1754 nodeid = cpu_to_node(cpu);
1755 numa_node_id = numa_cpu_node(cpu);
1756 pnode = uv_apicid_to_pnode(apicid);
1757
1758 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1759 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1760 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1761 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1762
1763 /* Init memoryless node: */
1764 if (nodeid != numa_node_id &&
1765 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1766 uv_hub_info_list(numa_node_id)->pnode = pnode;
1767 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1768 uv_cpu_hub_info(cpu)->pnode = pnode;
1769 }
1770
1771 for_each_node(nodeid) {
1772 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1773
1774 /* Add pnode info for pre-GAM list nodes without CPUs: */
1775 if (pnode == 0xffff) {
1776 unsigned long paddr;
1777
1778 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1779 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1780 uv_hub_info_list(nodeid)->pnode = pnode;
1781 }
1782 min_pnode = min(pnode, min_pnode);
1783 max_pnode = max(pnode, max_pnode);
1784 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1785 nodeid,
1786 uv_hub_info_list(nodeid)->pnode,
1787 uv_hub_info_list(nodeid)->nr_possible_cpus);
1788 }
1789
1790 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1791 map_gru_high(max_pnode);
1792 map_mmr_high(max_pnode);
1793 map_mmioh_high(min_pnode, max_pnode);
1794
1795 uv_nmi_setup();
1796 uv_cpu_init();
1797 uv_setup_proc_files(0);
1798
1799 /* Register Legacy VGA I/O redirection handler: */
1800 pci_register_set_vga_state(uv_set_vga_state);
1801
1802 check_efi_reboot();
1803 }
1804
1805 /*
1806 * There is a different code path needed to initialize a UV system that does
1807 * not have a "UV HUB" (referred to as "hubless").
1808 */
uv_system_init(void)1809 void __init uv_system_init(void)
1810 {
1811 if (likely(!is_uv_system() && !is_uv_hubless(1)))
1812 return;
1813
1814 if (is_uv_system())
1815 uv_system_init_hub();
1816 else
1817 uv_system_init_hubless();
1818 }
1819
1820 apic_driver(apic_x2apic_uv_x);
1821