| /third_party/mesa3d/src/asahi/compiler/ |
| D | agx_opcodes.py | 29 def __init__(self, name, dests, srcs, imms, is_float, can_eliminate, encoding_16, encoding_32): argument
60 def op(name, encoding_32, dests = 1, srcs = 0, imms = [], is_float = False, can_eliminate = True, e… argument
234 imms = [NEST, FCOND if is_float else ICOND, INVERT_COND] variable
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| /third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_dataflow_swizzles.c | 101 float imms[4] = {0.0f, 0.0f, 0.0f, 0.0f}; in try_rewrite_constant() local
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| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_build_util.h | 198 ImmediateValue *imms[NV50_IR_BUILD_IMM_HT_SIZE]; variable
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| /third_party/mesa3d/src/gallium/auxiliary/translate/ |
| D | translate_sse.c | 489 unsigned imms[2] = { 0, 0x3f800000 }; in translate_attr_convert() local
770 unsigned imms[2] = { 0, 1 }; in translate_attr_convert() local
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| /third_party/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 7117 static Instr SVEImmSetBits(unsigned imms, unsigned lane_size) { in SVEImmSetBits()
7166 static Instr ImmS(unsigned imms, unsigned reg_size) { in ImmS()
7181 static Instr ImmSetBits(unsigned imms, unsigned reg_size) { in ImmSetBits()
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| D | assembler-aarch64.cc | 682 unsigned imms) { in bfm()
693 unsigned imms) { in sbfm()
704 unsigned imms) { in ubfm()
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| D | macro-assembler-aarch64.h | 1179 unsigned imms) { in Bfm()
2414 unsigned imms) { in Sbfm()
2706 unsigned imms) { in Ubfm()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 297 unsigned imms = val & 0x3f; in decodeLogicalImmediate() local
325 unsigned imms = val & 0x3f; in isValidDecodeLogicalImmediate() local
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| D | AArch64InstPrinter.cpp | 122 int64_t imms = Op3.getImm(); in printInst() local
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| /third_party/mesa3d/src/gallium/frontends/d3d10umd/ |
| D | ShaderTGSI.c | 213 struct ureg_src imms; member
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| /third_party/node/deps/v8/src/compiler/backend/ia32/ |
| D | instruction-selector-ia32.cc | 2879 uint32_t imms[kMaxImms]; in VisitI8x16Shuffle() local
3036 auto imms = m.ResolvedValue().immediate(); in VisitI8x16Swizzle() local
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| /third_party/node/deps/v8/src/compiler/backend/x64/ |
| D | instruction-selector-x64.cc | 3625 uint32_t imms[kMaxImms]; in VisitI8x16Shuffle() local
3800 auto imms = m.ResolvedValue().immediate(); in VisitI8x16Swizzle() local
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| D | code-generator-x64.cc | 1102 void SetupSimdImmediateInRegister(TurboAssembler* assembler, uint32_t* imms, in SetupSimdImmediateInRegister()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | assembler-arm64.cc | 983 int imms) { in bfm()
991 int imms) { in sbfm()
999 int imms) { in ubfm()
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| /third_party/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi_soa.c | 2994 LLVMValueRef imms[4]; in lp_emit_immediate_soa() local
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| D | instruction-selector-arm64.cc | 3950 auto imms = m.ResolvedValue().immediate(); in isSimdZero() local
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| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_exec.c | 1152 float4 *imms = REALLOC(mach->Imms, mach->ImmsReserved, newReserved * sizeof(float4)); in tgsi_exec_machine_bind_shader() local
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| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| D | liftoff-assembler-arm64.h | 2543 int64_t imms[2] = {0, 0}; in emit_i8x16_shuffle() local
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| /third_party/node/deps/v8/src/execution/arm/ |
| D | simulator-arm.cc | 4105 uint8_t imms[kSimd128Size]; in VmovImmediate() local
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| /third_party/node/deps/v8/src/wasm/baseline/x64/ |
| D | liftoff-assembler-x64.h | 2474 uint32_t imms[4]; in emit_i8x16_shuffle() local
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| /third_party/node/deps/v8/src/wasm/baseline/ia32/ |
| D | liftoff-assembler-ia32.h | 2865 uint32_t imms[4]; in emit_i8x16_shuffle() local
|