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1 // Copyright 2017 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #ifndef V8_WASM_BASELINE_LIFTOFF_ASSEMBLER_DEFS_H_
6 #define V8_WASM_BASELINE_LIFTOFF_ASSEMBLER_DEFS_H_
7 
8 #include "src/codegen/assembler-arch.h"
9 #include "src/codegen/reglist.h"
10 
11 namespace v8 {
12 namespace internal {
13 namespace wasm {
14 
15 #if V8_TARGET_ARCH_IA32
16 
17 // Omit ebx, which is the root register.
18 constexpr RegList kLiftoffAssemblerGpCacheRegs = {eax, ecx, edx, esi, edi};
19 
20 // Omit xmm7, which is the kScratchDoubleReg.
21 constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {xmm0, xmm1, xmm2, xmm3,
22                                                         xmm4, xmm5, xmm6};
23 
24 #elif V8_TARGET_ARCH_X64
25 
26 constexpr RegList kLiftoffAssemblerGpCacheRegs = {rax, rcx, rdx, rbx,
27                                                   rsi, rdi, r9};
28 
29 constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {xmm0, xmm1, xmm2, xmm3,
30                                                         xmm4, xmm5, xmm6, xmm7};
31 
32 #elif V8_TARGET_ARCH_MIPS
33 
34 constexpr RegList kLiftoffAssemblerGpCacheRegs = {a0, a1, a2, a3, t0, t1, t2,
35                                                   t3, t4, t5, t6, s7, v0, v1};
36 
37 constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {
38     f0, f2, f4, f6, f8, f10, f12, f14, f16, f18, f20, f22, f24};
39 
40 #elif V8_TARGET_ARCH_MIPS64
41 
42 constexpr RegList kLiftoffAssemblerGpCacheRegs = {a0, a1, a2, a3, a4, a5, a6,
43                                                   a7, t0, t1, t2, s7, v0, v1};
44 
45 constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {
46     f0, f2, f4, f6, f8, f10, f12, f14, f16, f18, f20, f22, f24, f26};
47 
48 #elif V8_TARGET_ARCH_LOONG64
49 
50 // t6-t8 and s3-s4: scratch registers, s6: root
51 constexpr RegList kLiftoffAssemblerGpCacheRegs = {a0, a1, a2, a3, a4, a5, a6,
52                                                   a7, t0, t1, t2, t3, t4, t5,
53                                                   s0, s1, s2, s5, s7, s8};
54 
55 // f29: zero, f30-f31: macro-assembler scratch float Registers.
56 constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {
57     f0,  f1,  f2,  f3,  f4,  f5,  f6,  f7,  f8,  f9,  f10, f11, f12, f13, f14,
58     f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26, f27, f28};
59 
60 #elif V8_TARGET_ARCH_ARM
61 
62 // r10: root, r11: fp, r12: ip, r13: sp, r14: lr, r15: pc.
63 constexpr RegList kLiftoffAssemblerGpCacheRegs = {r0, r1, r2, r3, r4,
64                                                   r5, r6, r7, r8, r9};
65 
66 // d13: zero, d14-d15: scratch
67 constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {
68     d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12};
69 
70 #elif V8_TARGET_ARCH_ARM64
71 
72 // x16: ip0, x17: ip1, x18: platform register, x26: root, x28: base, x29: fp,
73 // x30: lr, x31: xzr.
74 constexpr RegList kLiftoffAssemblerGpCacheRegs = {
75     x0,  x1,  x2,  x3,  x4,  x5,  x6,  x7,  x8,  x9,  x10, x11,
76     x12, x13, x14, x15, x19, x20, x21, x22, x23, x24, x25, x27};
77 
78 // d15: fp_zero, d30-d31: macro-assembler scratch V Registers.
79 constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {
80     d0,  d1,  d2,  d3,  d4,  d5,  d6,  d7,  d8,  d9,  d10, d11, d12, d13, d14,
81     d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29};
82 
83 #elif V8_TARGET_ARCH_S390X
84 
85 constexpr RegList kLiftoffAssemblerGpCacheRegs = {r2, r3, r4, r5,
86                                                   r6, r7, r8, cp};
87 
88 constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {
89     d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12};
90 
91 #elif V8_TARGET_ARCH_PPC64
92 
93 constexpr RegList kLiftoffAssemblerGpCacheRegs = {r3, r4, r5,  r6,  r7,
94                                                   r8, r9, r10, r11, cp};
95 
96 constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {
97     d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12};
98 
99 #elif V8_TARGET_ARCH_RISCV64
100 
101 // Any change of kLiftoffAssemblerGpCacheRegs also need to update
102 // kPushedGpRegs in frame-constants-riscv64.h
103 constexpr RegList kLiftoffAssemblerGpCacheRegs = {a0, a1, a2, a3, a4, a5,
104                                                   a6, a7, t0, t1, t2, s7};
105 
106 // Any change of kLiftoffAssemblerGpCacheRegs also need to update
107 // kPushedFpRegs in frame-constants-riscv64.h
108 constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {
109     ft1, ft2, ft3, ft4, ft5, ft6, ft7, fa0,  fa1, fa2,
110     fa3, fa4, fa5, fa6, fa7, ft8, ft9, ft10, ft11};
111 #else
112 
113 constexpr RegList kLiftoffAssemblerGpCacheRegs = RegList::FromBits(0xff);
114 
115 constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs =
116     DoubleRegList::FromBits(0xff);
117 
118 #endif
119 }  // namespace wasm
120 }  // namespace internal
121 }  // namespace v8
122 
123 #endif  // V8_WASM_BASELINE_LIFTOFF_ASSEMBLER_DEFS_H_
124