| /third_party/mesa3d/src/panfrost/bifrost/ |
| D | bi_lower_divergent_indirects.c | 90 unsigned *lanes = data; in bi_lower_divergent_indirects_impl() local
123 bi_lower_divergent_indirects(nir_shader *shader, unsigned lanes) in bi_lower_divergent_indirects()
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| /third_party/mesa3d/src/panfrost/bifrost/valhall/ |
| D | valhall.h | 80 bool lanes : 1; member
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| D | valhall.py | 103 …halfswizzle = False, widen = False, lanes = False, combine = False, lane = None, absneg = False, n… argument
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| /third_party/typescript/src/debug/ |
| D | dbg.ts | 398 const lanes: string[] = fill(Array(laneCount), ""); constant
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| /third_party/node/deps/v8/src/codegen/arm/ |
| D | assembler-arm.h | 1454 LoadStoreLaneParams(uint8_t laneidx, NeonSize sz, int lanes) in LoadStoreLaneParams()
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| /third_party/vixl/src/aarch64/ |
| D | registers-aarch64.h | 620 static EncodedSize EncodeLaneSizeInBits(int size_in_bits, int lanes) { in EncodeLaneSizeInBits()
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| D | logic-aarch64.cc | 1180 unsigned lanes = LaneCountFromFormat(vform); in sminmaxp() local
1386 unsigned lanes = LaneCountFromFormat(vform); in uminmaxp() local
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| D | assembler-mips64.h | 1961 LoadStoreLaneParams(uint8_t laneidx, MSASize sz, int lanes) in LoadStoreLaneParams()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_pipeline_rt.c | 1397 unsigned lanes = device->physical_device->rt_wave_size; in build_traversal_shader() local
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| /third_party/node/deps/v8/src/codegen/riscv64/ |
| D | assembler-riscv64.h | 1822 LoadStoreLaneParams(uint8_t laneidx, int sz, int lanes) in LoadStoreLaneParams()
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| /third_party/node/deps/v8/src/execution/mips/ |
| D | simulator-mips.cc | 6397 #define BZ_DF(witdh, lanes) \ in DecodeTypeImmediate() argument
6427 #define BNZ_DF(witdh, lanes) \ in DecodeTypeImmediate() argument
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| /third_party/node/deps/v8/src/compiler/backend/ia32/ |
| D | code-generator-ia32.cc | 3053 uint32_t lanes = i.InputUint32(j); in AssembleArchInstruction() local
3065 uint32_t lanes = i.InputUint32(j); in AssembleArchInstruction() local
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| /third_party/node/deps/v8/src/compiler/backend/x64/ |
| D | code-generator-x64.cc | 3840 uint32_t lanes = i.InputUint32(j); in AssembleArchInstruction() local
3856 uint32_t lanes = i.InputUint32(j); in AssembleArchInstruction() local
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| /third_party/node/deps/v8/src/execution/mips64/ |
| D | simulator-mips64.cc | 6698 #define BZ_DF(witdh, lanes) \ in DecodeTypeImmediate() argument
6728 #define BNZ_DF(witdh, lanes) \ in DecodeTypeImmediate() argument
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| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir.h | 964 unsigned lanes : 4; variable
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| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-logic-arm64.cc | 1127 int lanes = LaneCountFromFormat(vform); in SMinMaxP() local
1277 int lanes = LaneCountFromFormat(vform); in UMinMaxP() local
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| /third_party/skia/third_party/externals/swiftshader/src/Pipeline/ |
| D | SpirvShaderDebugger.cpp | 1342 PerLaneVariables lanes; member
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| D | code-generator-arm64.cc | 2642 int lanes = i.InputInt32(1); in AssembleArchInstruction() local
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| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| D | code-generator-arm.cc | 2861 int lanes = kSimd128Size >> size; in AssembleArchInstruction() local
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| /third_party/node/deps/simdutf/ |
| D | simdutf.cpp | 17324 const int lanes = sizeof(uint8x16_t); in utf8_length_from_latin1() local
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| /third_party/vixl/src/aarch32/ |
| D | disasm-aarch32.cc | 87 DecodeNeonAndAlign(int lanes, SpacingType spacing, Alignment align) in DecodeNeonAndAlign()
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| /third_party/libbpf/.github/actions/build-selftests/ |
| D | vmlinux.h | 51372 u32 lanes; member
51422 u64 lanes[8]; member
59786 unsigned int lanes; member
59820 unsigned char lanes; member
72048 u32 lanes; member
83352 u8 lanes; member
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