| /third_party/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 785 __ ld1(v18.V16B(), v19.V16B(), v20.V16B(), v21.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
786 __ ld1(v23.V16B(), in GenerateTestSequenceNEON() local
791 __ ld1(v5.V16B(), in GenerateTestSequenceNEON() local
796 __ ld1(v18.V16B(), v19.V16B(), v20.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
797 __ ld1(v13.V16B(), v14.V16B(), v15.V16B(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
798 __ ld1(v19.V16B(), v20.V16B(), v21.V16B(), MemOperand(x1, 48, PostIndex)); in GenerateTestSequenceNEON() local
799 __ ld1(v17.V16B(), v18.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
800 __ ld1(v20.V16B(), v21.V16B(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
801 __ ld1(v28.V16B(), v29.V16B(), MemOperand(x1, 32, PostIndex)); in GenerateTestSequenceNEON() local
802 __ ld1(v29.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
[all …]
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| D | test-assembler-sve-aarch64.cc | 8811 Ld1Macro ld1, in Ldff1Helper()
9824 Ld1Macro ld1, in GatherLoadScalarPlusVectorHelper()
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| /third_party/mesa3d/src/gallium/drivers/llvmpipe/ |
| D | lp_linear_sampler.c | 533 __m128i ld1, ld2, ld3; in fetch_bgra_clamp_linear() local
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | assembler-arm64.cc | 2342 void Assembler::ld1(const VRegister& vt, const MemOperand& src) { in ld1() function in v8::internal::Assembler
2346 void Assembler::ld1(const VRegister& vt, const VRegister& vt2, in ld1() function in v8::internal::Assembler
2354 void Assembler::ld1(const VRegister& vt, const VRegister& vt2, in ld1() function in v8::internal::Assembler
2363 void Assembler::ld1(const VRegister& vt, const VRegister& vt2, in ld1() function in v8::internal::Assembler
2588 void Assembler::ld1(const VRegister& vt, int lane, const MemOperand& src) { in ld1() function in v8::internal::Assembler
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| /third_party/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 2051 void Assembler::ld1(const VRegister& vt, const MemOperand& src) { in ld1() function in vixl::aarch64::Assembler
2057 void Assembler::ld1(const VRegister& vt, in ld1() function in vixl::aarch64::Assembler
2068 void Assembler::ld1(const VRegister& vt, in ld1() function in vixl::aarch64::Assembler
2080 void Assembler::ld1(const VRegister& vt, in ld1() function in vixl::aarch64::Assembler
2362 void Assembler::ld1(const VRegister& vt, int lane, const MemOperand& src) { in ld1() function in vixl::aarch64::Assembler
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| D | logic-aarch64.cc | 170 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1() function in vixl::aarch64::Simulator
179 void Simulator::ld1(VectorFormat vform, in ld1() function in vixl::aarch64::Simulator
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| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_peephole.cpp | 3983 DeadCodeElim::checkSplitLoad(Instruction *ld1) in checkSplitLoad()
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| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-logic-arm64.cc | 346 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1() function in v8::internal::Simulator
354 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, int index, in ld1() function in v8::internal::Simulator
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| D | code-generator-arm64.cc | 2779 __ ld1(i.OutputSimd128Register().Format(f), laneidx, i.MemoryOperand(2)); in AssembleArchInstruction() local
|