1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
56 #include "lib/eq.h"
57 #include "fs_core.h"
58 #include "lib/mpfs.h"
59 #include "eswitch.h"
60 #include "devlink.h"
61 #include "fw_reset.h"
62 #include "lib/mlx5.h"
63 #include "fpga/core.h"
64 #include "fpga/ipsec.h"
65 #include "accel/ipsec.h"
66 #include "accel/tls.h"
67 #include "lib/clock.h"
68 #include "lib/vxlan.h"
69 #include "lib/geneve.h"
70 #include "lib/devcom.h"
71 #include "lib/pci_vsc.h"
72 #include "diag/fw_tracer.h"
73 #include "ecpf.h"
74 #include "lib/hv_vhca.h"
75 #include "diag/rsc_dump.h"
76
77 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
78 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
79 MODULE_LICENSE("Dual BSD/GPL");
80 MODULE_VERSION(DRIVER_VERSION);
81
82 unsigned int mlx5_core_debug_mask;
83 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
84 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
85
86 #define MLX5_DEFAULT_PROF 2
87 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
88 module_param_named(prof_sel, prof_sel, uint, 0444);
89 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
90
91 static u32 sw_owner_id[4];
92
93 enum {
94 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
95 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
96 };
97
98 static struct mlx5_profile profile[] = {
99 [0] = {
100 .mask = 0,
101 },
102 [1] = {
103 .mask = MLX5_PROF_MASK_QP_SIZE,
104 .log_max_qp = 12,
105 },
106 [2] = {
107 .mask = MLX5_PROF_MASK_QP_SIZE |
108 MLX5_PROF_MASK_MR_CACHE,
109 .log_max_qp = 18,
110 .mr_cache[0] = {
111 .size = 500,
112 .limit = 250
113 },
114 .mr_cache[1] = {
115 .size = 500,
116 .limit = 250
117 },
118 .mr_cache[2] = {
119 .size = 500,
120 .limit = 250
121 },
122 .mr_cache[3] = {
123 .size = 500,
124 .limit = 250
125 },
126 .mr_cache[4] = {
127 .size = 500,
128 .limit = 250
129 },
130 .mr_cache[5] = {
131 .size = 500,
132 .limit = 250
133 },
134 .mr_cache[6] = {
135 .size = 500,
136 .limit = 250
137 },
138 .mr_cache[7] = {
139 .size = 500,
140 .limit = 250
141 },
142 .mr_cache[8] = {
143 .size = 500,
144 .limit = 250
145 },
146 .mr_cache[9] = {
147 .size = 500,
148 .limit = 250
149 },
150 .mr_cache[10] = {
151 .size = 500,
152 .limit = 250
153 },
154 .mr_cache[11] = {
155 .size = 500,
156 .limit = 250
157 },
158 .mr_cache[12] = {
159 .size = 64,
160 .limit = 32
161 },
162 .mr_cache[13] = {
163 .size = 32,
164 .limit = 16
165 },
166 .mr_cache[14] = {
167 .size = 16,
168 .limit = 8
169 },
170 .mr_cache[15] = {
171 .size = 8,
172 .limit = 4
173 },
174 },
175 };
176
177 #define FW_INIT_TIMEOUT_MILI 2000
178 #define FW_INIT_WAIT_MS 2
179 #define FW_PRE_INIT_TIMEOUT_MILI 120000
180 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
181
fw_initializing(struct mlx5_core_dev * dev)182 static int fw_initializing(struct mlx5_core_dev *dev)
183 {
184 return ioread32be(&dev->iseg->initializing) >> 31;
185 }
186
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)187 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
188 u32 warn_time_mili)
189 {
190 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
191 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
192 int err = 0;
193
194 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL);
195
196 while (fw_initializing(dev)) {
197 if (time_after(jiffies, end)) {
198 err = -EBUSY;
199 break;
200 }
201 if (warn_time_mili && time_after(jiffies, warn)) {
202 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
203 jiffies_to_msecs(end - warn) / 1000);
204 warn = jiffies + msecs_to_jiffies(warn_time_mili);
205 }
206 msleep(FW_INIT_WAIT_MS);
207 }
208
209 return err;
210 }
211
mlx5_set_driver_version(struct mlx5_core_dev * dev)212 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
213 {
214 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
215 driver_version);
216 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
217 int remaining_size = driver_ver_sz;
218 char *string;
219
220 if (!MLX5_CAP_GEN(dev, driver_version))
221 return;
222
223 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
224
225 strncpy(string, "Linux", remaining_size);
226
227 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
228 strncat(string, ",", remaining_size);
229
230 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
231 strncat(string, DRIVER_NAME, remaining_size);
232
233 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
234 strncat(string, ",", remaining_size);
235
236 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
237
238 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
239 (u8)((LINUX_VERSION_CODE >> 16) & 0xff), (u8)((LINUX_VERSION_CODE >> 8) & 0xff),
240 (u16)(LINUX_VERSION_CODE & 0xffff));
241
242 /*Send the command*/
243 MLX5_SET(set_driver_version_in, in, opcode,
244 MLX5_CMD_OP_SET_DRIVER_VERSION);
245
246 mlx5_cmd_exec_in(dev, set_driver_version, in);
247 }
248
set_dma_caps(struct pci_dev * pdev)249 static int set_dma_caps(struct pci_dev *pdev)
250 {
251 int err;
252
253 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
254 if (err) {
255 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
256 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
257 if (err) {
258 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
259 return err;
260 }
261 }
262
263 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
264 if (err) {
265 dev_warn(&pdev->dev,
266 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
267 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
268 if (err) {
269 dev_err(&pdev->dev,
270 "Can't set consistent PCI DMA mask, aborting\n");
271 return err;
272 }
273 }
274
275 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
276 return err;
277 }
278
mlx5_pci_enable_device(struct mlx5_core_dev * dev)279 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
280 {
281 struct pci_dev *pdev = dev->pdev;
282 int err = 0;
283
284 mutex_lock(&dev->pci_status_mutex);
285 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
286 err = pci_enable_device(pdev);
287 if (!err)
288 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
289 }
290 mutex_unlock(&dev->pci_status_mutex);
291
292 return err;
293 }
294
mlx5_pci_disable_device(struct mlx5_core_dev * dev)295 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
296 {
297 struct pci_dev *pdev = dev->pdev;
298
299 mutex_lock(&dev->pci_status_mutex);
300 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
301 pci_disable_device(pdev);
302 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
303 }
304 mutex_unlock(&dev->pci_status_mutex);
305 }
306
request_bar(struct pci_dev * pdev)307 static int request_bar(struct pci_dev *pdev)
308 {
309 int err = 0;
310
311 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
312 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
313 return -ENODEV;
314 }
315
316 err = pci_request_regions(pdev, DRIVER_NAME);
317 if (err)
318 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
319
320 return err;
321 }
322
release_bar(struct pci_dev * pdev)323 static void release_bar(struct pci_dev *pdev)
324 {
325 pci_release_regions(pdev);
326 }
327
328 struct mlx5_reg_host_endianness {
329 u8 he;
330 u8 rsvd[15];
331 };
332
333 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
334
335 enum {
336 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
337 MLX5_DEV_CAP_FLAG_DCT,
338 };
339
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)340 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
341 {
342 switch (size) {
343 case 128:
344 return 0;
345 case 256:
346 return 1;
347 case 512:
348 return 2;
349 case 1024:
350 return 3;
351 case 2048:
352 return 4;
353 case 4096:
354 return 5;
355 default:
356 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
357 return 0;
358 }
359 }
360
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)361 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
362 enum mlx5_cap_type cap_type,
363 enum mlx5_cap_mode cap_mode)
364 {
365 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
366 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
367 void *out, *hca_caps;
368 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
369 int err;
370
371 memset(in, 0, sizeof(in));
372 out = kzalloc(out_sz, GFP_KERNEL);
373 if (!out)
374 return -ENOMEM;
375
376 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
377 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
378 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
379 if (err) {
380 mlx5_core_warn(dev,
381 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
382 cap_type, cap_mode, err);
383 goto query_ex;
384 }
385
386 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
387
388 switch (cap_mode) {
389 case HCA_CAP_OPMOD_GET_MAX:
390 memcpy(dev->caps.hca_max[cap_type], hca_caps,
391 MLX5_UN_SZ_BYTES(hca_cap_union));
392 break;
393 case HCA_CAP_OPMOD_GET_CUR:
394 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
395 MLX5_UN_SZ_BYTES(hca_cap_union));
396 break;
397 default:
398 mlx5_core_warn(dev,
399 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
400 cap_type, cap_mode);
401 err = -EINVAL;
402 break;
403 }
404 query_ex:
405 kfree(out);
406 return err;
407 }
408
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)409 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
410 {
411 int ret;
412
413 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
414 if (ret)
415 return ret;
416 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
417 }
418
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)419 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
420 {
421 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
422 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
423 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
424 }
425
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)426 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
427 {
428 void *set_hca_cap;
429 int req_endianness;
430 int err;
431
432 if (!MLX5_CAP_GEN(dev, atomic))
433 return 0;
434
435 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
436 if (err)
437 return err;
438
439 req_endianness =
440 MLX5_CAP_ATOMIC(dev,
441 supported_atomic_req_8B_endianness_mode_1);
442
443 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
444 return 0;
445
446 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
447
448 /* Set requestor to host endianness */
449 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
450 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
451
452 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
453 }
454
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)455 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
456 {
457 void *set_hca_cap;
458 bool do_set = false;
459 int err;
460
461 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
462 !MLX5_CAP_GEN(dev, pg))
463 return 0;
464
465 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
466 if (err)
467 return err;
468
469 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
470 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
471 MLX5_ST_SZ_BYTES(odp_cap));
472
473 #define ODP_CAP_SET_MAX(dev, field) \
474 do { \
475 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
476 if (_res) { \
477 do_set = true; \
478 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
479 } \
480 } while (0)
481
482 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
483 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
484 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
485 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
486 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
487 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
488 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
489 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
490 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
491 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
492 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
493 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
494 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
495 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
496
497 if (!do_set)
498 return 0;
499
500 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
501 }
502
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)503 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
504 {
505 struct mlx5_profile *prof = dev->profile;
506 void *set_hca_cap;
507 int err;
508
509 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
510 if (err)
511 return err;
512
513 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
514 capability);
515 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
516 MLX5_ST_SZ_BYTES(cmd_hca_cap));
517
518 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
519 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
520 128);
521 /* we limit the size of the pkey table to 128 entries for now */
522 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
523 to_fw_pkey_sz(dev, 128));
524
525 /* Check log_max_qp from HCA caps to set in current profile */
526 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
527 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
528 profile[prof_sel].log_max_qp,
529 MLX5_CAP_GEN_MAX(dev, log_max_qp));
530 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
531 }
532 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
533 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
534 prof->log_max_qp);
535
536 /* disable cmdif checksum */
537 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
538
539 /* Enable 4K UAR only when HCA supports it and page size is bigger
540 * than 4K.
541 */
542 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
543 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
544
545 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
546
547 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
548 MLX5_SET(cmd_hca_cap,
549 set_hca_cap,
550 cache_line_128byte,
551 cache_line_size() >= 128 ? 1 : 0);
552
553 if (MLX5_CAP_GEN_MAX(dev, dct))
554 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
555
556 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
557 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
558
559 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
560 MLX5_SET(cmd_hca_cap,
561 set_hca_cap,
562 num_vhca_ports,
563 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
564
565 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
566 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
567
568 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
569 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
570
571 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
572 }
573
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)574 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
575 {
576 void *set_hca_cap;
577 int err;
578
579 if (!MLX5_CAP_GEN(dev, roce))
580 return 0;
581
582 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
583 if (err)
584 return err;
585
586 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
587 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
588 return 0;
589
590 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
591 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE],
592 MLX5_ST_SZ_BYTES(roce_cap));
593 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
594
595 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
596 return err;
597 }
598
set_hca_cap(struct mlx5_core_dev * dev)599 static int set_hca_cap(struct mlx5_core_dev *dev)
600 {
601 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
602 void *set_ctx;
603 int err;
604
605 set_ctx = kzalloc(set_sz, GFP_KERNEL);
606 if (!set_ctx)
607 return -ENOMEM;
608
609 err = handle_hca_cap(dev, set_ctx);
610 if (err) {
611 mlx5_core_err(dev, "handle_hca_cap failed\n");
612 goto out;
613 }
614
615 memset(set_ctx, 0, set_sz);
616 err = handle_hca_cap_atomic(dev, set_ctx);
617 if (err) {
618 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
619 goto out;
620 }
621
622 memset(set_ctx, 0, set_sz);
623 err = handle_hca_cap_odp(dev, set_ctx);
624 if (err) {
625 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
626 goto out;
627 }
628
629 memset(set_ctx, 0, set_sz);
630 err = handle_hca_cap_roce(dev, set_ctx);
631 if (err) {
632 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
633 goto out;
634 }
635
636 out:
637 kfree(set_ctx);
638 return err;
639 }
640
set_hca_ctrl(struct mlx5_core_dev * dev)641 static int set_hca_ctrl(struct mlx5_core_dev *dev)
642 {
643 struct mlx5_reg_host_endianness he_in;
644 struct mlx5_reg_host_endianness he_out;
645 int err;
646
647 if (!mlx5_core_is_pf(dev))
648 return 0;
649
650 memset(&he_in, 0, sizeof(he_in));
651 he_in.he = MLX5_SET_HOST_ENDIANNESS;
652 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
653 &he_out, sizeof(he_out),
654 MLX5_REG_HOST_ENDIANNESS, 0, 1);
655 return err;
656 }
657
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)658 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
659 {
660 int ret = 0;
661
662 /* Disable local_lb by default */
663 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
664 ret = mlx5_nic_vport_update_local_lb(dev, false);
665
666 return ret;
667 }
668
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)669 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
670 {
671 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
672
673 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
674 MLX5_SET(enable_hca_in, in, function_id, func_id);
675 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
676 dev->caps.embedded_cpu);
677 return mlx5_cmd_exec_in(dev, enable_hca, in);
678 }
679
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)680 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
681 {
682 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
683
684 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
685 MLX5_SET(disable_hca_in, in, function_id, func_id);
686 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
687 dev->caps.embedded_cpu);
688 return mlx5_cmd_exec_in(dev, disable_hca, in);
689 }
690
mlx5_core_set_issi(struct mlx5_core_dev * dev)691 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
692 {
693 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
694 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
695 u32 sup_issi;
696 int err;
697
698 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
699 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
700 if (err) {
701 u32 syndrome;
702 u8 status;
703
704 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
705 if (!status || syndrome == MLX5_DRIVER_SYND) {
706 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
707 err, status, syndrome);
708 return err;
709 }
710
711 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
712 dev->issi = 0;
713 return 0;
714 }
715
716 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
717
718 if (sup_issi & (1 << 1)) {
719 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
720
721 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
722 MLX5_SET(set_issi_in, set_in, current_issi, 1);
723 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
724 if (err) {
725 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
726 err);
727 return err;
728 }
729
730 dev->issi = 1;
731
732 return 0;
733 } else if (sup_issi & (1 << 0) || !sup_issi) {
734 return 0;
735 }
736
737 return -EOPNOTSUPP;
738 }
739
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)740 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
741 const struct pci_device_id *id)
742 {
743 struct mlx5_priv *priv = &dev->priv;
744 int err = 0;
745
746 mutex_init(&dev->pci_status_mutex);
747 pci_set_drvdata(dev->pdev, dev);
748
749 dev->bar_addr = pci_resource_start(pdev, 0);
750 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
751
752 err = mlx5_pci_enable_device(dev);
753 if (err) {
754 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
755 return err;
756 }
757
758 err = request_bar(pdev);
759 if (err) {
760 mlx5_core_err(dev, "error requesting BARs, aborting\n");
761 goto err_disable;
762 }
763
764 pci_set_master(pdev);
765
766 err = set_dma_caps(pdev);
767 if (err) {
768 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
769 goto err_clr_master;
770 }
771
772 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
773 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
774 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
775 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
776
777 dev->iseg_base = dev->bar_addr;
778 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
779 if (!dev->iseg) {
780 err = -ENOMEM;
781 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
782 goto err_clr_master;
783 }
784
785 mlx5_pci_vsc_init(dev);
786 return 0;
787
788 err_clr_master:
789 pci_clear_master(dev->pdev);
790 release_bar(dev->pdev);
791 err_disable:
792 mlx5_pci_disable_device(dev);
793 return err;
794 }
795
mlx5_pci_close(struct mlx5_core_dev * dev)796 static void mlx5_pci_close(struct mlx5_core_dev *dev)
797 {
798 /* health work might still be active, and it needs pci bar in
799 * order to know the NIC state. Therefore, drain the health WQ
800 * before removing the pci bars
801 */
802 mlx5_drain_health_wq(dev);
803 iounmap(dev->iseg);
804 pci_clear_master(dev->pdev);
805 release_bar(dev->pdev);
806 mlx5_pci_disable_device(dev);
807 }
808
mlx5_init_once(struct mlx5_core_dev * dev)809 static int mlx5_init_once(struct mlx5_core_dev *dev)
810 {
811 int err;
812
813 dev->priv.devcom = mlx5_devcom_register_device(dev);
814 if (IS_ERR(dev->priv.devcom))
815 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
816 dev->priv.devcom);
817
818 err = mlx5_query_board_id(dev);
819 if (err) {
820 mlx5_core_err(dev, "query board id failed\n");
821 goto err_devcom;
822 }
823
824 err = mlx5_irq_table_init(dev);
825 if (err) {
826 mlx5_core_err(dev, "failed to initialize irq table\n");
827 goto err_devcom;
828 }
829
830 err = mlx5_eq_table_init(dev);
831 if (err) {
832 mlx5_core_err(dev, "failed to initialize eq\n");
833 goto err_irq_cleanup;
834 }
835
836 err = mlx5_events_init(dev);
837 if (err) {
838 mlx5_core_err(dev, "failed to initialize events\n");
839 goto err_eq_cleanup;
840 }
841
842 err = mlx5_fw_reset_init(dev);
843 if (err) {
844 mlx5_core_err(dev, "failed to initialize fw reset events\n");
845 goto err_events_cleanup;
846 }
847
848 mlx5_cq_debugfs_init(dev);
849
850 mlx5_init_reserved_gids(dev);
851
852 mlx5_init_clock(dev);
853
854 dev->vxlan = mlx5_vxlan_create(dev);
855 dev->geneve = mlx5_geneve_create(dev);
856
857 err = mlx5_init_rl_table(dev);
858 if (err) {
859 mlx5_core_err(dev, "Failed to init rate limiting\n");
860 goto err_tables_cleanup;
861 }
862
863 err = mlx5_mpfs_init(dev);
864 if (err) {
865 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
866 goto err_rl_cleanup;
867 }
868
869 err = mlx5_sriov_init(dev);
870 if (err) {
871 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
872 goto err_mpfs_cleanup;
873 }
874
875 err = mlx5_eswitch_init(dev);
876 if (err) {
877 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
878 goto err_sriov_cleanup;
879 }
880
881 err = mlx5_fpga_init(dev);
882 if (err) {
883 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
884 goto err_eswitch_cleanup;
885 }
886
887 dev->dm = mlx5_dm_create(dev);
888 if (IS_ERR(dev->dm))
889 mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm));
890
891 dev->tracer = mlx5_fw_tracer_create(dev);
892 dev->hv_vhca = mlx5_hv_vhca_create(dev);
893 dev->rsc_dump = mlx5_rsc_dump_create(dev);
894
895 return 0;
896
897 err_eswitch_cleanup:
898 mlx5_eswitch_cleanup(dev->priv.eswitch);
899 err_sriov_cleanup:
900 mlx5_sriov_cleanup(dev);
901 err_mpfs_cleanup:
902 mlx5_mpfs_cleanup(dev);
903 err_rl_cleanup:
904 mlx5_cleanup_rl_table(dev);
905 err_tables_cleanup:
906 mlx5_geneve_destroy(dev->geneve);
907 mlx5_vxlan_destroy(dev->vxlan);
908 mlx5_cleanup_clock(dev);
909 mlx5_cleanup_reserved_gids(dev);
910 mlx5_cq_debugfs_cleanup(dev);
911 mlx5_fw_reset_cleanup(dev);
912 err_events_cleanup:
913 mlx5_events_cleanup(dev);
914 err_eq_cleanup:
915 mlx5_eq_table_cleanup(dev);
916 err_irq_cleanup:
917 mlx5_irq_table_cleanup(dev);
918 err_devcom:
919 mlx5_devcom_unregister_device(dev->priv.devcom);
920
921 return err;
922 }
923
mlx5_cleanup_once(struct mlx5_core_dev * dev)924 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
925 {
926 mlx5_rsc_dump_destroy(dev);
927 mlx5_hv_vhca_destroy(dev->hv_vhca);
928 mlx5_fw_tracer_destroy(dev->tracer);
929 mlx5_dm_cleanup(dev);
930 mlx5_fpga_cleanup(dev);
931 mlx5_eswitch_cleanup(dev->priv.eswitch);
932 mlx5_sriov_cleanup(dev);
933 mlx5_mpfs_cleanup(dev);
934 mlx5_cleanup_rl_table(dev);
935 mlx5_geneve_destroy(dev->geneve);
936 mlx5_vxlan_destroy(dev->vxlan);
937 mlx5_cleanup_clock(dev);
938 mlx5_cleanup_reserved_gids(dev);
939 mlx5_cq_debugfs_cleanup(dev);
940 mlx5_fw_reset_cleanup(dev);
941 mlx5_events_cleanup(dev);
942 mlx5_eq_table_cleanup(dev);
943 mlx5_irq_table_cleanup(dev);
944 mlx5_devcom_unregister_device(dev->priv.devcom);
945 }
946
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot)947 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
948 {
949 int err;
950
951 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
952 fw_rev_min(dev), fw_rev_sub(dev));
953
954 /* Only PFs hold the relevant PCIe information for this query */
955 if (mlx5_core_is_pf(dev))
956 pcie_print_link_status(dev->pdev);
957
958 /* wait for firmware to accept initialization segments configurations
959 */
960 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL);
961 if (err) {
962 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
963 FW_PRE_INIT_TIMEOUT_MILI);
964 return err;
965 }
966
967 err = mlx5_cmd_init(dev);
968 if (err) {
969 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
970 return err;
971 }
972
973 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
974 if (err) {
975 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
976 FW_INIT_TIMEOUT_MILI);
977 goto err_cmd_cleanup;
978 }
979
980 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
981 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
982
983 err = mlx5_core_enable_hca(dev, 0);
984 if (err) {
985 mlx5_core_err(dev, "enable hca failed\n");
986 goto err_cmd_cleanup;
987 }
988
989 err = mlx5_core_set_issi(dev);
990 if (err) {
991 mlx5_core_err(dev, "failed to set issi\n");
992 goto err_disable_hca;
993 }
994
995 err = mlx5_satisfy_startup_pages(dev, 1);
996 if (err) {
997 mlx5_core_err(dev, "failed to allocate boot pages\n");
998 goto err_disable_hca;
999 }
1000
1001 err = set_hca_ctrl(dev);
1002 if (err) {
1003 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1004 goto reclaim_boot_pages;
1005 }
1006
1007 err = set_hca_cap(dev);
1008 if (err) {
1009 mlx5_core_err(dev, "set_hca_cap failed\n");
1010 goto reclaim_boot_pages;
1011 }
1012
1013 err = mlx5_satisfy_startup_pages(dev, 0);
1014 if (err) {
1015 mlx5_core_err(dev, "failed to allocate init pages\n");
1016 goto reclaim_boot_pages;
1017 }
1018
1019 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1020 if (err) {
1021 mlx5_core_err(dev, "init hca failed\n");
1022 goto reclaim_boot_pages;
1023 }
1024
1025 mlx5_set_driver_version(dev);
1026
1027 mlx5_start_health_poll(dev);
1028
1029 err = mlx5_query_hca_caps(dev);
1030 if (err) {
1031 mlx5_core_err(dev, "query hca failed\n");
1032 goto stop_health;
1033 }
1034
1035 return 0;
1036
1037 stop_health:
1038 mlx5_stop_health_poll(dev, boot);
1039 reclaim_boot_pages:
1040 mlx5_reclaim_startup_pages(dev);
1041 err_disable_hca:
1042 mlx5_core_disable_hca(dev, 0);
1043 err_cmd_cleanup:
1044 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1045 mlx5_cmd_cleanup(dev);
1046
1047 return err;
1048 }
1049
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1050 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1051 {
1052 int err;
1053
1054 mlx5_stop_health_poll(dev, boot);
1055 err = mlx5_cmd_teardown_hca(dev);
1056 if (err) {
1057 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1058 return err;
1059 }
1060 mlx5_reclaim_startup_pages(dev);
1061 mlx5_core_disable_hca(dev, 0);
1062 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1063 mlx5_cmd_cleanup(dev);
1064
1065 return 0;
1066 }
1067
mlx5_load(struct mlx5_core_dev * dev)1068 static int mlx5_load(struct mlx5_core_dev *dev)
1069 {
1070 int err;
1071
1072 dev->priv.uar = mlx5_get_uars_page(dev);
1073 if (IS_ERR(dev->priv.uar)) {
1074 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1075 err = PTR_ERR(dev->priv.uar);
1076 return err;
1077 }
1078
1079 mlx5_events_start(dev);
1080 mlx5_pagealloc_start(dev);
1081
1082 err = mlx5_irq_table_create(dev);
1083 if (err) {
1084 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1085 goto err_irq_table;
1086 }
1087
1088 err = mlx5_eq_table_create(dev);
1089 if (err) {
1090 mlx5_core_err(dev, "Failed to create EQs\n");
1091 goto err_eq_table;
1092 }
1093
1094 err = mlx5_fw_tracer_init(dev->tracer);
1095 if (err) {
1096 mlx5_core_err(dev, "Failed to init FW tracer\n");
1097 goto err_fw_tracer;
1098 }
1099
1100 mlx5_fw_reset_events_start(dev);
1101 mlx5_hv_vhca_init(dev->hv_vhca);
1102
1103 err = mlx5_rsc_dump_init(dev);
1104 if (err) {
1105 mlx5_core_err(dev, "Failed to init Resource dump\n");
1106 goto err_rsc_dump;
1107 }
1108
1109 err = mlx5_fpga_device_start(dev);
1110 if (err) {
1111 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1112 goto err_fpga_start;
1113 }
1114
1115 mlx5_accel_ipsec_init(dev);
1116
1117 err = mlx5_accel_tls_init(dev);
1118 if (err) {
1119 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1120 goto err_tls_start;
1121 }
1122
1123 err = mlx5_init_fs(dev);
1124 if (err) {
1125 mlx5_core_err(dev, "Failed to init flow steering\n");
1126 goto err_fs;
1127 }
1128
1129 err = mlx5_core_set_hca_defaults(dev);
1130 if (err) {
1131 mlx5_core_err(dev, "Failed to set hca defaults\n");
1132 goto err_sriov;
1133 }
1134
1135 err = mlx5_sriov_attach(dev);
1136 if (err) {
1137 mlx5_core_err(dev, "sriov init failed %d\n", err);
1138 goto err_sriov;
1139 }
1140
1141 err = mlx5_ec_init(dev);
1142 if (err) {
1143 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1144 goto err_ec;
1145 }
1146
1147 return 0;
1148
1149 err_ec:
1150 mlx5_sriov_detach(dev);
1151 err_sriov:
1152 mlx5_cleanup_fs(dev);
1153 err_fs:
1154 mlx5_accel_tls_cleanup(dev);
1155 err_tls_start:
1156 mlx5_accel_ipsec_cleanup(dev);
1157 mlx5_fpga_device_stop(dev);
1158 err_fpga_start:
1159 mlx5_rsc_dump_cleanup(dev);
1160 err_rsc_dump:
1161 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1162 mlx5_fw_reset_events_stop(dev);
1163 mlx5_fw_tracer_cleanup(dev->tracer);
1164 err_fw_tracer:
1165 mlx5_eq_table_destroy(dev);
1166 err_eq_table:
1167 mlx5_irq_table_destroy(dev);
1168 err_irq_table:
1169 mlx5_pagealloc_stop(dev);
1170 mlx5_events_stop(dev);
1171 mlx5_put_uars_page(dev, dev->priv.uar);
1172 return err;
1173 }
1174
mlx5_unload(struct mlx5_core_dev * dev)1175 static void mlx5_unload(struct mlx5_core_dev *dev)
1176 {
1177 mlx5_ec_cleanup(dev);
1178 mlx5_sriov_detach(dev);
1179 mlx5_cleanup_fs(dev);
1180 mlx5_accel_ipsec_cleanup(dev);
1181 mlx5_accel_tls_cleanup(dev);
1182 mlx5_fpga_device_stop(dev);
1183 mlx5_rsc_dump_cleanup(dev);
1184 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1185 mlx5_fw_reset_events_stop(dev);
1186 mlx5_fw_tracer_cleanup(dev->tracer);
1187 mlx5_eq_table_destroy(dev);
1188 mlx5_irq_table_destroy(dev);
1189 mlx5_pagealloc_stop(dev);
1190 mlx5_events_stop(dev);
1191 mlx5_put_uars_page(dev, dev->priv.uar);
1192 }
1193
mlx5_load_one(struct mlx5_core_dev * dev,bool boot)1194 int mlx5_load_one(struct mlx5_core_dev *dev, bool boot)
1195 {
1196 int err = 0;
1197
1198 mutex_lock(&dev->intf_state_mutex);
1199 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1200 mlx5_core_warn(dev, "interface is up, NOP\n");
1201 goto out;
1202 }
1203 /* remove any previous indication of internal error */
1204 dev->state = MLX5_DEVICE_STATE_UP;
1205
1206 err = mlx5_function_setup(dev, boot);
1207 if (err)
1208 goto err_function;
1209
1210 if (boot) {
1211 err = mlx5_init_once(dev);
1212 if (err) {
1213 mlx5_core_err(dev, "sw objs init failed\n");
1214 goto function_teardown;
1215 }
1216 }
1217
1218 err = mlx5_load(dev);
1219 if (err)
1220 goto err_load;
1221
1222 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1223
1224 if (boot) {
1225 err = mlx5_devlink_register(priv_to_devlink(dev), dev->device);
1226 if (err)
1227 goto err_devlink_reg;
1228 mlx5_register_device(dev);
1229 } else {
1230 mlx5_attach_device(dev);
1231 }
1232
1233 mutex_unlock(&dev->intf_state_mutex);
1234 return 0;
1235
1236 err_devlink_reg:
1237 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1238 mlx5_unload(dev);
1239 err_load:
1240 if (boot)
1241 mlx5_cleanup_once(dev);
1242 function_teardown:
1243 mlx5_function_teardown(dev, boot);
1244 err_function:
1245 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1246 out:
1247 mutex_unlock(&dev->intf_state_mutex);
1248 return err;
1249 }
1250
mlx5_unload_one(struct mlx5_core_dev * dev,bool cleanup)1251 void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup)
1252 {
1253 mutex_lock(&dev->intf_state_mutex);
1254
1255 if (cleanup) {
1256 mlx5_unregister_device(dev);
1257 mlx5_devlink_unregister(priv_to_devlink(dev));
1258 } else {
1259 mlx5_detach_device(dev);
1260 }
1261
1262 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1263 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1264 __func__);
1265 if (cleanup)
1266 mlx5_cleanup_once(dev);
1267 goto out;
1268 }
1269
1270 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1271
1272 mlx5_unload(dev);
1273
1274 if (cleanup)
1275 mlx5_cleanup_once(dev);
1276
1277 mlx5_function_teardown(dev, cleanup);
1278 out:
1279 mutex_unlock(&dev->intf_state_mutex);
1280 }
1281
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1282 static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1283 {
1284 struct mlx5_priv *priv = &dev->priv;
1285 int err;
1286
1287 dev->profile = &profile[profile_idx];
1288
1289 INIT_LIST_HEAD(&priv->ctx_list);
1290 spin_lock_init(&priv->ctx_lock);
1291 mutex_init(&dev->intf_state_mutex);
1292
1293 mutex_init(&priv->bfregs.reg_head.lock);
1294 mutex_init(&priv->bfregs.wc_head.lock);
1295 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1296 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1297
1298 mutex_init(&priv->alloc_mutex);
1299 mutex_init(&priv->pgdir_mutex);
1300 INIT_LIST_HEAD(&priv->pgdir_list);
1301
1302 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1303 mlx5_debugfs_root);
1304 err = mlx5_health_init(dev);
1305 if (err)
1306 goto err_health_init;
1307
1308 err = mlx5_pagealloc_init(dev);
1309 if (err)
1310 goto err_pagealloc_init;
1311
1312 return 0;
1313
1314 err_pagealloc_init:
1315 mlx5_health_cleanup(dev);
1316 err_health_init:
1317 debugfs_remove(dev->priv.dbg_root);
1318 mutex_destroy(&priv->pgdir_mutex);
1319 mutex_destroy(&priv->alloc_mutex);
1320 mutex_destroy(&priv->bfregs.wc_head.lock);
1321 mutex_destroy(&priv->bfregs.reg_head.lock);
1322 mutex_destroy(&dev->intf_state_mutex);
1323 return err;
1324 }
1325
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1326 static void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1327 {
1328 struct mlx5_priv *priv = &dev->priv;
1329
1330 mlx5_pagealloc_cleanup(dev);
1331 mlx5_health_cleanup(dev);
1332 debugfs_remove_recursive(dev->priv.dbg_root);
1333 mutex_destroy(&priv->pgdir_mutex);
1334 mutex_destroy(&priv->alloc_mutex);
1335 mutex_destroy(&priv->bfregs.wc_head.lock);
1336 mutex_destroy(&priv->bfregs.reg_head.lock);
1337 mutex_destroy(&dev->intf_state_mutex);
1338 }
1339
1340 #define MLX5_IB_MOD "mlx5_ib"
init_one(struct pci_dev * pdev,const struct pci_device_id * id)1341 static int init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1342 {
1343 struct mlx5_core_dev *dev;
1344 struct devlink *devlink;
1345 int err;
1346
1347 devlink = mlx5_devlink_alloc();
1348 if (!devlink) {
1349 dev_err(&pdev->dev, "devlink alloc failed\n");
1350 return -ENOMEM;
1351 }
1352
1353 dev = devlink_priv(devlink);
1354 dev->device = &pdev->dev;
1355 dev->pdev = pdev;
1356
1357 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1358 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1359
1360 err = mlx5_mdev_init(dev, prof_sel);
1361 if (err)
1362 goto mdev_init_err;
1363
1364 err = mlx5_pci_init(dev, pdev, id);
1365 if (err) {
1366 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1367 err);
1368 goto pci_init_err;
1369 }
1370
1371 err = mlx5_load_one(dev, true);
1372 if (err) {
1373 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n",
1374 err);
1375 goto err_load_one;
1376 }
1377
1378 request_module_nowait(MLX5_IB_MOD);
1379
1380 err = mlx5_crdump_enable(dev);
1381 if (err)
1382 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1383
1384 pci_save_state(pdev);
1385 if (!mlx5_core_is_mp_slave(dev))
1386 devlink_reload_enable(devlink);
1387 return 0;
1388
1389 err_load_one:
1390 mlx5_pci_close(dev);
1391 pci_init_err:
1392 mlx5_mdev_uninit(dev);
1393 mdev_init_err:
1394 mlx5_devlink_free(devlink);
1395
1396 return err;
1397 }
1398
remove_one(struct pci_dev * pdev)1399 static void remove_one(struct pci_dev *pdev)
1400 {
1401 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1402 struct devlink *devlink = priv_to_devlink(dev);
1403
1404 devlink_reload_disable(devlink);
1405 mlx5_crdump_disable(dev);
1406 mlx5_drain_health_wq(dev);
1407 mlx5_unload_one(dev, true);
1408 mlx5_pci_close(dev);
1409 mlx5_mdev_uninit(dev);
1410 mlx5_devlink_free(devlink);
1411 }
1412
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1413 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1414 pci_channel_state_t state)
1415 {
1416 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1417
1418 mlx5_core_info(dev, "%s was called\n", __func__);
1419
1420 mlx5_enter_error_state(dev, false);
1421 mlx5_error_sw_reset(dev);
1422 mlx5_unload_one(dev, false);
1423 mlx5_drain_health_wq(dev);
1424 mlx5_pci_disable_device(dev);
1425
1426 return state == pci_channel_io_perm_failure ?
1427 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1428 }
1429
1430 /* wait for the device to show vital signs by waiting
1431 * for the health counter to start counting.
1432 */
wait_vital(struct pci_dev * pdev)1433 static int wait_vital(struct pci_dev *pdev)
1434 {
1435 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1436 struct mlx5_core_health *health = &dev->priv.health;
1437 const int niter = 100;
1438 u32 last_count = 0;
1439 u32 count;
1440 int i;
1441
1442 for (i = 0; i < niter; i++) {
1443 count = ioread32be(health->health_counter);
1444 if (count && count != 0xffffffff) {
1445 if (last_count && last_count != count) {
1446 mlx5_core_info(dev,
1447 "wait vital counter value 0x%x after %d iterations\n",
1448 count, i);
1449 return 0;
1450 }
1451 last_count = count;
1452 }
1453 msleep(50);
1454 }
1455
1456 return -ETIMEDOUT;
1457 }
1458
mlx5_pci_slot_reset(struct pci_dev * pdev)1459 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1460 {
1461 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1462 int err;
1463
1464 mlx5_core_info(dev, "%s was called\n", __func__);
1465
1466 err = mlx5_pci_enable_device(dev);
1467 if (err) {
1468 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1469 __func__, err);
1470 return PCI_ERS_RESULT_DISCONNECT;
1471 }
1472
1473 pci_set_master(pdev);
1474 pci_restore_state(pdev);
1475 pci_save_state(pdev);
1476
1477 if (wait_vital(pdev)) {
1478 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1479 return PCI_ERS_RESULT_DISCONNECT;
1480 }
1481
1482 return PCI_ERS_RESULT_RECOVERED;
1483 }
1484
mlx5_pci_resume(struct pci_dev * pdev)1485 static void mlx5_pci_resume(struct pci_dev *pdev)
1486 {
1487 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1488 int err;
1489
1490 mlx5_core_info(dev, "%s was called\n", __func__);
1491
1492 err = mlx5_load_one(dev, false);
1493 if (err)
1494 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1495 __func__, err);
1496 else
1497 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1498 }
1499
1500 static const struct pci_error_handlers mlx5_err_handler = {
1501 .error_detected = mlx5_pci_err_detected,
1502 .slot_reset = mlx5_pci_slot_reset,
1503 .resume = mlx5_pci_resume
1504 };
1505
mlx5_try_fast_unload(struct mlx5_core_dev * dev)1506 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1507 {
1508 bool fast_teardown = false, force_teardown = false;
1509 int ret = 1;
1510
1511 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1512 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1513
1514 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1515 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1516
1517 if (!fast_teardown && !force_teardown)
1518 return -EOPNOTSUPP;
1519
1520 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1521 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1522 return -EAGAIN;
1523 }
1524
1525 /* Panic tear down fw command will stop the PCI bus communication
1526 * with the HCA, so the health polll is no longer needed.
1527 */
1528 mlx5_drain_health_wq(dev);
1529 mlx5_stop_health_poll(dev, false);
1530
1531 ret = mlx5_cmd_fast_teardown_hca(dev);
1532 if (!ret)
1533 goto succeed;
1534
1535 ret = mlx5_cmd_force_teardown_hca(dev);
1536 if (!ret)
1537 goto succeed;
1538
1539 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1540 mlx5_start_health_poll(dev);
1541 return ret;
1542
1543 succeed:
1544 mlx5_enter_error_state(dev, true);
1545
1546 /* Some platforms requiring freeing the IRQ's in the shutdown
1547 * flow. If they aren't freed they can't be allocated after
1548 * kexec. There is no need to cleanup the mlx5_core software
1549 * contexts.
1550 */
1551 mlx5_core_eq_free_irqs(dev);
1552
1553 return 0;
1554 }
1555
shutdown(struct pci_dev * pdev)1556 static void shutdown(struct pci_dev *pdev)
1557 {
1558 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1559 int err;
1560
1561 mlx5_core_info(dev, "Shutdown was called\n");
1562 err = mlx5_try_fast_unload(dev);
1563 if (err)
1564 mlx5_unload_one(dev, false);
1565 mlx5_pci_disable_device(dev);
1566 }
1567
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)1568 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1569 {
1570 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1571
1572 mlx5_unload_one(dev, false);
1573
1574 return 0;
1575 }
1576
mlx5_resume(struct pci_dev * pdev)1577 static int mlx5_resume(struct pci_dev *pdev)
1578 {
1579 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1580
1581 return mlx5_load_one(dev, false);
1582 }
1583
1584 static const struct pci_device_id mlx5_core_pci_table[] = {
1585 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1586 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1587 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1588 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1589 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1590 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1591 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1592 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1593 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1594 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1595 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1596 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1597 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1598 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1599 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1600 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1601 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1602 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1603 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1604 { 0, }
1605 };
1606
1607 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1608
mlx5_disable_device(struct mlx5_core_dev * dev)1609 void mlx5_disable_device(struct mlx5_core_dev *dev)
1610 {
1611 mlx5_error_sw_reset(dev);
1612 mlx5_unload_one(dev, false);
1613 }
1614
mlx5_recover_device(struct mlx5_core_dev * dev)1615 void mlx5_recover_device(struct mlx5_core_dev *dev)
1616 {
1617 mlx5_pci_disable_device(dev);
1618 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1619 mlx5_pci_resume(dev->pdev);
1620 }
1621
1622 static struct pci_driver mlx5_core_driver = {
1623 .name = DRIVER_NAME,
1624 .id_table = mlx5_core_pci_table,
1625 .probe = init_one,
1626 .remove = remove_one,
1627 .suspend = mlx5_suspend,
1628 .resume = mlx5_resume,
1629 .shutdown = shutdown,
1630 .err_handler = &mlx5_err_handler,
1631 .sriov_configure = mlx5_core_sriov_configure,
1632 };
1633
mlx5_core_verify_params(void)1634 static void mlx5_core_verify_params(void)
1635 {
1636 if (prof_sel >= ARRAY_SIZE(profile)) {
1637 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1638 prof_sel,
1639 ARRAY_SIZE(profile) - 1,
1640 MLX5_DEFAULT_PROF);
1641 prof_sel = MLX5_DEFAULT_PROF;
1642 }
1643 }
1644
mlx5_init(void)1645 static int __init mlx5_init(void)
1646 {
1647 int err;
1648
1649 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1650
1651 mlx5_core_verify_params();
1652 mlx5_fpga_ipsec_build_fs_cmds();
1653 mlx5_register_debugfs();
1654
1655 err = pci_register_driver(&mlx5_core_driver);
1656 if (err)
1657 goto err_debug;
1658
1659 #ifdef CONFIG_MLX5_CORE_EN
1660 mlx5e_init();
1661 #endif
1662
1663 return 0;
1664
1665 err_debug:
1666 mlx5_unregister_debugfs();
1667 return err;
1668 }
1669
mlx5_cleanup(void)1670 static void __exit mlx5_cleanup(void)
1671 {
1672 #ifdef CONFIG_MLX5_CORE_EN
1673 mlx5e_cleanup();
1674 #endif
1675 pci_unregister_driver(&mlx5_core_driver);
1676 mlx5_unregister_debugfs();
1677 }
1678
1679 module_init(mlx5_init);
1680 module_exit(mlx5_cleanup);
1681