1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #ifndef _LINUX_NVME_H
8 #define _LINUX_NVME_H
9
10 #include <linux/bits.h>
11 #include <linux/types.h>
12 #include <linux/uuid.h>
13
14 /* NQN names in commands fields specified one size */
15 #define NVMF_NQN_FIELD_LEN 256
16
17 /* However the max length of a qualified name is another size */
18 #define NVMF_NQN_SIZE 223
19
20 #define NVMF_TRSVCID_SIZE 32
21 #define NVMF_TRADDR_SIZE 256
22 #define NVMF_TSAS_SIZE 256
23
24 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25
26 #define NVME_RDMA_IP_PORT 4420
27
28 #define NVME_NSID_ALL 0xffffffff
29
30 enum nvme_subsys_type {
31 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
32 NVME_NQN_NVME = 2, /* NVME type target subsystem */
33 };
34
35 /* Address Family codes for Discovery Log Page entry ADRFAM field */
36 enum {
37 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
38 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
39 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
40 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
41 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
42 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
43 NVMF_ADDR_FAMILY_MAX,
44 };
45
46 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
47 enum {
48 NVMF_TRTYPE_RDMA = 1, /* RDMA */
49 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
50 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
51 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
52 NVMF_TRTYPE_MAX,
53 };
54
55 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
56 enum {
57 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
58 NVMF_TREQ_REQUIRED = 1, /* Required */
59 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
60 #define NVME_TREQ_SECURE_CHANNEL_MASK \
61 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
62
63 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
64 };
65
66 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
67 * RDMA_QPTYPE field
68 */
69 enum {
70 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
71 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
72 };
73
74 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
75 * RDMA_QPTYPE field
76 */
77 enum {
78 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
79 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
80 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
81 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
82 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
83 };
84
85 /* RDMA Connection Management Service Type codes for Discovery Log Page
86 * entry TSAS RDMA_CMS field
87 */
88 enum {
89 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
90 };
91
92 #define NVME_AQ_DEPTH 32
93 #define NVME_NR_AEN_COMMANDS 1
94 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
95
96 /*
97 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
98 * NVM-Express 1.2 specification, section 4.1.2.
99 */
100 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
101
102 enum {
103 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
104 NVME_REG_VS = 0x0008, /* Version */
105 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
106 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
107 NVME_REG_CC = 0x0014, /* Controller Configuration */
108 NVME_REG_CSTS = 0x001c, /* Controller Status */
109 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
110 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
111 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
112 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
113 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
114 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
115 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
116 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
117 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
118 * Location
119 */
120 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
121 * Space Control
122 */
123 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
124 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
125 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
126 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
127 * Buffer Size
128 */
129 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
130 * Write Throughput
131 */
132 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
133 };
134
135 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
136 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
137 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
138 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
139 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
140 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
141 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
142 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
143
144 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
145 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
146
147 enum {
148 NVME_CMBSZ_SQS = 1 << 0,
149 NVME_CMBSZ_CQS = 1 << 1,
150 NVME_CMBSZ_LISTS = 1 << 2,
151 NVME_CMBSZ_RDS = 1 << 3,
152 NVME_CMBSZ_WDS = 1 << 4,
153
154 NVME_CMBSZ_SZ_SHIFT = 12,
155 NVME_CMBSZ_SZ_MASK = 0xfffff,
156
157 NVME_CMBSZ_SZU_SHIFT = 8,
158 NVME_CMBSZ_SZU_MASK = 0xf,
159 };
160
161 /*
162 * Submission and Completion Queue Entry Sizes for the NVM command set.
163 * (In bytes and specified as a power of two (2^n)).
164 */
165 #define NVME_ADM_SQES 6
166 #define NVME_NVM_IOSQES 6
167 #define NVME_NVM_IOCQES 4
168
169 enum {
170 NVME_CC_ENABLE = 1 << 0,
171 NVME_CC_EN_SHIFT = 0,
172 NVME_CC_CSS_SHIFT = 4,
173 NVME_CC_MPS_SHIFT = 7,
174 NVME_CC_AMS_SHIFT = 11,
175 NVME_CC_SHN_SHIFT = 14,
176 NVME_CC_IOSQES_SHIFT = 16,
177 NVME_CC_IOCQES_SHIFT = 20,
178 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
179 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
180 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
181 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
182 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
183 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
184 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
185 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
186 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
187 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
188 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
189 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
190 NVME_CAP_CSS_NVM = 1 << 0,
191 NVME_CAP_CSS_CSI = 1 << 6,
192 NVME_CSTS_RDY = 1 << 0,
193 NVME_CSTS_CFS = 1 << 1,
194 NVME_CSTS_NSSRO = 1 << 4,
195 NVME_CSTS_PP = 1 << 5,
196 NVME_CSTS_SHST_NORMAL = 0 << 2,
197 NVME_CSTS_SHST_OCCUR = 1 << 2,
198 NVME_CSTS_SHST_CMPLT = 2 << 2,
199 NVME_CSTS_SHST_MASK = 3 << 2,
200 NVME_CMBMSC_CRE = 1 << 0,
201 NVME_CMBMSC_CMSE = 1 << 1,
202 };
203
204 struct nvme_id_power_state {
205 __le16 max_power; /* centiwatts */
206 __u8 rsvd2;
207 __u8 flags;
208 __le32 entry_lat; /* microseconds */
209 __le32 exit_lat; /* microseconds */
210 __u8 read_tput;
211 __u8 read_lat;
212 __u8 write_tput;
213 __u8 write_lat;
214 __le16 idle_power;
215 __u8 idle_scale;
216 __u8 rsvd19;
217 __le16 active_power;
218 __u8 active_work_scale;
219 __u8 rsvd23[9];
220 };
221
222 enum {
223 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
224 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
225 };
226
227 enum nvme_ctrl_attr {
228 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
229 NVME_CTRL_ATTR_TBKAS = (1 << 6),
230 };
231
232 struct nvme_id_ctrl {
233 __le16 vid;
234 __le16 ssvid;
235 char sn[20];
236 char mn[40];
237 char fr[8];
238 __u8 rab;
239 __u8 ieee[3];
240 __u8 cmic;
241 __u8 mdts;
242 __le16 cntlid;
243 __le32 ver;
244 __le32 rtd3r;
245 __le32 rtd3e;
246 __le32 oaes;
247 __le32 ctratt;
248 __u8 rsvd100[28];
249 __le16 crdt1;
250 __le16 crdt2;
251 __le16 crdt3;
252 __u8 rsvd134[122];
253 __le16 oacs;
254 __u8 acl;
255 __u8 aerl;
256 __u8 frmw;
257 __u8 lpa;
258 __u8 elpe;
259 __u8 npss;
260 __u8 avscc;
261 __u8 apsta;
262 __le16 wctemp;
263 __le16 cctemp;
264 __le16 mtfa;
265 __le32 hmpre;
266 __le32 hmmin;
267 __u8 tnvmcap[16];
268 __u8 unvmcap[16];
269 __le32 rpmbs;
270 __le16 edstt;
271 __u8 dsto;
272 __u8 fwug;
273 __le16 kas;
274 __le16 hctma;
275 __le16 mntmt;
276 __le16 mxtmt;
277 __le32 sanicap;
278 __le32 hmminds;
279 __le16 hmmaxd;
280 __u8 rsvd338[4];
281 __u8 anatt;
282 __u8 anacap;
283 __le32 anagrpmax;
284 __le32 nanagrpid;
285 __u8 rsvd352[160];
286 __u8 sqes;
287 __u8 cqes;
288 __le16 maxcmd;
289 __le32 nn;
290 __le16 oncs;
291 __le16 fuses;
292 __u8 fna;
293 __u8 vwc;
294 __le16 awun;
295 __le16 awupf;
296 __u8 nvscc;
297 __u8 nwpc;
298 __le16 acwu;
299 __u8 rsvd534[2];
300 __le32 sgls;
301 __le32 mnan;
302 __u8 rsvd544[224];
303 char subnqn[256];
304 __u8 rsvd1024[768];
305 __le32 ioccsz;
306 __le32 iorcsz;
307 __le16 icdoff;
308 __u8 ctrattr;
309 __u8 msdbd;
310 __u8 rsvd1804[244];
311 struct nvme_id_power_state psd[32];
312 __u8 vs[1024];
313 };
314
315 enum {
316 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
317 NVME_CTRL_CMIC_ANA = 1 << 3,
318 NVME_CTRL_ONCS_COMPARE = 1 << 0,
319 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
320 NVME_CTRL_ONCS_DSM = 1 << 2,
321 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
322 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
323 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
324 NVME_CTRL_VWC_PRESENT = 1 << 0,
325 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
326 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
327 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
328 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
329 NVME_CTRL_CTRATT_128_ID = 1 << 0,
330 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
331 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
332 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
333 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
334 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
335 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
336 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
337 };
338
339 struct nvme_lbaf {
340 __le16 ms;
341 __u8 ds;
342 __u8 rp;
343 };
344
345 struct nvme_id_ns {
346 __le64 nsze;
347 __le64 ncap;
348 __le64 nuse;
349 __u8 nsfeat;
350 __u8 nlbaf;
351 __u8 flbas;
352 __u8 mc;
353 __u8 dpc;
354 __u8 dps;
355 __u8 nmic;
356 __u8 rescap;
357 __u8 fpi;
358 __u8 dlfeat;
359 __le16 nawun;
360 __le16 nawupf;
361 __le16 nacwu;
362 __le16 nabsn;
363 __le16 nabo;
364 __le16 nabspf;
365 __le16 noiob;
366 __u8 nvmcap[16];
367 __le16 npwg;
368 __le16 npwa;
369 __le16 npdg;
370 __le16 npda;
371 __le16 nows;
372 __u8 rsvd74[18];
373 __le32 anagrpid;
374 __u8 rsvd96[3];
375 __u8 nsattr;
376 __le16 nvmsetid;
377 __le16 endgid;
378 __u8 nguid[16];
379 __u8 eui64[8];
380 struct nvme_lbaf lbaf[16];
381 __u8 rsvd192[192];
382 __u8 vs[3712];
383 };
384
385 struct nvme_zns_lbafe {
386 __le64 zsze;
387 __u8 zdes;
388 __u8 rsvd9[7];
389 };
390
391 struct nvme_id_ns_zns {
392 __le16 zoc;
393 __le16 ozcs;
394 __le32 mar;
395 __le32 mor;
396 __le32 rrl;
397 __le32 frl;
398 __u8 rsvd20[2796];
399 struct nvme_zns_lbafe lbafe[16];
400 __u8 rsvd3072[768];
401 __u8 vs[256];
402 };
403
404 struct nvme_id_ctrl_zns {
405 __u8 zasl;
406 __u8 rsvd1[4095];
407 };
408
409 enum {
410 NVME_ID_CNS_NS = 0x00,
411 NVME_ID_CNS_CTRL = 0x01,
412 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
413 NVME_ID_CNS_NS_DESC_LIST = 0x03,
414 NVME_ID_CNS_CS_NS = 0x05,
415 NVME_ID_CNS_CS_CTRL = 0x06,
416 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
417 NVME_ID_CNS_NS_PRESENT = 0x11,
418 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
419 NVME_ID_CNS_CTRL_LIST = 0x13,
420 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
421 NVME_ID_CNS_NS_GRANULARITY = 0x16,
422 NVME_ID_CNS_UUID_LIST = 0x17,
423 };
424
425 enum {
426 NVME_CSI_NVM = 0,
427 NVME_CSI_ZNS = 2,
428 };
429
430 enum {
431 NVME_DIR_IDENTIFY = 0x00,
432 NVME_DIR_STREAMS = 0x01,
433 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
434 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
435 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
436 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
437 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
438 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
439 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
440 NVME_DIR_ENDIR = 0x01,
441 };
442
443 enum {
444 NVME_NS_FEAT_THIN = 1 << 0,
445 NVME_NS_FEAT_ATOMICS = 1 << 1,
446 NVME_NS_FEAT_IO_OPT = 1 << 4,
447 NVME_NS_ATTR_RO = 1 << 0,
448 NVME_NS_FLBAS_LBA_MASK = 0xf,
449 NVME_NS_FLBAS_META_EXT = 0x10,
450 NVME_NS_NMIC_SHARED = 1 << 0,
451 NVME_LBAF_RP_BEST = 0,
452 NVME_LBAF_RP_BETTER = 1,
453 NVME_LBAF_RP_GOOD = 2,
454 NVME_LBAF_RP_DEGRADED = 3,
455 NVME_NS_DPC_PI_LAST = 1 << 4,
456 NVME_NS_DPC_PI_FIRST = 1 << 3,
457 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
458 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
459 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
460 NVME_NS_DPS_PI_FIRST = 1 << 3,
461 NVME_NS_DPS_PI_MASK = 0x7,
462 NVME_NS_DPS_PI_TYPE1 = 1,
463 NVME_NS_DPS_PI_TYPE2 = 2,
464 NVME_NS_DPS_PI_TYPE3 = 3,
465 };
466
467 /* Identify Namespace Metadata Capabilities (MC): */
468 enum {
469 NVME_MC_EXTENDED_LBA = (1 << 0),
470 NVME_MC_METADATA_PTR = (1 << 1),
471 };
472
473 struct nvme_ns_id_desc {
474 __u8 nidt;
475 __u8 nidl;
476 __le16 reserved;
477 };
478
479 #define NVME_NIDT_EUI64_LEN 8
480 #define NVME_NIDT_NGUID_LEN 16
481 #define NVME_NIDT_UUID_LEN 16
482 #define NVME_NIDT_CSI_LEN 1
483
484 enum {
485 NVME_NIDT_EUI64 = 0x01,
486 NVME_NIDT_NGUID = 0x02,
487 NVME_NIDT_UUID = 0x03,
488 NVME_NIDT_CSI = 0x04,
489 };
490
491 struct nvme_smart_log {
492 __u8 critical_warning;
493 __u8 temperature[2];
494 __u8 avail_spare;
495 __u8 spare_thresh;
496 __u8 percent_used;
497 __u8 endu_grp_crit_warn_sumry;
498 __u8 rsvd7[25];
499 __u8 data_units_read[16];
500 __u8 data_units_written[16];
501 __u8 host_reads[16];
502 __u8 host_writes[16];
503 __u8 ctrl_busy_time[16];
504 __u8 power_cycles[16];
505 __u8 power_on_hours[16];
506 __u8 unsafe_shutdowns[16];
507 __u8 media_errors[16];
508 __u8 num_err_log_entries[16];
509 __le32 warning_temp_time;
510 __le32 critical_comp_time;
511 __le16 temp_sensor[8];
512 __le32 thm_temp1_trans_count;
513 __le32 thm_temp2_trans_count;
514 __le32 thm_temp1_total_time;
515 __le32 thm_temp2_total_time;
516 __u8 rsvd232[280];
517 };
518
519 struct nvme_fw_slot_info_log {
520 __u8 afi;
521 __u8 rsvd1[7];
522 __le64 frs[7];
523 __u8 rsvd64[448];
524 };
525
526 enum {
527 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
528 NVME_CMD_EFFECTS_LBCC = 1 << 1,
529 NVME_CMD_EFFECTS_NCC = 1 << 2,
530 NVME_CMD_EFFECTS_NIC = 1 << 3,
531 NVME_CMD_EFFECTS_CCC = 1 << 4,
532 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
533 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
534 };
535
536 struct nvme_effects_log {
537 __le32 acs[256];
538 __le32 iocs[256];
539 __u8 resv[2048];
540 };
541
542 enum nvme_ana_state {
543 NVME_ANA_OPTIMIZED = 0x01,
544 NVME_ANA_NONOPTIMIZED = 0x02,
545 NVME_ANA_INACCESSIBLE = 0x03,
546 NVME_ANA_PERSISTENT_LOSS = 0x04,
547 NVME_ANA_CHANGE = 0x0f,
548 };
549
550 struct nvme_ana_group_desc {
551 __le32 grpid;
552 __le32 nnsids;
553 __le64 chgcnt;
554 __u8 state;
555 __u8 rsvd17[15];
556 __le32 nsids[];
557 };
558
559 /* flag for the log specific field of the ANA log */
560 #define NVME_ANA_LOG_RGO (1 << 0)
561
562 struct nvme_ana_rsp_hdr {
563 __le64 chgcnt;
564 __le16 ngrps;
565 __le16 rsvd10[3];
566 };
567
568 struct nvme_zone_descriptor {
569 __u8 zt;
570 __u8 zs;
571 __u8 za;
572 __u8 rsvd3[5];
573 __le64 zcap;
574 __le64 zslba;
575 __le64 wp;
576 __u8 rsvd32[32];
577 };
578
579 enum {
580 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
581 };
582
583 struct nvme_zone_report {
584 __le64 nr_zones;
585 __u8 resv8[56];
586 struct nvme_zone_descriptor entries[];
587 };
588
589 enum {
590 NVME_SMART_CRIT_SPARE = 1 << 0,
591 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
592 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
593 NVME_SMART_CRIT_MEDIA = 1 << 3,
594 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
595 };
596
597 enum {
598 NVME_AER_ERROR = 0,
599 NVME_AER_SMART = 1,
600 NVME_AER_NOTICE = 2,
601 NVME_AER_CSS = 6,
602 NVME_AER_VS = 7,
603 };
604
605 enum {
606 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
607 };
608
609 enum {
610 NVME_AER_NOTICE_NS_CHANGED = 0x00,
611 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
612 NVME_AER_NOTICE_ANA = 0x03,
613 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
614 };
615
616 enum {
617 NVME_AEN_BIT_NS_ATTR = 8,
618 NVME_AEN_BIT_FW_ACT = 9,
619 NVME_AEN_BIT_ANA_CHANGE = 11,
620 NVME_AEN_BIT_DISC_CHANGE = 31,
621 };
622
623 enum {
624 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
625 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
626 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
627 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
628 };
629
630 struct nvme_lba_range_type {
631 __u8 type;
632 __u8 attributes;
633 __u8 rsvd2[14];
634 __u64 slba;
635 __u64 nlb;
636 __u8 guid[16];
637 __u8 rsvd48[16];
638 };
639
640 enum {
641 NVME_LBART_TYPE_FS = 0x01,
642 NVME_LBART_TYPE_RAID = 0x02,
643 NVME_LBART_TYPE_CACHE = 0x03,
644 NVME_LBART_TYPE_SWAP = 0x04,
645
646 NVME_LBART_ATTRIB_TEMP = 1 << 0,
647 NVME_LBART_ATTRIB_HIDE = 1 << 1,
648 };
649
650 struct nvme_reservation_status {
651 __le32 gen;
652 __u8 rtype;
653 __u8 regctl[2];
654 __u8 resv5[2];
655 __u8 ptpls;
656 __u8 resv10[13];
657 struct {
658 __le16 cntlid;
659 __u8 rcsts;
660 __u8 resv3[5];
661 __le64 hostid;
662 __le64 rkey;
663 } regctl_ds[];
664 };
665
666 enum nvme_async_event_type {
667 NVME_AER_TYPE_ERROR = 0,
668 NVME_AER_TYPE_SMART = 1,
669 NVME_AER_TYPE_NOTICE = 2,
670 };
671
672 /* I/O commands */
673
674 enum nvme_opcode {
675 nvme_cmd_flush = 0x00,
676 nvme_cmd_write = 0x01,
677 nvme_cmd_read = 0x02,
678 nvme_cmd_write_uncor = 0x04,
679 nvme_cmd_compare = 0x05,
680 nvme_cmd_write_zeroes = 0x08,
681 nvme_cmd_dsm = 0x09,
682 nvme_cmd_verify = 0x0c,
683 nvme_cmd_resv_register = 0x0d,
684 nvme_cmd_resv_report = 0x0e,
685 nvme_cmd_resv_acquire = 0x11,
686 nvme_cmd_resv_release = 0x15,
687 nvme_cmd_zone_mgmt_send = 0x79,
688 nvme_cmd_zone_mgmt_recv = 0x7a,
689 nvme_cmd_zone_append = 0x7d,
690 };
691
692 #define nvme_opcode_name(opcode) { opcode, #opcode }
693 #define show_nvm_opcode_name(val) \
694 __print_symbolic(val, \
695 nvme_opcode_name(nvme_cmd_flush), \
696 nvme_opcode_name(nvme_cmd_write), \
697 nvme_opcode_name(nvme_cmd_read), \
698 nvme_opcode_name(nvme_cmd_write_uncor), \
699 nvme_opcode_name(nvme_cmd_compare), \
700 nvme_opcode_name(nvme_cmd_write_zeroes), \
701 nvme_opcode_name(nvme_cmd_dsm), \
702 nvme_opcode_name(nvme_cmd_resv_register), \
703 nvme_opcode_name(nvme_cmd_resv_report), \
704 nvme_opcode_name(nvme_cmd_resv_acquire), \
705 nvme_opcode_name(nvme_cmd_resv_release))
706
707
708 /*
709 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
710 *
711 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
712 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
713 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
714 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
715 * request subtype
716 */
717 enum {
718 NVME_SGL_FMT_ADDRESS = 0x00,
719 NVME_SGL_FMT_OFFSET = 0x01,
720 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
721 NVME_SGL_FMT_INVALIDATE = 0x0f,
722 };
723
724 /*
725 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
726 *
727 * For struct nvme_sgl_desc:
728 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
729 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
730 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
731 *
732 * For struct nvme_keyed_sgl_desc:
733 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
734 *
735 * Transport-specific SGL types:
736 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
737 */
738 enum {
739 NVME_SGL_FMT_DATA_DESC = 0x00,
740 NVME_SGL_FMT_SEG_DESC = 0x02,
741 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
742 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
743 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
744 };
745
746 struct nvme_sgl_desc {
747 __le64 addr;
748 __le32 length;
749 __u8 rsvd[3];
750 __u8 type;
751 };
752
753 struct nvme_keyed_sgl_desc {
754 __le64 addr;
755 __u8 length[3];
756 __u8 key[4];
757 __u8 type;
758 };
759
760 union nvme_data_ptr {
761 struct {
762 __le64 prp1;
763 __le64 prp2;
764 };
765 struct nvme_sgl_desc sgl;
766 struct nvme_keyed_sgl_desc ksgl;
767 };
768
769 /*
770 * Lowest two bits of our flags field (FUSE field in the spec):
771 *
772 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
773 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
774 *
775 * Highest two bits in our flags field (PSDT field in the spec):
776 *
777 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
778 * If used, MPTR contains addr of single physical buffer (byte aligned).
779 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
780 * If used, MPTR contains an address of an SGL segment containing
781 * exactly 1 SGL descriptor (qword aligned).
782 */
783 enum {
784 NVME_CMD_FUSE_FIRST = (1 << 0),
785 NVME_CMD_FUSE_SECOND = (1 << 1),
786
787 NVME_CMD_SGL_METABUF = (1 << 6),
788 NVME_CMD_SGL_METASEG = (1 << 7),
789 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
790 };
791
792 struct nvme_common_command {
793 __u8 opcode;
794 __u8 flags;
795 __u16 command_id;
796 __le32 nsid;
797 __le32 cdw2[2];
798 __le64 metadata;
799 union nvme_data_ptr dptr;
800 __le32 cdw10;
801 __le32 cdw11;
802 __le32 cdw12;
803 __le32 cdw13;
804 __le32 cdw14;
805 __le32 cdw15;
806 };
807
808 struct nvme_rw_command {
809 __u8 opcode;
810 __u8 flags;
811 __u16 command_id;
812 __le32 nsid;
813 __u64 rsvd2;
814 __le64 metadata;
815 union nvme_data_ptr dptr;
816 __le64 slba;
817 __le16 length;
818 __le16 control;
819 __le32 dsmgmt;
820 __le32 reftag;
821 __le16 apptag;
822 __le16 appmask;
823 };
824
825 enum {
826 NVME_RW_LR = 1 << 15,
827 NVME_RW_FUA = 1 << 14,
828 NVME_RW_APPEND_PIREMAP = 1 << 9,
829 NVME_RW_DSM_FREQ_UNSPEC = 0,
830 NVME_RW_DSM_FREQ_TYPICAL = 1,
831 NVME_RW_DSM_FREQ_RARE = 2,
832 NVME_RW_DSM_FREQ_READS = 3,
833 NVME_RW_DSM_FREQ_WRITES = 4,
834 NVME_RW_DSM_FREQ_RW = 5,
835 NVME_RW_DSM_FREQ_ONCE = 6,
836 NVME_RW_DSM_FREQ_PREFETCH = 7,
837 NVME_RW_DSM_FREQ_TEMP = 8,
838 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
839 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
840 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
841 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
842 NVME_RW_DSM_SEQ_REQ = 1 << 6,
843 NVME_RW_DSM_COMPRESSED = 1 << 7,
844 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
845 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
846 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
847 NVME_RW_PRINFO_PRACT = 1 << 13,
848 NVME_RW_DTYPE_STREAMS = 1 << 4,
849 };
850
851 struct nvme_dsm_cmd {
852 __u8 opcode;
853 __u8 flags;
854 __u16 command_id;
855 __le32 nsid;
856 __u64 rsvd2[2];
857 union nvme_data_ptr dptr;
858 __le32 nr;
859 __le32 attributes;
860 __u32 rsvd12[4];
861 };
862
863 enum {
864 NVME_DSMGMT_IDR = 1 << 0,
865 NVME_DSMGMT_IDW = 1 << 1,
866 NVME_DSMGMT_AD = 1 << 2,
867 };
868
869 #define NVME_DSM_MAX_RANGES 256
870
871 struct nvme_dsm_range {
872 __le32 cattr;
873 __le32 nlb;
874 __le64 slba;
875 };
876
877 struct nvme_write_zeroes_cmd {
878 __u8 opcode;
879 __u8 flags;
880 __u16 command_id;
881 __le32 nsid;
882 __u64 rsvd2;
883 __le64 metadata;
884 union nvme_data_ptr dptr;
885 __le64 slba;
886 __le16 length;
887 __le16 control;
888 __le32 dsmgmt;
889 __le32 reftag;
890 __le16 apptag;
891 __le16 appmask;
892 };
893
894 enum nvme_zone_mgmt_action {
895 NVME_ZONE_CLOSE = 0x1,
896 NVME_ZONE_FINISH = 0x2,
897 NVME_ZONE_OPEN = 0x3,
898 NVME_ZONE_RESET = 0x4,
899 NVME_ZONE_OFFLINE = 0x5,
900 NVME_ZONE_SET_DESC_EXT = 0x10,
901 };
902
903 struct nvme_zone_mgmt_send_cmd {
904 __u8 opcode;
905 __u8 flags;
906 __u16 command_id;
907 __le32 nsid;
908 __le32 cdw2[2];
909 __le64 metadata;
910 union nvme_data_ptr dptr;
911 __le64 slba;
912 __le32 cdw12;
913 __u8 zsa;
914 __u8 select_all;
915 __u8 rsvd13[2];
916 __le32 cdw14[2];
917 };
918
919 struct nvme_zone_mgmt_recv_cmd {
920 __u8 opcode;
921 __u8 flags;
922 __u16 command_id;
923 __le32 nsid;
924 __le64 rsvd2[2];
925 union nvme_data_ptr dptr;
926 __le64 slba;
927 __le32 numd;
928 __u8 zra;
929 __u8 zrasf;
930 __u8 pr;
931 __u8 rsvd13;
932 __le32 cdw14[2];
933 };
934
935 enum {
936 NVME_ZRA_ZONE_REPORT = 0,
937 NVME_ZRASF_ZONE_REPORT_ALL = 0,
938 NVME_REPORT_ZONE_PARTIAL = 1,
939 };
940
941 /* Features */
942
943 enum {
944 NVME_TEMP_THRESH_MASK = 0xffff,
945 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
946 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
947 };
948
949 struct nvme_feat_auto_pst {
950 __le64 entries[32];
951 };
952
953 enum {
954 NVME_HOST_MEM_ENABLE = (1 << 0),
955 NVME_HOST_MEM_RETURN = (1 << 1),
956 };
957
958 struct nvme_feat_host_behavior {
959 __u8 acre;
960 __u8 resv1[511];
961 };
962
963 enum {
964 NVME_ENABLE_ACRE = 1,
965 };
966
967 /* Admin commands */
968
969 enum nvme_admin_opcode {
970 nvme_admin_delete_sq = 0x00,
971 nvme_admin_create_sq = 0x01,
972 nvme_admin_get_log_page = 0x02,
973 nvme_admin_delete_cq = 0x04,
974 nvme_admin_create_cq = 0x05,
975 nvme_admin_identify = 0x06,
976 nvme_admin_abort_cmd = 0x08,
977 nvme_admin_set_features = 0x09,
978 nvme_admin_get_features = 0x0a,
979 nvme_admin_async_event = 0x0c,
980 nvme_admin_ns_mgmt = 0x0d,
981 nvme_admin_activate_fw = 0x10,
982 nvme_admin_download_fw = 0x11,
983 nvme_admin_dev_self_test = 0x14,
984 nvme_admin_ns_attach = 0x15,
985 nvme_admin_keep_alive = 0x18,
986 nvme_admin_directive_send = 0x19,
987 nvme_admin_directive_recv = 0x1a,
988 nvme_admin_virtual_mgmt = 0x1c,
989 nvme_admin_nvme_mi_send = 0x1d,
990 nvme_admin_nvme_mi_recv = 0x1e,
991 nvme_admin_dbbuf = 0x7C,
992 nvme_admin_format_nvm = 0x80,
993 nvme_admin_security_send = 0x81,
994 nvme_admin_security_recv = 0x82,
995 nvme_admin_sanitize_nvm = 0x84,
996 nvme_admin_get_lba_status = 0x86,
997 nvme_admin_vendor_start = 0xC0,
998 };
999
1000 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1001 #define show_admin_opcode_name(val) \
1002 __print_symbolic(val, \
1003 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1004 nvme_admin_opcode_name(nvme_admin_create_sq), \
1005 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1006 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1007 nvme_admin_opcode_name(nvme_admin_create_cq), \
1008 nvme_admin_opcode_name(nvme_admin_identify), \
1009 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1010 nvme_admin_opcode_name(nvme_admin_set_features), \
1011 nvme_admin_opcode_name(nvme_admin_get_features), \
1012 nvme_admin_opcode_name(nvme_admin_async_event), \
1013 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1014 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1015 nvme_admin_opcode_name(nvme_admin_download_fw), \
1016 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1017 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1018 nvme_admin_opcode_name(nvme_admin_directive_send), \
1019 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1020 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1021 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1022 nvme_admin_opcode_name(nvme_admin_security_send), \
1023 nvme_admin_opcode_name(nvme_admin_security_recv), \
1024 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1025 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1026
1027 enum {
1028 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1029 NVME_CQ_IRQ_ENABLED = (1 << 1),
1030 NVME_SQ_PRIO_URGENT = (0 << 1),
1031 NVME_SQ_PRIO_HIGH = (1 << 1),
1032 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1033 NVME_SQ_PRIO_LOW = (3 << 1),
1034 NVME_FEAT_ARBITRATION = 0x01,
1035 NVME_FEAT_POWER_MGMT = 0x02,
1036 NVME_FEAT_LBA_RANGE = 0x03,
1037 NVME_FEAT_TEMP_THRESH = 0x04,
1038 NVME_FEAT_ERR_RECOVERY = 0x05,
1039 NVME_FEAT_VOLATILE_WC = 0x06,
1040 NVME_FEAT_NUM_QUEUES = 0x07,
1041 NVME_FEAT_IRQ_COALESCE = 0x08,
1042 NVME_FEAT_IRQ_CONFIG = 0x09,
1043 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1044 NVME_FEAT_ASYNC_EVENT = 0x0b,
1045 NVME_FEAT_AUTO_PST = 0x0c,
1046 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1047 NVME_FEAT_TIMESTAMP = 0x0e,
1048 NVME_FEAT_KATO = 0x0f,
1049 NVME_FEAT_HCTM = 0x10,
1050 NVME_FEAT_NOPSC = 0x11,
1051 NVME_FEAT_RRL = 0x12,
1052 NVME_FEAT_PLM_CONFIG = 0x13,
1053 NVME_FEAT_PLM_WINDOW = 0x14,
1054 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1055 NVME_FEAT_SANITIZE = 0x17,
1056 NVME_FEAT_SW_PROGRESS = 0x80,
1057 NVME_FEAT_HOST_ID = 0x81,
1058 NVME_FEAT_RESV_MASK = 0x82,
1059 NVME_FEAT_RESV_PERSIST = 0x83,
1060 NVME_FEAT_WRITE_PROTECT = 0x84,
1061 NVME_FEAT_VENDOR_START = 0xC0,
1062 NVME_FEAT_VENDOR_END = 0xFF,
1063 NVME_LOG_ERROR = 0x01,
1064 NVME_LOG_SMART = 0x02,
1065 NVME_LOG_FW_SLOT = 0x03,
1066 NVME_LOG_CHANGED_NS = 0x04,
1067 NVME_LOG_CMD_EFFECTS = 0x05,
1068 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1069 NVME_LOG_TELEMETRY_HOST = 0x07,
1070 NVME_LOG_TELEMETRY_CTRL = 0x08,
1071 NVME_LOG_ENDURANCE_GROUP = 0x09,
1072 NVME_LOG_ANA = 0x0c,
1073 NVME_LOG_DISC = 0x70,
1074 NVME_LOG_RESERVATION = 0x80,
1075 NVME_FWACT_REPL = (0 << 3),
1076 NVME_FWACT_REPL_ACTV = (1 << 3),
1077 NVME_FWACT_ACTV = (2 << 3),
1078 };
1079
1080 /* NVMe Namespace Write Protect State */
1081 enum {
1082 NVME_NS_NO_WRITE_PROTECT = 0,
1083 NVME_NS_WRITE_PROTECT,
1084 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1085 NVME_NS_WRITE_PROTECT_PERMANENT,
1086 };
1087
1088 #define NVME_MAX_CHANGED_NAMESPACES 1024
1089
1090 struct nvme_identify {
1091 __u8 opcode;
1092 __u8 flags;
1093 __u16 command_id;
1094 __le32 nsid;
1095 __u64 rsvd2[2];
1096 union nvme_data_ptr dptr;
1097 __u8 cns;
1098 __u8 rsvd3;
1099 __le16 ctrlid;
1100 __u8 rsvd11[3];
1101 __u8 csi;
1102 __u32 rsvd12[4];
1103 };
1104
1105 #define NVME_IDENTIFY_DATA_SIZE 4096
1106
1107 struct nvme_features {
1108 __u8 opcode;
1109 __u8 flags;
1110 __u16 command_id;
1111 __le32 nsid;
1112 __u64 rsvd2[2];
1113 union nvme_data_ptr dptr;
1114 __le32 fid;
1115 __le32 dword11;
1116 __le32 dword12;
1117 __le32 dword13;
1118 __le32 dword14;
1119 __le32 dword15;
1120 };
1121
1122 struct nvme_host_mem_buf_desc {
1123 __le64 addr;
1124 __le32 size;
1125 __u32 rsvd;
1126 };
1127
1128 struct nvme_create_cq {
1129 __u8 opcode;
1130 __u8 flags;
1131 __u16 command_id;
1132 __u32 rsvd1[5];
1133 __le64 prp1;
1134 __u64 rsvd8;
1135 __le16 cqid;
1136 __le16 qsize;
1137 __le16 cq_flags;
1138 __le16 irq_vector;
1139 __u32 rsvd12[4];
1140 };
1141
1142 struct nvme_create_sq {
1143 __u8 opcode;
1144 __u8 flags;
1145 __u16 command_id;
1146 __u32 rsvd1[5];
1147 __le64 prp1;
1148 __u64 rsvd8;
1149 __le16 sqid;
1150 __le16 qsize;
1151 __le16 sq_flags;
1152 __le16 cqid;
1153 __u32 rsvd12[4];
1154 };
1155
1156 struct nvme_delete_queue {
1157 __u8 opcode;
1158 __u8 flags;
1159 __u16 command_id;
1160 __u32 rsvd1[9];
1161 __le16 qid;
1162 __u16 rsvd10;
1163 __u32 rsvd11[5];
1164 };
1165
1166 struct nvme_abort_cmd {
1167 __u8 opcode;
1168 __u8 flags;
1169 __u16 command_id;
1170 __u32 rsvd1[9];
1171 __le16 sqid;
1172 __u16 cid;
1173 __u32 rsvd11[5];
1174 };
1175
1176 struct nvme_download_firmware {
1177 __u8 opcode;
1178 __u8 flags;
1179 __u16 command_id;
1180 __u32 rsvd1[5];
1181 union nvme_data_ptr dptr;
1182 __le32 numd;
1183 __le32 offset;
1184 __u32 rsvd12[4];
1185 };
1186
1187 struct nvme_format_cmd {
1188 __u8 opcode;
1189 __u8 flags;
1190 __u16 command_id;
1191 __le32 nsid;
1192 __u64 rsvd2[4];
1193 __le32 cdw10;
1194 __u32 rsvd11[5];
1195 };
1196
1197 struct nvme_get_log_page_command {
1198 __u8 opcode;
1199 __u8 flags;
1200 __u16 command_id;
1201 __le32 nsid;
1202 __u64 rsvd2[2];
1203 union nvme_data_ptr dptr;
1204 __u8 lid;
1205 __u8 lsp; /* upper 4 bits reserved */
1206 __le16 numdl;
1207 __le16 numdu;
1208 __u16 rsvd11;
1209 union {
1210 struct {
1211 __le32 lpol;
1212 __le32 lpou;
1213 };
1214 __le64 lpo;
1215 };
1216 __u8 rsvd14[3];
1217 __u8 csi;
1218 __u32 rsvd15;
1219 };
1220
1221 struct nvme_directive_cmd {
1222 __u8 opcode;
1223 __u8 flags;
1224 __u16 command_id;
1225 __le32 nsid;
1226 __u64 rsvd2[2];
1227 union nvme_data_ptr dptr;
1228 __le32 numd;
1229 __u8 doper;
1230 __u8 dtype;
1231 __le16 dspec;
1232 __u8 endir;
1233 __u8 tdtype;
1234 __u16 rsvd15;
1235
1236 __u32 rsvd16[3];
1237 };
1238
1239 /*
1240 * Fabrics subcommands.
1241 */
1242 enum nvmf_fabrics_opcode {
1243 nvme_fabrics_command = 0x7f,
1244 };
1245
1246 enum nvmf_capsule_command {
1247 nvme_fabrics_type_property_set = 0x00,
1248 nvme_fabrics_type_connect = 0x01,
1249 nvme_fabrics_type_property_get = 0x04,
1250 };
1251
1252 #define nvme_fabrics_type_name(type) { type, #type }
1253 #define show_fabrics_type_name(type) \
1254 __print_symbolic(type, \
1255 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1256 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1257 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1258
1259 /*
1260 * If not fabrics command, fctype will be ignored.
1261 */
1262 #define show_opcode_name(qid, opcode, fctype) \
1263 ((opcode) == nvme_fabrics_command ? \
1264 show_fabrics_type_name(fctype) : \
1265 ((qid) ? \
1266 show_nvm_opcode_name(opcode) : \
1267 show_admin_opcode_name(opcode)))
1268
1269 struct nvmf_common_command {
1270 __u8 opcode;
1271 __u8 resv1;
1272 __u16 command_id;
1273 __u8 fctype;
1274 __u8 resv2[35];
1275 __u8 ts[24];
1276 };
1277
1278 /*
1279 * The legal cntlid range a NVMe Target will provide.
1280 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1281 * Devices based on earlier specs did not have the subsystem concept;
1282 * therefore, those devices had their cntlid value set to 0 as a result.
1283 */
1284 #define NVME_CNTLID_MIN 1
1285 #define NVME_CNTLID_MAX 0xffef
1286 #define NVME_CNTLID_DYNAMIC 0xffff
1287
1288 #define MAX_DISC_LOGS 255
1289
1290 /* Discovery log page entry */
1291 struct nvmf_disc_rsp_page_entry {
1292 __u8 trtype;
1293 __u8 adrfam;
1294 __u8 subtype;
1295 __u8 treq;
1296 __le16 portid;
1297 __le16 cntlid;
1298 __le16 asqsz;
1299 __u8 resv8[22];
1300 char trsvcid[NVMF_TRSVCID_SIZE];
1301 __u8 resv64[192];
1302 char subnqn[NVMF_NQN_FIELD_LEN];
1303 char traddr[NVMF_TRADDR_SIZE];
1304 union tsas {
1305 char common[NVMF_TSAS_SIZE];
1306 struct rdma {
1307 __u8 qptype;
1308 __u8 prtype;
1309 __u8 cms;
1310 __u8 resv3[5];
1311 __u16 pkey;
1312 __u8 resv10[246];
1313 } rdma;
1314 } tsas;
1315 };
1316
1317 /* Discovery log page header */
1318 struct nvmf_disc_rsp_page_hdr {
1319 __le64 genctr;
1320 __le64 numrec;
1321 __le16 recfmt;
1322 __u8 resv14[1006];
1323 struct nvmf_disc_rsp_page_entry entries[];
1324 };
1325
1326 enum {
1327 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1328 };
1329
1330 struct nvmf_connect_command {
1331 __u8 opcode;
1332 __u8 resv1;
1333 __u16 command_id;
1334 __u8 fctype;
1335 __u8 resv2[19];
1336 union nvme_data_ptr dptr;
1337 __le16 recfmt;
1338 __le16 qid;
1339 __le16 sqsize;
1340 __u8 cattr;
1341 __u8 resv3;
1342 __le32 kato;
1343 __u8 resv4[12];
1344 };
1345
1346 struct nvmf_connect_data {
1347 uuid_t hostid;
1348 __le16 cntlid;
1349 char resv4[238];
1350 char subsysnqn[NVMF_NQN_FIELD_LEN];
1351 char hostnqn[NVMF_NQN_FIELD_LEN];
1352 char resv5[256];
1353 };
1354
1355 struct nvmf_property_set_command {
1356 __u8 opcode;
1357 __u8 resv1;
1358 __u16 command_id;
1359 __u8 fctype;
1360 __u8 resv2[35];
1361 __u8 attrib;
1362 __u8 resv3[3];
1363 __le32 offset;
1364 __le64 value;
1365 __u8 resv4[8];
1366 };
1367
1368 struct nvmf_property_get_command {
1369 __u8 opcode;
1370 __u8 resv1;
1371 __u16 command_id;
1372 __u8 fctype;
1373 __u8 resv2[35];
1374 __u8 attrib;
1375 __u8 resv3[3];
1376 __le32 offset;
1377 __u8 resv4[16];
1378 };
1379
1380 struct nvme_dbbuf {
1381 __u8 opcode;
1382 __u8 flags;
1383 __u16 command_id;
1384 __u32 rsvd1[5];
1385 __le64 prp1;
1386 __le64 prp2;
1387 __u32 rsvd12[6];
1388 };
1389
1390 struct streams_directive_params {
1391 __le16 msl;
1392 __le16 nssa;
1393 __le16 nsso;
1394 __u8 rsvd[10];
1395 __le32 sws;
1396 __le16 sgs;
1397 __le16 nsa;
1398 __le16 nso;
1399 __u8 rsvd2[6];
1400 };
1401
1402 struct nvme_command {
1403 union {
1404 struct nvme_common_command common;
1405 struct nvme_rw_command rw;
1406 struct nvme_identify identify;
1407 struct nvme_features features;
1408 struct nvme_create_cq create_cq;
1409 struct nvme_create_sq create_sq;
1410 struct nvme_delete_queue delete_queue;
1411 struct nvme_download_firmware dlfw;
1412 struct nvme_format_cmd format;
1413 struct nvme_dsm_cmd dsm;
1414 struct nvme_write_zeroes_cmd write_zeroes;
1415 struct nvme_zone_mgmt_send_cmd zms;
1416 struct nvme_zone_mgmt_recv_cmd zmr;
1417 struct nvme_abort_cmd abort;
1418 struct nvme_get_log_page_command get_log_page;
1419 struct nvmf_common_command fabrics;
1420 struct nvmf_connect_command connect;
1421 struct nvmf_property_set_command prop_set;
1422 struct nvmf_property_get_command prop_get;
1423 struct nvme_dbbuf dbbuf;
1424 struct nvme_directive_cmd directive;
1425 };
1426 };
1427
nvme_is_fabrics(struct nvme_command * cmd)1428 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1429 {
1430 return cmd->common.opcode == nvme_fabrics_command;
1431 }
1432
1433 struct nvme_error_slot {
1434 __le64 error_count;
1435 __le16 sqid;
1436 __le16 cmdid;
1437 __le16 status_field;
1438 __le16 param_error_location;
1439 __le64 lba;
1440 __le32 nsid;
1441 __u8 vs;
1442 __u8 resv[3];
1443 __le64 cs;
1444 __u8 resv2[24];
1445 };
1446
nvme_is_write(struct nvme_command * cmd)1447 static inline bool nvme_is_write(struct nvme_command *cmd)
1448 {
1449 /*
1450 * What a mess...
1451 *
1452 * Why can't we simply have a Fabrics In and Fabrics out command?
1453 */
1454 if (unlikely(nvme_is_fabrics(cmd)))
1455 return cmd->fabrics.fctype & 1;
1456 return cmd->common.opcode & 1;
1457 }
1458
1459 enum {
1460 /*
1461 * Generic Command Status:
1462 */
1463 NVME_SC_SUCCESS = 0x0,
1464 NVME_SC_INVALID_OPCODE = 0x1,
1465 NVME_SC_INVALID_FIELD = 0x2,
1466 NVME_SC_CMDID_CONFLICT = 0x3,
1467 NVME_SC_DATA_XFER_ERROR = 0x4,
1468 NVME_SC_POWER_LOSS = 0x5,
1469 NVME_SC_INTERNAL = 0x6,
1470 NVME_SC_ABORT_REQ = 0x7,
1471 NVME_SC_ABORT_QUEUE = 0x8,
1472 NVME_SC_FUSED_FAIL = 0x9,
1473 NVME_SC_FUSED_MISSING = 0xa,
1474 NVME_SC_INVALID_NS = 0xb,
1475 NVME_SC_CMD_SEQ_ERROR = 0xc,
1476 NVME_SC_SGL_INVALID_LAST = 0xd,
1477 NVME_SC_SGL_INVALID_COUNT = 0xe,
1478 NVME_SC_SGL_INVALID_DATA = 0xf,
1479 NVME_SC_SGL_INVALID_METADATA = 0x10,
1480 NVME_SC_SGL_INVALID_TYPE = 0x11,
1481
1482 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1483 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1484
1485 NVME_SC_SANITIZE_FAILED = 0x1C,
1486 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1487
1488 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1489 NVME_SC_CMD_INTERRUPTED = 0x21,
1490
1491 NVME_SC_LBA_RANGE = 0x80,
1492 NVME_SC_CAP_EXCEEDED = 0x81,
1493 NVME_SC_NS_NOT_READY = 0x82,
1494 NVME_SC_RESERVATION_CONFLICT = 0x83,
1495
1496 /*
1497 * Command Specific Status:
1498 */
1499 NVME_SC_CQ_INVALID = 0x100,
1500 NVME_SC_QID_INVALID = 0x101,
1501 NVME_SC_QUEUE_SIZE = 0x102,
1502 NVME_SC_ABORT_LIMIT = 0x103,
1503 NVME_SC_ABORT_MISSING = 0x104,
1504 NVME_SC_ASYNC_LIMIT = 0x105,
1505 NVME_SC_FIRMWARE_SLOT = 0x106,
1506 NVME_SC_FIRMWARE_IMAGE = 0x107,
1507 NVME_SC_INVALID_VECTOR = 0x108,
1508 NVME_SC_INVALID_LOG_PAGE = 0x109,
1509 NVME_SC_INVALID_FORMAT = 0x10a,
1510 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1511 NVME_SC_INVALID_QUEUE = 0x10c,
1512 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1513 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1514 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1515 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1516 NVME_SC_FW_NEEDS_RESET = 0x111,
1517 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1518 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1519 NVME_SC_OVERLAPPING_RANGE = 0x114,
1520 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1521 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1522 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1523 NVME_SC_NS_IS_PRIVATE = 0x119,
1524 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1525 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1526 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1527 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1528 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1529
1530 /*
1531 * I/O Command Set Specific - NVM commands:
1532 */
1533 NVME_SC_BAD_ATTRIBUTES = 0x180,
1534 NVME_SC_INVALID_PI = 0x181,
1535 NVME_SC_READ_ONLY = 0x182,
1536 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1537
1538 /*
1539 * I/O Command Set Specific - Fabrics commands:
1540 */
1541 NVME_SC_CONNECT_FORMAT = 0x180,
1542 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1543 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1544 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1545 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1546
1547 NVME_SC_DISCOVERY_RESTART = 0x190,
1548 NVME_SC_AUTH_REQUIRED = 0x191,
1549
1550 /*
1551 * I/O Command Set Specific - Zoned commands:
1552 */
1553 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1554 NVME_SC_ZONE_FULL = 0x1b9,
1555 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1556 NVME_SC_ZONE_OFFLINE = 0x1bb,
1557 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1558 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1559 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1560 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1561
1562 /*
1563 * Media and Data Integrity Errors:
1564 */
1565 NVME_SC_WRITE_FAULT = 0x280,
1566 NVME_SC_READ_ERROR = 0x281,
1567 NVME_SC_GUARD_CHECK = 0x282,
1568 NVME_SC_APPTAG_CHECK = 0x283,
1569 NVME_SC_REFTAG_CHECK = 0x284,
1570 NVME_SC_COMPARE_FAILED = 0x285,
1571 NVME_SC_ACCESS_DENIED = 0x286,
1572 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1573
1574 /*
1575 * Path-related Errors:
1576 */
1577 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1578 NVME_SC_ANA_INACCESSIBLE = 0x302,
1579 NVME_SC_ANA_TRANSITION = 0x303,
1580 NVME_SC_HOST_PATH_ERROR = 0x370,
1581 NVME_SC_HOST_ABORTED_CMD = 0x371,
1582
1583 NVME_SC_CRD = 0x1800,
1584 NVME_SC_DNR = 0x4000,
1585 };
1586
1587 struct nvme_completion {
1588 /*
1589 * Used by Admin and Fabrics commands to return data:
1590 */
1591 union nvme_result {
1592 __le16 u16;
1593 __le32 u32;
1594 __le64 u64;
1595 } result;
1596 __le16 sq_head; /* how much of this queue may be reclaimed */
1597 __le16 sq_id; /* submission queue that generated this entry */
1598 __u16 command_id; /* of the command which completed */
1599 __le16 status; /* did the command fail, and if so, why? */
1600 };
1601
1602 #define NVME_VS(major, minor, tertiary) \
1603 (((major) << 16) | ((minor) << 8) | (tertiary))
1604
1605 #define NVME_MAJOR(ver) ((ver) >> 16)
1606 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1607 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1608
1609 #endif /* _LINUX_NVME_H */
1610