1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "evergreen_compute.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/list.h"
32 #include "util/u_draw_quad.h"
33 #include "util/u_memory.h"
34 #include "util/format/u_format_s3tc.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/os_time.h"
37 #include "vl/vl_decoder.h"
38 #include "vl/vl_video_buffer.h"
39 #include "radeon_video.h"
40 #include <inttypes.h>
41 #include <sys/utsname.h>
42 #include <stdlib.h>
43
44 #ifdef LLVM_AVAILABLE
45 #include <llvm-c/TargetMachine.h>
46 #endif
47
48 struct r600_multi_fence {
49 struct pipe_reference reference;
50 struct pipe_fence_handle *gfx;
51 struct pipe_fence_handle *sdma;
52
53 /* If the context wasn't flushed at fence creation, this is non-NULL. */
54 struct {
55 struct r600_common_context *ctx;
56 unsigned ib_index;
57 } gfx_unflushed;
58 };
59
60 /*
61 * pipe_context
62 */
63
64 /**
65 * Write an EOP event.
66 *
67 * \param event EVENT_TYPE_*
68 * \param event_flags Optional cache flush flags (TC)
69 * \param data_sel 1 = fence, 3 = timestamp
70 * \param buf Buffer
71 * \param va GPU address
72 * \param old_value Previous fence value (for a bug workaround)
73 * \param new_value Fence value to write for this event.
74 */
r600_gfx_write_event_eop(struct r600_common_context * ctx,unsigned event,unsigned event_flags,unsigned data_sel,struct r600_resource * buf,uint64_t va,uint32_t new_fence,unsigned query_type)75 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
76 unsigned event, unsigned event_flags,
77 unsigned data_sel,
78 struct r600_resource *buf, uint64_t va,
79 uint32_t new_fence, unsigned query_type)
80 {
81 struct radeon_cmdbuf *cs = &ctx->gfx.cs;
82 unsigned op = EVENT_TYPE(event) |
83 EVENT_INDEX(5) |
84 event_flags;
85 unsigned sel = EOP_DATA_SEL(data_sel);
86
87 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
88 radeon_emit(cs, op);
89 radeon_emit(cs, va);
90 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
91 radeon_emit(cs, new_fence); /* immediate data */
92 radeon_emit(cs, 0); /* unused */
93
94 if (buf)
95 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE |
96 RADEON_PRIO_QUERY);
97 }
98
r600_gfx_write_fence_dwords(struct r600_common_screen * screen)99 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
100 {
101 unsigned dwords = 6;
102
103 if (!screen->info.r600_has_virtual_memory)
104 dwords += 2;
105
106 return dwords;
107 }
108
r600_gfx_wait_fence(struct r600_common_context * ctx,struct r600_resource * buf,uint64_t va,uint32_t ref,uint32_t mask)109 void r600_gfx_wait_fence(struct r600_common_context *ctx,
110 struct r600_resource *buf,
111 uint64_t va, uint32_t ref, uint32_t mask)
112 {
113 struct radeon_cmdbuf *cs = &ctx->gfx.cs;
114
115 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
116 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
117 radeon_emit(cs, va);
118 radeon_emit(cs, va >> 32);
119 radeon_emit(cs, ref); /* reference value */
120 radeon_emit(cs, mask); /* mask */
121 radeon_emit(cs, 4); /* poll interval */
122
123 if (buf)
124 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ |
125 RADEON_PRIO_QUERY);
126 }
127
r600_draw_rectangle(struct blitter_context * blitter,void * vertex_elements_cso,blitter_get_vs_func get_vs,int x1,int y1,int x2,int y2,float depth,unsigned num_instances,enum blitter_attrib_type type,const union blitter_attrib * attrib)128 void r600_draw_rectangle(struct blitter_context *blitter,
129 void *vertex_elements_cso,
130 blitter_get_vs_func get_vs,
131 int x1, int y1, int x2, int y2,
132 float depth, unsigned num_instances,
133 enum blitter_attrib_type type,
134 const union blitter_attrib *attrib)
135 {
136 struct r600_common_context *rctx =
137 (struct r600_common_context*)util_blitter_get_pipe(blitter);
138 struct pipe_viewport_state viewport;
139 struct pipe_resource *buf = NULL;
140 unsigned offset = 0;
141 float *vb;
142
143 rctx->b.bind_vertex_elements_state(&rctx->b, vertex_elements_cso);
144 rctx->b.bind_vs_state(&rctx->b, get_vs(blitter));
145
146 /* Some operations (like color resolve on r6xx) don't work
147 * with the conventional primitive types.
148 * One that works is PT_RECTLIST, which we use here. */
149
150 /* setup viewport */
151 viewport.scale[0] = 1.0f;
152 viewport.scale[1] = 1.0f;
153 viewport.scale[2] = 1.0f;
154 viewport.translate[0] = 0.0f;
155 viewport.translate[1] = 0.0f;
156 viewport.translate[2] = 0.0f;
157 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
158
159 /* Upload vertices. The hw rectangle has only 3 vertices,
160 * The 4th one is derived from the first 3.
161 * The vertex specification should match u_blitter's vertex element state. */
162 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
163 rctx->screen->info.tcc_cache_line_size,
164 &offset, &buf, (void**)&vb);
165 if (!buf)
166 return;
167
168 vb[0] = x1;
169 vb[1] = y1;
170 vb[2] = depth;
171 vb[3] = 1;
172
173 vb[8] = x1;
174 vb[9] = y2;
175 vb[10] = depth;
176 vb[11] = 1;
177
178 vb[16] = x2;
179 vb[17] = y1;
180 vb[18] = depth;
181 vb[19] = 1;
182
183 switch (type) {
184 case UTIL_BLITTER_ATTRIB_COLOR:
185 memcpy(vb+4, attrib->color, sizeof(float)*4);
186 memcpy(vb+12, attrib->color, sizeof(float)*4);
187 memcpy(vb+20, attrib->color, sizeof(float)*4);
188 break;
189 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
190 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
191 vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
192 vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
193 /* fall through */
194 vb[4] = attrib->texcoord.x1;
195 vb[5] = attrib->texcoord.y1;
196 vb[12] = attrib->texcoord.x1;
197 vb[13] = attrib->texcoord.y2;
198 vb[20] = attrib->texcoord.x2;
199 vb[21] = attrib->texcoord.y1;
200 break;
201 default:; /* Nothing to do. */
202 }
203
204 /* draw */
205 struct pipe_vertex_buffer vbuffer = {};
206 vbuffer.buffer.resource = buf;
207 vbuffer.stride = 2 * 4 * sizeof(float); /* vertex size */
208 vbuffer.buffer_offset = offset;
209
210 rctx->b.set_vertex_buffers(&rctx->b, blitter->vb_slot, 1, 0, false, &vbuffer);
211 util_draw_arrays_instanced(&rctx->b, R600_PRIM_RECTANGLE_LIST, 0, 3,
212 0, num_instances);
213 pipe_resource_reference(&buf, NULL);
214 }
215
r600_dma_emit_wait_idle(struct r600_common_context * rctx)216 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
217 {
218 struct radeon_cmdbuf *cs = &rctx->dma.cs;
219
220 if (rctx->gfx_level >= EVERGREEN)
221 radeon_emit(cs, 0xf0000000); /* NOP */
222 else {
223 /* TODO: R600-R700 should use the FENCE packet.
224 * CS checker support is required. */
225 }
226 }
227
r600_need_dma_space(struct r600_common_context * ctx,unsigned num_dw,struct r600_resource * dst,struct r600_resource * src)228 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
229 struct r600_resource *dst, struct r600_resource *src)
230 {
231 uint64_t vram = (uint64_t)ctx->dma.cs.used_vram_kb * 1024;
232 uint64_t gtt = (uint64_t)ctx->dma.cs.used_gart_kb * 1024;
233
234 if (dst) {
235 vram += dst->vram_usage;
236 gtt += dst->gart_usage;
237 }
238 if (src) {
239 vram += src->vram_usage;
240 gtt += src->gart_usage;
241 }
242
243 /* Flush the GFX IB if DMA depends on it. */
244 if (radeon_emitted(&ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
245 ((dst &&
246 ctx->ws->cs_is_buffer_referenced(&ctx->gfx.cs, dst->buf,
247 RADEON_USAGE_READWRITE)) ||
248 (src &&
249 ctx->ws->cs_is_buffer_referenced(&ctx->gfx.cs, src->buf,
250 RADEON_USAGE_WRITE))))
251 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
252
253 /* Flush if there's not enough space, or if the memory usage per IB
254 * is too large.
255 *
256 * IBs using too little memory are limited by the IB submission overhead.
257 * IBs using too much memory are limited by the kernel/TTM overhead.
258 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
259 *
260 * This heuristic makes sure that DMA requests are executed
261 * very soon after the call is made and lowers memory usage.
262 * It improves texture upload performance by keeping the DMA
263 * engine busy while uploads are being submitted.
264 */
265 num_dw++; /* for emit_wait_idle below */
266 if (!ctx->ws->cs_check_space(&ctx->dma.cs, num_dw) ||
267 ctx->dma.cs.used_vram_kb + ctx->dma.cs.used_gart_kb > 64 * 1024 ||
268 !radeon_cs_memory_below_limit(ctx->screen, &ctx->dma.cs, vram, gtt)) {
269 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
270 assert((num_dw + ctx->dma.cs.current.cdw) <= ctx->dma.cs.current.max_dw);
271 }
272
273 /* Wait for idle if either buffer has been used in the IB before to
274 * prevent read-after-write hazards.
275 */
276 if ((dst &&
277 ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs, dst->buf,
278 RADEON_USAGE_READWRITE)) ||
279 (src &&
280 ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs, src->buf,
281 RADEON_USAGE_WRITE)))
282 r600_dma_emit_wait_idle(ctx);
283
284 /* If GPUVM is not supported, the CS checker needs 2 entries
285 * in the buffer list per packet, which has to be done manually.
286 */
287 if (ctx->screen->info.r600_has_virtual_memory) {
288 if (dst)
289 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
290 RADEON_USAGE_WRITE);
291 if (src)
292 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
293 RADEON_USAGE_READ);
294 }
295
296 /* this function is called before all DMA calls, so increment this. */
297 ctx->num_dma_calls++;
298 }
299
r600_preflush_suspend_features(struct r600_common_context * ctx)300 void r600_preflush_suspend_features(struct r600_common_context *ctx)
301 {
302 /* suspend queries */
303 if (!list_is_empty(&ctx->active_queries))
304 r600_suspend_queries(ctx);
305
306 ctx->streamout.suspended = false;
307 if (ctx->streamout.begin_emitted) {
308 r600_emit_streamout_end(ctx);
309 ctx->streamout.suspended = true;
310 }
311 }
312
r600_postflush_resume_features(struct r600_common_context * ctx)313 void r600_postflush_resume_features(struct r600_common_context *ctx)
314 {
315 if (ctx->streamout.suspended) {
316 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
317 r600_streamout_buffers_dirty(ctx);
318 }
319
320 /* resume queries */
321 if (!list_is_empty(&ctx->active_queries))
322 r600_resume_queries(ctx);
323 }
324
r600_fence_server_sync(struct pipe_context * ctx,struct pipe_fence_handle * fence)325 static void r600_fence_server_sync(struct pipe_context *ctx,
326 struct pipe_fence_handle *fence)
327 {
328 /* radeon synchronizes all rings by default and will not implement
329 * fence imports.
330 */
331 }
332
r600_flush_from_st(struct pipe_context * ctx,struct pipe_fence_handle ** fence,unsigned flags)333 static void r600_flush_from_st(struct pipe_context *ctx,
334 struct pipe_fence_handle **fence,
335 unsigned flags)
336 {
337 struct pipe_screen *screen = ctx->screen;
338 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
339 struct radeon_winsys *ws = rctx->ws;
340 struct pipe_fence_handle *gfx_fence = NULL;
341 struct pipe_fence_handle *sdma_fence = NULL;
342 bool deferred_fence = false;
343 unsigned rflags = PIPE_FLUSH_ASYNC;
344
345 if (flags & PIPE_FLUSH_END_OF_FRAME)
346 rflags |= PIPE_FLUSH_END_OF_FRAME;
347
348 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
349 if (rctx->dma.cs.priv)
350 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
351
352 if (!radeon_emitted(&rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
353 if (fence)
354 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
355 if (!(flags & PIPE_FLUSH_DEFERRED))
356 ws->cs_sync_flush(&rctx->gfx.cs);
357 } else {
358 /* Instead of flushing, create a deferred fence. Constraints:
359 * - the gallium frontend must allow a deferred flush.
360 * - the gallium frontend must request a fence.
361 * Thread safety in fence_finish must be ensured by the gallium frontend.
362 */
363 if (flags & PIPE_FLUSH_DEFERRED && fence) {
364 gfx_fence = rctx->ws->cs_get_next_fence(&rctx->gfx.cs);
365 deferred_fence = true;
366 } else {
367 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
368 }
369 }
370
371 /* Both engines can signal out of order, so we need to keep both fences. */
372 if (fence) {
373 struct r600_multi_fence *multi_fence =
374 CALLOC_STRUCT(r600_multi_fence);
375 if (!multi_fence) {
376 ws->fence_reference(&sdma_fence, NULL);
377 ws->fence_reference(&gfx_fence, NULL);
378 goto finish;
379 }
380
381 multi_fence->reference.count = 1;
382 /* If both fences are NULL, fence_finish will always return true. */
383 multi_fence->gfx = gfx_fence;
384 multi_fence->sdma = sdma_fence;
385
386 if (deferred_fence) {
387 multi_fence->gfx_unflushed.ctx = rctx;
388 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
389 }
390
391 screen->fence_reference(screen, fence, NULL);
392 *fence = (struct pipe_fence_handle*)multi_fence;
393 }
394 finish:
395 if (!(flags & PIPE_FLUSH_DEFERRED)) {
396 if (rctx->dma.cs.priv)
397 ws->cs_sync_flush(&rctx->dma.cs);
398 ws->cs_sync_flush(&rctx->gfx.cs);
399 }
400 }
401
r600_flush_dma_ring(void * ctx,unsigned flags,struct pipe_fence_handle ** fence)402 static void r600_flush_dma_ring(void *ctx, unsigned flags,
403 struct pipe_fence_handle **fence)
404 {
405 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
406 struct radeon_cmdbuf *cs = &rctx->dma.cs;
407 struct radeon_saved_cs saved;
408 bool check_vm =
409 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
410 rctx->check_vm_faults;
411
412 if (!radeon_emitted(cs, 0)) {
413 if (fence)
414 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
415 return;
416 }
417
418 if (check_vm)
419 radeon_save_cs(rctx->ws, cs, &saved, true);
420
421 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
422 if (fence)
423 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
424
425 if (check_vm) {
426 /* Use conservative timeout 800ms, after which we won't wait any
427 * longer and assume the GPU is hung.
428 */
429 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
430
431 rctx->check_vm_faults(rctx, &saved, AMD_IP_SDMA);
432 radeon_clear_saved_cs(&saved);
433 }
434 }
435
436 /**
437 * Store a linearized copy of all chunks of \p cs together with the buffer
438 * list in \p saved.
439 */
radeon_save_cs(struct radeon_winsys * ws,struct radeon_cmdbuf * cs,struct radeon_saved_cs * saved,bool get_buffer_list)440 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
441 struct radeon_saved_cs *saved, bool get_buffer_list)
442 {
443 uint32_t *buf;
444 unsigned i;
445
446 /* Save the IB chunks. */
447 saved->num_dw = cs->prev_dw + cs->current.cdw;
448 saved->ib = MALLOC(4 * saved->num_dw);
449 if (!saved->ib)
450 goto oom;
451
452 buf = saved->ib;
453 for (i = 0; i < cs->num_prev; ++i) {
454 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
455 buf += cs->prev[i].cdw;
456 }
457 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
458
459 if (!get_buffer_list)
460 return;
461
462 /* Save the buffer list. */
463 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
464 saved->bo_list = CALLOC(saved->bo_count,
465 sizeof(saved->bo_list[0]));
466 if (!saved->bo_list) {
467 FREE(saved->ib);
468 goto oom;
469 }
470 ws->cs_get_buffer_list(cs, saved->bo_list);
471
472 return;
473
474 oom:
475 fprintf(stderr, "%s: out of memory\n", __func__);
476 memset(saved, 0, sizeof(*saved));
477 }
478
radeon_clear_saved_cs(struct radeon_saved_cs * saved)479 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
480 {
481 FREE(saved->ib);
482 FREE(saved->bo_list);
483
484 memset(saved, 0, sizeof(*saved));
485 }
486
r600_get_reset_status(struct pipe_context * ctx)487 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
488 {
489 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
490
491 return rctx->ws->ctx_query_reset_status(rctx->ctx, false, NULL);
492 }
493
r600_set_debug_callback(struct pipe_context * ctx,const struct util_debug_callback * cb)494 static void r600_set_debug_callback(struct pipe_context *ctx,
495 const struct util_debug_callback *cb)
496 {
497 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
498
499 if (cb)
500 rctx->debug = *cb;
501 else
502 memset(&rctx->debug, 0, sizeof(rctx->debug));
503 }
504
r600_set_device_reset_callback(struct pipe_context * ctx,const struct pipe_device_reset_callback * cb)505 static void r600_set_device_reset_callback(struct pipe_context *ctx,
506 const struct pipe_device_reset_callback *cb)
507 {
508 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
509
510 if (cb)
511 rctx->device_reset_callback = *cb;
512 else
513 memset(&rctx->device_reset_callback, 0,
514 sizeof(rctx->device_reset_callback));
515 }
516
r600_check_device_reset(struct r600_common_context * rctx)517 bool r600_check_device_reset(struct r600_common_context *rctx)
518 {
519 enum pipe_reset_status status;
520
521 if (!rctx->device_reset_callback.reset)
522 return false;
523
524 if (!rctx->b.get_device_reset_status)
525 return false;
526
527 status = rctx->b.get_device_reset_status(&rctx->b);
528 if (status == PIPE_NO_RESET)
529 return false;
530
531 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
532 return true;
533 }
534
r600_dma_clear_buffer_fallback(struct pipe_context * ctx,struct pipe_resource * dst,uint64_t offset,uint64_t size,unsigned value)535 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
536 struct pipe_resource *dst,
537 uint64_t offset, uint64_t size,
538 unsigned value)
539 {
540 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
541
542 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
543 }
544
r600_resource_commit(struct pipe_context * pctx,struct pipe_resource * resource,unsigned level,struct pipe_box * box,bool commit)545 static bool r600_resource_commit(struct pipe_context *pctx,
546 struct pipe_resource *resource,
547 unsigned level, struct pipe_box *box,
548 bool commit)
549 {
550 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
551 struct r600_resource *res = r600_resource(resource);
552
553 /*
554 * Since buffer commitment changes cannot be pipelined, we need to
555 * (a) flush any pending commands that refer to the buffer we're about
556 * to change, and
557 * (b) wait for threaded submit to finish, including those that were
558 * triggered by some other, earlier operation.
559 */
560 if (radeon_emitted(&ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
561 ctx->ws->cs_is_buffer_referenced(&ctx->gfx.cs,
562 res->buf, RADEON_USAGE_READWRITE)) {
563 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
564 }
565 if (radeon_emitted(&ctx->dma.cs, 0) &&
566 ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs,
567 res->buf, RADEON_USAGE_READWRITE)) {
568 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
569 }
570
571 ctx->ws->cs_sync_flush(&ctx->dma.cs);
572 ctx->ws->cs_sync_flush(&ctx->gfx.cs);
573
574 assert(resource->target == PIPE_BUFFER);
575
576 return ctx->ws->buffer_commit(ctx->ws, res->buf, box->x, box->width, commit);
577 }
578
r600_common_context_init(struct r600_common_context * rctx,struct r600_common_screen * rscreen,unsigned context_flags)579 bool r600_common_context_init(struct r600_common_context *rctx,
580 struct r600_common_screen *rscreen,
581 unsigned context_flags)
582 {
583 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
584 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
585
586 rctx->screen = rscreen;
587 rctx->ws = rscreen->ws;
588 rctx->family = rscreen->family;
589 rctx->gfx_level = rscreen->gfx_level;
590
591 rctx->b.invalidate_resource = r600_invalidate_resource;
592 rctx->b.resource_commit = r600_resource_commit;
593 rctx->b.buffer_map = r600_buffer_transfer_map;
594 rctx->b.texture_map = r600_texture_transfer_map;
595 rctx->b.transfer_flush_region = r600_buffer_flush_region;
596 rctx->b.buffer_unmap = r600_buffer_transfer_unmap;
597 rctx->b.texture_unmap = r600_texture_transfer_unmap;
598 rctx->b.texture_subdata = u_default_texture_subdata;
599 rctx->b.flush = r600_flush_from_st;
600 rctx->b.set_debug_callback = r600_set_debug_callback;
601 rctx->b.fence_server_sync = r600_fence_server_sync;
602 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
603
604 /* evergreen_compute.c has a special codepath for global buffers.
605 * Everything else can use the direct path.
606 */
607 if ((rscreen->gfx_level == EVERGREEN || rscreen->gfx_level == CAYMAN) &&
608 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
609 rctx->b.buffer_subdata = u_default_buffer_subdata;
610 else
611 rctx->b.buffer_subdata = r600_buffer_subdata;
612
613 rctx->b.get_device_reset_status = r600_get_reset_status;
614 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
615
616 r600_init_context_texture_functions(rctx);
617 r600_init_viewport_functions(rctx);
618 r600_streamout_init(rctx);
619 r600_query_init(rctx);
620 cayman_init_msaa(&rctx->b);
621
622 u_suballocator_init(&rctx->allocator_zeroed_memory, &rctx->b, rscreen->info.gart_page_size,
623 0, PIPE_USAGE_DEFAULT, 0, true);
624
625 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
626 0, PIPE_USAGE_STREAM, 0);
627 if (!rctx->b.stream_uploader)
628 return false;
629
630 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
631 0, PIPE_USAGE_DEFAULT, 0);
632 if (!rctx->b.const_uploader)
633 return false;
634
635 rctx->ctx = rctx->ws->ctx_create(rctx->ws, RADEON_CTX_PRIORITY_MEDIUM);
636 if (!rctx->ctx)
637 return false;
638
639 if (rscreen->info.ip[AMD_IP_SDMA].num_queues && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
640 rctx->ws->cs_create(&rctx->dma.cs, rctx->ctx, AMD_IP_SDMA,
641 r600_flush_dma_ring, rctx, false);
642 rctx->dma.flush = r600_flush_dma_ring;
643 }
644
645 return true;
646 }
647
r600_common_context_cleanup(struct r600_common_context * rctx)648 void r600_common_context_cleanup(struct r600_common_context *rctx)
649 {
650 if (rctx->query_result_shader)
651 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
652
653 rctx->ws->cs_destroy(&rctx->gfx.cs);
654 rctx->ws->cs_destroy(&rctx->dma.cs);
655 if (rctx->ctx)
656 rctx->ws->ctx_destroy(rctx->ctx);
657
658 if (rctx->b.stream_uploader)
659 u_upload_destroy(rctx->b.stream_uploader);
660 if (rctx->b.const_uploader)
661 u_upload_destroy(rctx->b.const_uploader);
662
663 slab_destroy_child(&rctx->pool_transfers);
664 slab_destroy_child(&rctx->pool_transfers_unsync);
665
666 u_suballocator_destroy(&rctx->allocator_zeroed_memory);
667 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
668 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
669 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
670 }
671
672 /*
673 * pipe_screen
674 */
675
676 static const struct debug_named_value common_debug_options[] = {
677 /* logging */
678 { "tex", DBG_TEX, "Print texture info" },
679 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
680 { "compute", DBG_COMPUTE, "Print compute info" },
681 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
682 { "info", DBG_INFO, "Print driver information" },
683
684 /* shaders */
685 { "fs", DBG_FS, "Print fetch shaders" },
686 { "vs", DBG_VS, "Print vertex shaders" },
687 { "gs", DBG_GS, "Print geometry shaders" },
688 { "ps", DBG_PS, "Print pixel shaders" },
689 { "cs", DBG_CS, "Print compute shaders" },
690 { "tcs", DBG_TCS, "Print tessellation control shaders" },
691 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
692 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
693 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
694 { "use_tgsi", DBG_USE_TGSI, "Take TGSI directly instead of using NIR-to-TGSI"},
695
696 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
697 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
698 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
699 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
700
701 /* features */
702 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
703 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
704 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
705 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
706 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
707 { "notiling", DBG_NO_TILING, "Disable tiling" },
708 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
709 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
710 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
711 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
712
713 DEBUG_NAMED_VALUE_END /* must be last */
714 };
715
r600_get_vendor(struct pipe_screen * pscreen)716 static const char* r600_get_vendor(struct pipe_screen* pscreen)
717 {
718 return "X.Org";
719 }
720
r600_get_device_vendor(struct pipe_screen * pscreen)721 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
722 {
723 return "AMD";
724 }
725
r600_get_family_name(const struct r600_common_screen * rscreen)726 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
727 {
728 switch (rscreen->info.family) {
729 case CHIP_R600: return "AMD R600";
730 case CHIP_RV610: return "AMD RV610";
731 case CHIP_RV630: return "AMD RV630";
732 case CHIP_RV670: return "AMD RV670";
733 case CHIP_RV620: return "AMD RV620";
734 case CHIP_RV635: return "AMD RV635";
735 case CHIP_RS780: return "AMD RS780";
736 case CHIP_RS880: return "AMD RS880";
737 case CHIP_RV770: return "AMD RV770";
738 case CHIP_RV730: return "AMD RV730";
739 case CHIP_RV710: return "AMD RV710";
740 case CHIP_RV740: return "AMD RV740";
741 case CHIP_CEDAR: return "AMD CEDAR";
742 case CHIP_REDWOOD: return "AMD REDWOOD";
743 case CHIP_JUNIPER: return "AMD JUNIPER";
744 case CHIP_CYPRESS: return "AMD CYPRESS";
745 case CHIP_HEMLOCK: return "AMD HEMLOCK";
746 case CHIP_PALM: return "AMD PALM";
747 case CHIP_SUMO: return "AMD SUMO";
748 case CHIP_SUMO2: return "AMD SUMO2";
749 case CHIP_BARTS: return "AMD BARTS";
750 case CHIP_TURKS: return "AMD TURKS";
751 case CHIP_CAICOS: return "AMD CAICOS";
752 case CHIP_CAYMAN: return "AMD CAYMAN";
753 case CHIP_ARUBA: return "AMD ARUBA";
754 default: return "AMD unknown";
755 }
756 }
757
r600_disk_cache_create(struct r600_common_screen * rscreen)758 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
759 {
760 /* Don't use the cache if shader dumping is enabled. */
761 if (rscreen->debug_flags & DBG_ALL_SHADERS)
762 return;
763
764 struct mesa_sha1 ctx;
765 unsigned char sha1[20];
766 char cache_id[20 * 2 + 1];
767
768 _mesa_sha1_init(&ctx);
769 if (!disk_cache_get_function_identifier(r600_disk_cache_create,
770 &ctx))
771 return;
772
773 _mesa_sha1_final(&ctx, sha1);
774 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
775
776 /* These flags affect shader compilation. */
777 uint64_t shader_debug_flags =
778 rscreen->debug_flags &
779 (DBG_NIR |
780 DBG_NIR_PREFERRED |
781 DBG_USE_TGSI);
782
783 rscreen->disk_shader_cache =
784 disk_cache_create(r600_get_family_name(rscreen),
785 cache_id,
786 shader_debug_flags);
787 }
788
r600_get_disk_shader_cache(struct pipe_screen * pscreen)789 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
790 {
791 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
792 return rscreen->disk_shader_cache;
793 }
794
r600_get_name(struct pipe_screen * pscreen)795 static const char* r600_get_name(struct pipe_screen* pscreen)
796 {
797 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
798
799 return rscreen->renderer_string;
800 }
801
r600_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)802 static float r600_get_paramf(struct pipe_screen* pscreen,
803 enum pipe_capf param)
804 {
805 switch (param) {
806 case PIPE_CAPF_MIN_LINE_WIDTH:
807 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
808 case PIPE_CAPF_MIN_POINT_SIZE:
809 case PIPE_CAPF_MIN_POINT_SIZE_AA:
810 return 1;
811
812 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
813 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
814 return 0.1;
815
816 case PIPE_CAPF_MAX_LINE_WIDTH:
817 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
818 case PIPE_CAPF_MAX_POINT_SIZE:
819 case PIPE_CAPF_MAX_POINT_SIZE_AA:
820 return 8191.0f;
821 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
822 return 16.0f;
823 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
824 return 16.0f;
825 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
826 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
827 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
828 return 0.0f;
829 }
830 return 0.0f;
831 }
832
r600_get_video_param(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)833 static int r600_get_video_param(struct pipe_screen *screen,
834 enum pipe_video_profile profile,
835 enum pipe_video_entrypoint entrypoint,
836 enum pipe_video_cap param)
837 {
838 switch (param) {
839 case PIPE_VIDEO_CAP_SUPPORTED:
840 return vl_profile_supported(screen, profile, entrypoint);
841 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
842 return 1;
843 case PIPE_VIDEO_CAP_MAX_WIDTH:
844 case PIPE_VIDEO_CAP_MAX_HEIGHT:
845 return vl_video_buffer_max_size(screen);
846 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
847 return PIPE_FORMAT_NV12;
848 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
849 return false;
850 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
851 return false;
852 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
853 return true;
854 case PIPE_VIDEO_CAP_MAX_LEVEL:
855 return vl_level_supported(screen, profile);
856 default:
857 return 0;
858 }
859 }
860
r600_get_llvm_processor_name(enum radeon_family family)861 const char *r600_get_llvm_processor_name(enum radeon_family family)
862 {
863 switch (family) {
864 case CHIP_R600:
865 case CHIP_RV630:
866 case CHIP_RV635:
867 case CHIP_RV670:
868 return "r600";
869 case CHIP_RV610:
870 case CHIP_RV620:
871 case CHIP_RS780:
872 case CHIP_RS880:
873 return "rs880";
874 case CHIP_RV710:
875 return "rv710";
876 case CHIP_RV730:
877 return "rv730";
878 case CHIP_RV740:
879 case CHIP_RV770:
880 return "rv770";
881 case CHIP_PALM:
882 case CHIP_CEDAR:
883 return "cedar";
884 case CHIP_SUMO:
885 case CHIP_SUMO2:
886 return "sumo";
887 case CHIP_REDWOOD:
888 return "redwood";
889 case CHIP_JUNIPER:
890 return "juniper";
891 case CHIP_HEMLOCK:
892 case CHIP_CYPRESS:
893 return "cypress";
894 case CHIP_BARTS:
895 return "barts";
896 case CHIP_TURKS:
897 return "turks";
898 case CHIP_CAICOS:
899 return "caicos";
900 case CHIP_CAYMAN:
901 case CHIP_ARUBA:
902 return "cayman";
903
904 default:
905 return "";
906 }
907 }
908
get_max_threads_per_block(struct r600_common_screen * screen,enum pipe_shader_ir ir_type)909 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
910 enum pipe_shader_ir ir_type)
911 {
912 if (ir_type != PIPE_SHADER_IR_TGSI &&
913 ir_type != PIPE_SHADER_IR_NIR)
914 return 256;
915 if (screen->gfx_level >= EVERGREEN)
916 return 1024;
917 return 256;
918 }
919
r600_get_compute_param(struct pipe_screen * screen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)920 static int r600_get_compute_param(struct pipe_screen *screen,
921 enum pipe_shader_ir ir_type,
922 enum pipe_compute_cap param,
923 void *ret)
924 {
925 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
926
927 //TODO: select these params by asic
928 switch (param) {
929 case PIPE_COMPUTE_CAP_IR_TARGET: {
930 const char *gpu;
931 const char *triple = "r600--";
932 gpu = r600_get_llvm_processor_name(rscreen->family);
933 if (ret) {
934 sprintf(ret, "%s-%s", gpu, triple);
935 }
936 /* +2 for dash and terminating NIL byte */
937 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
938 }
939 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
940 if (ret) {
941 uint64_t *grid_dimension = ret;
942 grid_dimension[0] = 3;
943 }
944 return 1 * sizeof(uint64_t);
945
946 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
947 if (ret) {
948 uint64_t *grid_size = ret;
949 grid_size[0] = 65535;
950 grid_size[1] = 65535;
951 grid_size[2] = 65535;
952 }
953 return 3 * sizeof(uint64_t) ;
954
955 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
956 if (ret) {
957 uint64_t *block_size = ret;
958 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
959 block_size[0] = threads_per_block;
960 block_size[1] = threads_per_block;
961 block_size[2] = threads_per_block;
962 }
963 return 3 * sizeof(uint64_t);
964
965 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
966 if (ret) {
967 uint64_t *max_threads_per_block = ret;
968 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
969 }
970 return sizeof(uint64_t);
971 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
972 if (ret) {
973 uint32_t *address_bits = ret;
974 address_bits[0] = 32;
975 }
976 return 1 * sizeof(uint32_t);
977
978 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
979 if (ret) {
980 uint64_t *max_global_size = ret;
981 uint64_t max_mem_alloc_size;
982
983 r600_get_compute_param(screen, ir_type,
984 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
985 &max_mem_alloc_size);
986
987 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
988 * 1/4 of the MAX_GLOBAL_SIZE. Since the
989 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
990 * make sure we never report more than
991 * 4 * MAX_MEM_ALLOC_SIZE.
992 */
993 *max_global_size = MIN2(4 * max_mem_alloc_size,
994 rscreen->info.max_heap_size_kb * 1024ull);
995 }
996 return sizeof(uint64_t);
997
998 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
999 if (ret) {
1000 uint64_t *max_local_size = ret;
1001 /* Value reported by the closed source driver. */
1002 *max_local_size = 32768;
1003 }
1004 return sizeof(uint64_t);
1005
1006 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1007 if (ret) {
1008 uint64_t *max_input_size = ret;
1009 /* Value reported by the closed source driver. */
1010 *max_input_size = 1024;
1011 }
1012 return sizeof(uint64_t);
1013
1014 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1015 if (ret) {
1016 uint64_t *max_mem_alloc_size = ret;
1017
1018 *max_mem_alloc_size = (rscreen->info.max_heap_size_kb / 4) * 1024ull;
1019 }
1020 return sizeof(uint64_t);
1021
1022 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1023 if (ret) {
1024 uint32_t *max_clock_frequency = ret;
1025 *max_clock_frequency = rscreen->info.max_gpu_freq_mhz;
1026 }
1027 return sizeof(uint32_t);
1028
1029 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1030 if (ret) {
1031 uint32_t *max_compute_units = ret;
1032 *max_compute_units = rscreen->info.num_cu;
1033 }
1034 return sizeof(uint32_t);
1035
1036 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1037 if (ret) {
1038 uint32_t *images_supported = ret;
1039 *images_supported = 0;
1040 }
1041 return sizeof(uint32_t);
1042 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1043 break; /* unused */
1044 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1045 if (ret) {
1046 uint32_t *subgroup_size = ret;
1047 *subgroup_size = r600_wavefront_size(rscreen->family);
1048 }
1049 return sizeof(uint32_t);
1050 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1051 if (ret) {
1052 uint64_t *max_variable_threads_per_block = ret;
1053 *max_variable_threads_per_block = 0;
1054 }
1055 return sizeof(uint64_t);
1056 }
1057
1058 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1059 return 0;
1060 }
1061
r600_get_timestamp(struct pipe_screen * screen)1062 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1063 {
1064 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1065
1066 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1067 rscreen->info.clock_crystal_freq;
1068 }
1069
r600_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** dst,struct pipe_fence_handle * src)1070 static void r600_fence_reference(struct pipe_screen *screen,
1071 struct pipe_fence_handle **dst,
1072 struct pipe_fence_handle *src)
1073 {
1074 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1075 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1076 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1077
1078 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1079 ws->fence_reference(&(*rdst)->gfx, NULL);
1080 ws->fence_reference(&(*rdst)->sdma, NULL);
1081 FREE(*rdst);
1082 }
1083 *rdst = rsrc;
1084 }
1085
r600_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)1086 static bool r600_fence_finish(struct pipe_screen *screen,
1087 struct pipe_context *ctx,
1088 struct pipe_fence_handle *fence,
1089 uint64_t timeout)
1090 {
1091 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1092 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1093 struct r600_common_context *rctx;
1094 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1095
1096 ctx = threaded_context_unwrap_sync(ctx);
1097 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1098
1099 if (rfence->sdma) {
1100 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1101 return false;
1102
1103 /* Recompute the timeout after waiting. */
1104 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1105 int64_t time = os_time_get_nano();
1106 timeout = abs_timeout > time ? abs_timeout - time : 0;
1107 }
1108 }
1109
1110 if (!rfence->gfx)
1111 return true;
1112
1113 /* Flush the gfx IB if it hasn't been flushed yet. */
1114 if (rctx &&
1115 rfence->gfx_unflushed.ctx == rctx &&
1116 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1117 rctx->gfx.flush(rctx, timeout ? 0 : PIPE_FLUSH_ASYNC, NULL);
1118 rfence->gfx_unflushed.ctx = NULL;
1119
1120 if (!timeout)
1121 return false;
1122
1123 /* Recompute the timeout after all that. */
1124 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1125 int64_t time = os_time_get_nano();
1126 timeout = abs_timeout > time ? abs_timeout - time : 0;
1127 }
1128 }
1129
1130 return rws->fence_wait(rws, rfence->gfx, timeout);
1131 }
1132
r600_query_memory_info(struct pipe_screen * screen,struct pipe_memory_info * info)1133 static void r600_query_memory_info(struct pipe_screen *screen,
1134 struct pipe_memory_info *info)
1135 {
1136 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1137 struct radeon_winsys *ws = rscreen->ws;
1138 unsigned vram_usage, gtt_usage;
1139
1140 info->total_device_memory = rscreen->info.vram_size_kb;
1141 info->total_staging_memory = rscreen->info.gart_size_kb;
1142
1143 /* The real TTM memory usage is somewhat random, because:
1144 *
1145 * 1) TTM delays freeing memory, because it can only free it after
1146 * fences expire.
1147 *
1148 * 2) The memory usage can be really low if big VRAM evictions are
1149 * taking place, but the real usage is well above the size of VRAM.
1150 *
1151 * Instead, return statistics of this process.
1152 */
1153 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1154 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1155
1156 info->avail_device_memory =
1157 vram_usage <= info->total_device_memory ?
1158 info->total_device_memory - vram_usage : 0;
1159 info->avail_staging_memory =
1160 gtt_usage <= info->total_staging_memory ?
1161 info->total_staging_memory - gtt_usage : 0;
1162
1163 info->device_memory_evicted =
1164 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1165
1166 /* Just return the number of evicted 64KB pages. */
1167 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1168 }
1169
r600_resource_create_common(struct pipe_screen * screen,const struct pipe_resource * templ)1170 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1171 const struct pipe_resource *templ)
1172 {
1173 if (templ->target == PIPE_BUFFER) {
1174 return r600_buffer_create(screen, templ, 256);
1175 } else {
1176 return r600_texture_create(screen, templ);
1177 }
1178 }
1179
1180 static const void *
r600_get_compiler_options(struct pipe_screen * screen,enum pipe_shader_ir ir,enum pipe_shader_type shader)1181 r600_get_compiler_options(struct pipe_screen *screen,
1182 enum pipe_shader_ir ir,
1183 enum pipe_shader_type shader)
1184 {
1185 assert(ir == PIPE_SHADER_IR_NIR);
1186
1187 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1188
1189 if (shader != PIPE_SHADER_FRAGMENT)
1190 return &rscreen->nir_options;
1191 else
1192 return &rscreen->nir_options_fs;
1193 }
1194
1195 extern bool r600_lower_to_scalar_instr_filter(const nir_instr *instr, const void *);
1196
r600_resource_destroy(struct pipe_screen * screen,struct pipe_resource * res)1197 static void r600_resource_destroy(struct pipe_screen *screen,
1198 struct pipe_resource *res)
1199 {
1200 if (res->target == PIPE_BUFFER) {
1201 if (r600_resource(res)->compute_global_bo)
1202 r600_compute_global_buffer_destroy(screen, res);
1203 else
1204 r600_buffer_destroy(screen, res);
1205 } else {
1206 r600_texture_destroy(screen, res);
1207 }
1208 }
1209
r600_common_screen_init(struct r600_common_screen * rscreen,struct radeon_winsys * ws)1210 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1211 struct radeon_winsys *ws)
1212 {
1213 char family_name[32] = {}, kernel_version[128] = {};
1214 struct utsname uname_data;
1215 const char *chip_name;
1216
1217 ws->query_info(ws, &rscreen->info, false, false);
1218 rscreen->ws = ws;
1219
1220 chip_name = r600_get_family_name(rscreen);
1221
1222 if (uname(&uname_data) == 0)
1223 snprintf(kernel_version, sizeof(kernel_version),
1224 " / %s", uname_data.release);
1225
1226 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1227 "%s (%sDRM %i.%i.%i%s"
1228 #ifdef LLVM_AVAILABLE
1229 ", LLVM " MESA_LLVM_VERSION_STRING
1230 #endif
1231 ")",
1232 chip_name, family_name, rscreen->info.drm_major,
1233 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1234 kernel_version);
1235
1236 rscreen->b.get_name = r600_get_name;
1237 rscreen->b.get_vendor = r600_get_vendor;
1238 rscreen->b.get_device_vendor = r600_get_device_vendor;
1239 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1240 rscreen->b.get_compute_param = r600_get_compute_param;
1241 rscreen->b.get_paramf = r600_get_paramf;
1242 rscreen->b.get_timestamp = r600_get_timestamp;
1243 rscreen->b.get_compiler_options = r600_get_compiler_options;
1244 rscreen->b.fence_finish = r600_fence_finish;
1245 rscreen->b.fence_reference = r600_fence_reference;
1246 rscreen->b.resource_destroy = r600_resource_destroy;
1247 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1248 rscreen->b.query_memory_info = r600_query_memory_info;
1249
1250 if (rscreen->info.ip[AMD_IP_UVD].num_queues) {
1251 rscreen->b.get_video_param = rvid_get_video_param;
1252 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1253 } else {
1254 rscreen->b.get_video_param = r600_get_video_param;
1255 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1256 }
1257
1258 r600_init_screen_texture_functions(rscreen);
1259 r600_init_screen_query_functions(rscreen);
1260
1261 rscreen->family = rscreen->info.family;
1262 rscreen->gfx_level = rscreen->info.gfx_level;
1263 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1264
1265 r600_disk_cache_create(rscreen);
1266
1267 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1268
1269 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1270 if (rscreen->force_aniso >= 0) {
1271 printf("radeon: Forcing anisotropy filter to %ix\n",
1272 /* round down to a power of two */
1273 1 << util_logbase2(rscreen->force_aniso));
1274 }
1275
1276 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1277 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1278
1279 if (rscreen->debug_flags & DBG_INFO) {
1280 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1281 rscreen->info.pci_domain, rscreen->info.pci_bus,
1282 rscreen->info.pci_dev, rscreen->info.pci_func);
1283 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1284 printf("family = %i (%s)\n", rscreen->info.family,
1285 r600_get_family_name(rscreen));
1286 printf("gfx_level = %i\n", rscreen->info.gfx_level);
1287 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1288 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1289 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size_kb, 1024));
1290 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size_kb, 1024));
1291 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size_kb, 1024));
1292 printf("max_heap_size = %i MB\n",
1293 (int)DIV_ROUND_UP(rscreen->info.max_heap_size_kb, 1024));
1294 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1295 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1296 printf("r600_has_virtual_memory = %i\n", rscreen->info.r600_has_virtual_memory);
1297 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1298 printf("ip[AMD_IP_UVD] = %u\n", rscreen->info.ip[AMD_IP_UVD].num_queues);
1299 printf("ip[AMD_IP_SDMA] = %i\n", rscreen->info.ip[AMD_IP_SDMA].num_queues);
1300 printf("ip[AMD_IP_COMPUTE] = %u\n", rscreen->info.ip[AMD_IP_COMPUTE].num_queues);
1301 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1302 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1303 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1304 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1305 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1306 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1307 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1308 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1309 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1310 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1311 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1312
1313 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1314 printf("max_gpu_freq_mhz = %i\n", rscreen->info.max_gpu_freq_mhz);
1315 printf("num_cu = %i\n", rscreen->info.num_cu);
1316 printf("max_se = %i\n", rscreen->info.max_se);
1317 printf("max_sh_per_se = %i\n", rscreen->info.max_sa_per_se);
1318
1319 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1320 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1321 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1322 printf("num_render_backends = %i\n", rscreen->info.max_render_backends);
1323 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1324 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1325 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1326 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1327 }
1328
1329 const struct nir_shader_compiler_options nir_options = {
1330 .fuse_ffma16 = true,
1331 .fuse_ffma32 = true,
1332 .fuse_ffma64 = true,
1333 .lower_flrp32 = true,
1334 .lower_flrp64 = true,
1335 .lower_fdiv = true,
1336 .lower_isign = true,
1337 .lower_fsign = true,
1338 .lower_fmod = true,
1339 .lower_extract_byte = true,
1340 .lower_extract_word = true,
1341 .lower_insert_byte = true,
1342 .lower_insert_word = true,
1343 .lower_rotate = true,
1344 /* due to a bug in the shader compiler, some loops hang
1345 * if they are not unrolled, see:
1346 * https://bugs.freedesktop.org/show_bug.cgi?id=86720
1347 */
1348 .max_unroll_iterations = 255,
1349 .lower_interpolate_at = true,
1350 .vectorize_io = true,
1351 .has_umad24 = true,
1352 .has_umul24 = true,
1353 .has_fmulz = true,
1354 .use_interpolated_input_intrinsics = true,
1355 .has_fsub = true,
1356 .has_isub = true,
1357 .lower_iabs = true,
1358 .lower_uadd_sat = true,
1359 .lower_usub_sat = true,
1360 .lower_bitfield_extract = true,
1361 .lower_bitfield_insert_to_bitfield_select = true,
1362 .has_fused_comp_and_csel = true,
1363 .lower_find_msb_to_reverse = true,
1364 .lower_to_scalar = true,
1365 .lower_to_scalar_filter = r600_lower_to_scalar_instr_filter,
1366 .linker_ignore_precision = true,
1367 .lower_fpow = true,
1368 .lower_int64_options = ~0
1369 };
1370
1371 rscreen->nir_options = nir_options;
1372
1373 if (rscreen->info.family < CHIP_CEDAR)
1374 rscreen->nir_options.force_indirect_unrolling_sampler = true;
1375
1376 if (rscreen->info.gfx_level < EVERGREEN) {
1377 /* Pre-EG doesn't have these ALU ops */
1378 rscreen->nir_options.lower_bit_count = true;
1379 rscreen->nir_options.lower_bitfield_reverse = true;
1380 }
1381
1382 if (rscreen->info.gfx_level < CAYMAN) {
1383 rscreen->nir_options.lower_doubles_options = nir_lower_fp64_full_software;
1384 } else {
1385 rscreen->nir_options.lower_doubles_options =
1386 nir_lower_ddiv |
1387 nir_lower_dfloor |
1388 nir_lower_dceil |
1389 nir_lower_dmod |
1390 nir_lower_dsub |
1391 nir_lower_dtrunc;
1392 }
1393
1394 if (!(rscreen->debug_flags & DBG_NIR_PREFERRED)) {
1395
1396 rscreen->nir_options.lower_fpow = false;
1397 /* TGSI is vector, and NIR-to-TGSI doesn't like it when the
1398 * input vars have been scalarized.
1399 */
1400 rscreen->nir_options.lower_to_scalar = false;
1401
1402 /* NIR-to-TGSI can't do fused integer csel, and it can't just
1403 * override the flag and get the code lowered back when we ask
1404 * it to handle it.
1405 */
1406 rscreen->nir_options.has_fused_comp_and_csel = false;
1407
1408 /* r600 has a bitfield_select and bitfield_extract opcode
1409 * (called bfi/bfe), but TGSI's BFI/BFE isn't that.
1410 */
1411 rscreen->nir_options.lower_bitfield_extract = false;
1412 rscreen->nir_options.lower_bitfield_insert_to_bitfield_select = false;
1413
1414 /* TGSI's ifind is reversed from ours, keep it the TGSI way. */
1415 rscreen->nir_options.lower_find_msb_to_reverse = false;
1416 } else {
1417 rscreen->nir_options.has_fmulz = true;
1418 }
1419
1420 rscreen->nir_options_fs = rscreen->nir_options;
1421 rscreen->nir_options_fs.lower_all_io_to_temps = true;
1422
1423 return true;
1424 }
1425
r600_destroy_common_screen(struct r600_common_screen * rscreen)1426 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1427 {
1428 r600_perfcounters_destroy(rscreen);
1429 r600_gpu_load_kill_thread(rscreen);
1430
1431 mtx_destroy(&rscreen->gpu_load_mutex);
1432 mtx_destroy(&rscreen->aux_context_lock);
1433 rscreen->aux_context->destroy(rscreen->aux_context);
1434
1435 slab_destroy_parent(&rscreen->pool_transfers);
1436
1437 disk_cache_destroy(rscreen->disk_shader_cache);
1438 rscreen->ws->destroy(rscreen->ws);
1439 FREE(rscreen);
1440 }
1441
r600_can_dump_shader(struct r600_common_screen * rscreen,unsigned processor)1442 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1443 unsigned processor)
1444 {
1445 return rscreen->debug_flags & (1 << processor);
1446 }
1447
r600_extra_shader_checks(struct r600_common_screen * rscreen,unsigned processor)1448 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1449 {
1450 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1451 r600_can_dump_shader(rscreen, processor);
1452 }
1453
r600_screen_clear_buffer(struct r600_common_screen * rscreen,struct pipe_resource * dst,uint64_t offset,uint64_t size,unsigned value)1454 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1455 uint64_t offset, uint64_t size, unsigned value)
1456 {
1457 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1458
1459 mtx_lock(&rscreen->aux_context_lock);
1460 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1461 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1462 mtx_unlock(&rscreen->aux_context_lock);
1463 }
1464