1 /*
2 * Copyright © 2021 Valve Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #define AC_SURFACE_INCLUDE_NIR
25 #include "ac_surface.h"
26
27 #include "radv_meta.h"
28 #include "radv_private.h"
29 #include "vk_format.h"
30
31 void
radv_device_finish_meta_copy_vrs_htile_state(struct radv_device * device)32 radv_device_finish_meta_copy_vrs_htile_state(struct radv_device *device)
33 {
34 struct radv_meta_state *state = &device->meta_state;
35
36 radv_DestroyPipeline(radv_device_to_handle(device), state->copy_vrs_htile_pipeline,
37 &state->alloc);
38 radv_DestroyPipelineLayout(radv_device_to_handle(device), state->copy_vrs_htile_p_layout,
39 &state->alloc);
40 device->vk.dispatch_table.DestroyDescriptorSetLayout(
41 radv_device_to_handle(device), state->copy_vrs_htile_ds_layout, &state->alloc);
42 }
43
44 static nir_shader *
build_copy_vrs_htile_shader(struct radv_device * device,struct radeon_surf * surf)45 build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf)
46 {
47 nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "meta_copy_vrs_htile");
48 b.shader->info.workgroup_size[0] = 8;
49 b.shader->info.workgroup_size[1] = 8;
50
51 /* Get coordinates. */
52 nir_ssa_def *global_id = get_global_ids(&b, 2);
53
54 /* Multiply the coordinates by the HTILE block size. */
55 nir_ssa_def *coord = nir_imul_imm(&b, global_id, 8);
56
57 /* Load constants. */
58 nir_ssa_def *constants = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 0), .range = 12);
59 nir_ssa_def *htile_pitch = nir_channel(&b, constants, 0);
60 nir_ssa_def *htile_slice_size = nir_channel(&b, constants, 1);
61 nir_ssa_def *read_htile_value = nir_channel(&b, constants, 2);
62
63 /* Get the HTILE addr from coordinates. */
64 nir_ssa_def *zero = nir_imm_int(&b, 0);
65 nir_ssa_def *htile_addr = ac_nir_htile_addr_from_coord(
66 &b, &device->physical_device->rad_info, &surf->u.gfx9.zs.htile_equation, htile_pitch,
67 htile_slice_size, nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), zero, zero);
68
69 /* Set up the input VRS image descriptor. */
70 const struct glsl_type *vrs_sampler_type =
71 glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_FLOAT);
72 nir_variable *input_vrs_img =
73 nir_variable_create(b.shader, nir_var_uniform, vrs_sampler_type, "input_vrs_image");
74 input_vrs_img->data.descriptor_set = 0;
75 input_vrs_img->data.binding = 0;
76
77 nir_ssa_def *input_vrs_img_deref = &nir_build_deref_var(&b, input_vrs_img)->dest.ssa;
78
79 /* Load the VRS rates from the 2D image. */
80 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
81 tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
82 tex->op = nir_texop_txf;
83 tex->src[0].src_type = nir_tex_src_coord;
84 tex->src[0].src = nir_src_for_ssa(global_id);
85 tex->src[1].src_type = nir_tex_src_lod;
86 tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
87 tex->src[2].src_type = nir_tex_src_texture_deref;
88 tex->src[2].src = nir_src_for_ssa(input_vrs_img_deref);
89 tex->dest_type = nir_type_float32;
90 tex->is_array = false;
91 tex->coord_components = 2;
92
93 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
94 nir_builder_instr_insert(&b, &tex->instr);
95
96 /* Extract the X/Y rates and clamp them because the maximum supported VRS rate is 2x2 (1x1 in
97 * hardware).
98 *
99 * VRS rate X = min(value >> 2, 1)
100 * VRS rate Y = min(value & 3, 1)
101 */
102 nir_ssa_def *x_rate = nir_ushr_imm(&b, nir_channel(&b, &tex->dest.ssa, 0), 2);
103 x_rate = nir_umin(&b, x_rate, nir_imm_int(&b, 1));
104
105 nir_ssa_def *y_rate = nir_iand_imm(&b, nir_channel(&b, &tex->dest.ssa, 0), 3);
106 y_rate = nir_umin(&b, y_rate, nir_imm_int(&b, 1));
107
108 /* Compute the final VRS rate. */
109 nir_ssa_def *vrs_rates = nir_ior(&b, nir_ishl_imm(&b, y_rate, 10), nir_ishl_imm(&b, x_rate, 6));
110
111 /* Load the HTILE buffer descriptor. */
112 nir_ssa_def *htile_buf = radv_meta_load_descriptor(&b, 0, 1);
113
114 /* Load the HTILE value if requested, otherwise use the default value. */
115 nir_variable *htile_value = nir_local_variable_create(b.impl, glsl_int_type(), "htile_value");
116
117 nir_push_if(&b, nir_ieq_imm(&b, read_htile_value, 1));
118 {
119 /* Load the existing HTILE 32-bit value for this 8x8 pixels area. */
120 nir_ssa_def *input_value = nir_load_ssbo(&b, 1, 32, htile_buf, htile_addr);
121
122 /* Clear the 4-bit VRS rates. */
123 nir_store_var(&b, htile_value, nir_iand_imm(&b, input_value, 0xfffff33f), 0x1);
124 }
125 nir_push_else(&b, NULL);
126 {
127 nir_store_var(&b, htile_value, nir_imm_int(&b, 0xfffff33f), 0x1);
128 }
129 nir_pop_if(&b, NULL);
130
131 /* Set the VRS rates loaded from the image. */
132 nir_ssa_def *output_value = nir_ior(&b, nir_load_var(&b, htile_value), vrs_rates);
133
134 /* Store the updated HTILE 32-bit which contains the VRS rates. */
135 nir_store_ssbo(&b, output_value, htile_buf, htile_addr, .access = ACCESS_NON_READABLE);
136
137 return b.shader;
138 }
139
140 static VkResult
radv_device_init_meta_copy_vrs_htile_state(struct radv_device * device,struct radeon_surf * surf)141 radv_device_init_meta_copy_vrs_htile_state(struct radv_device *device,
142 struct radeon_surf *surf)
143 {
144 struct radv_meta_state *state = &device->meta_state;
145 nir_shader *cs = build_copy_vrs_htile_shader(device, surf);
146 VkResult result;
147
148 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
149 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
150 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
151 .bindingCount = 2,
152 .pBindings = (VkDescriptorSetLayoutBinding[]){
153 {.binding = 0,
154 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
155 .descriptorCount = 1,
156 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
157 .pImmutableSamplers = NULL},
158 {.binding = 1,
159 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
160 .descriptorCount = 1,
161 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
162 .pImmutableSamplers = NULL},
163 }};
164
165 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_layout_info,
166 &state->alloc, &state->copy_vrs_htile_ds_layout);
167 if (result != VK_SUCCESS)
168 goto fail;
169
170 VkPipelineLayoutCreateInfo p_layout_info = {
171 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
172 .setLayoutCount = 1,
173 .pSetLayouts = &state->copy_vrs_htile_ds_layout,
174 .pushConstantRangeCount = 1,
175 .pPushConstantRanges =
176 &(VkPushConstantRange){
177 VK_SHADER_STAGE_COMPUTE_BIT,
178 0,
179 12,
180 },
181 };
182
183 result = radv_CreatePipelineLayout(radv_device_to_handle(device), &p_layout_info, &state->alloc,
184 &state->copy_vrs_htile_p_layout);
185 if (result != VK_SUCCESS)
186 goto fail;
187
188 VkPipelineShaderStageCreateInfo shader_stage = {
189 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
190 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
191 .module = vk_shader_module_handle_from_nir(cs),
192 .pName = "main",
193 .pSpecializationInfo = NULL,
194 };
195
196 VkComputePipelineCreateInfo pipeline_info = {
197 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
198 .stage = shader_stage,
199 .flags = 0,
200 .layout = state->copy_vrs_htile_p_layout,
201 };
202
203 result = radv_CreateComputePipelines(radv_device_to_handle(device),
204 radv_pipeline_cache_to_handle(&state->cache), 1,
205 &pipeline_info, NULL, &state->copy_vrs_htile_pipeline);
206 fail:
207 ralloc_free(cs);
208 return result;
209 }
210
211 void
radv_copy_vrs_htile(struct radv_cmd_buffer * cmd_buffer,struct radv_image * vrs_image,VkExtent2D * extent,struct radv_image * dst_image,struct radv_buffer * htile_buffer,bool read_htile_value)212 radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_image,
213 VkExtent2D *extent, struct radv_image *dst_image,
214 struct radv_buffer *htile_buffer, bool read_htile_value)
215 {
216 struct radv_device *device = cmd_buffer->device;
217 struct radv_meta_state *state = &device->meta_state;
218 struct radv_meta_saved_state saved_state;
219 struct radv_image_view vrs_iview;
220
221 assert(radv_image_has_htile(dst_image));
222
223 if (!cmd_buffer->device->meta_state.copy_vrs_htile_pipeline) {
224 VkResult ret = radv_device_init_meta_copy_vrs_htile_state(cmd_buffer->device,
225 &dst_image->planes[0].surface);
226 if (ret != VK_SUCCESS) {
227 cmd_buffer->record_result = ret;
228 return;
229 }
230 }
231
232 cmd_buffer->state.flush_bits |=
233 radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, NULL) |
234 radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, NULL);
235
236 radv_meta_save(
237 &saved_state, cmd_buffer,
238 RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
239
240 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
241 state->copy_vrs_htile_pipeline);
242
243 radv_image_view_init(&vrs_iview, cmd_buffer->device,
244 &(VkImageViewCreateInfo){
245 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
246 .image = radv_image_to_handle(vrs_image),
247 .viewType = VK_IMAGE_VIEW_TYPE_2D,
248 .format = vrs_image->vk.format,
249 .subresourceRange = {.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
250 .baseMipLevel = 0,
251 .levelCount = 1,
252 .baseArrayLayer = 0,
253 .layerCount = 1},
254 },
255 0, NULL);
256
257 radv_meta_push_descriptor_set(
258 cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, state->copy_vrs_htile_p_layout, 0, /* set */
259 2, /* descriptorWriteCount */
260 (VkWriteDescriptorSet[]){
261 {.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
262 .dstBinding = 0,
263 .dstArrayElement = 0,
264 .descriptorCount = 1,
265 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
266 .pImageInfo =
267 (VkDescriptorImageInfo[]){
268 {
269 .sampler = VK_NULL_HANDLE,
270 .imageView = radv_image_view_to_handle(&vrs_iview),
271 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
272 },
273 }},
274 {.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
275 .dstBinding = 1,
276 .dstArrayElement = 0,
277 .descriptorCount = 1,
278 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
279 .pBufferInfo = &(VkDescriptorBufferInfo){.buffer = radv_buffer_to_handle(htile_buffer),
280 .offset = 0,
281 .range = htile_buffer->vk.size}}});
282
283 const unsigned constants[3] = {
284 dst_image->planes[0].surface.meta_pitch, dst_image->planes[0].surface.meta_slice_size,
285 read_htile_value,
286 };
287
288 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), state->copy_vrs_htile_p_layout,
289 VK_SHADER_STAGE_COMPUTE_BIT, 0, 12, constants);
290
291 uint32_t width = DIV_ROUND_UP(extent->width, 8);
292 uint32_t height = DIV_ROUND_UP(extent->height, 8);
293
294 radv_unaligned_dispatch(cmd_buffer, width, height, 1);
295
296 radv_image_view_finish(&vrs_iview);
297
298 radv_meta_restore(&saved_state, cmd_buffer);
299
300 cmd_buffer->state.flush_bits |=
301 RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
302 radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, NULL);
303 }
304