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1 /*
2  * Copyright 2012 Advanced Micro Devices, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * on the rights to use, copy, modify, merge, publish, distribute, sub
9  * license, and/or sell copies of the Software, and to permit persons to whom
10  * the Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #include "si_build_pm4.h"
26 #include "util/u_upload_mgr.h"
27 #include "util/u_viewport.h"
28 
29 #define SI_MAX_SCISSOR 16384
30 
si_get_small_prim_cull_info(struct si_context * sctx,struct si_small_prim_cull_info * out)31 static void si_get_small_prim_cull_info(struct si_context *sctx, struct si_small_prim_cull_info *out)
32 {
33    /* This is needed by the small primitive culling, because it's done
34     * in screen space.
35     */
36    struct si_small_prim_cull_info info;
37    unsigned num_samples = si_get_num_coverage_samples(sctx);
38    assert(num_samples >= 1);
39 
40    info.scale[0] = sctx->viewports.states[0].scale[0];
41    info.scale[1] = sctx->viewports.states[0].scale[1];
42    info.translate[0] = sctx->viewports.states[0].translate[0];
43    info.translate[1] = sctx->viewports.states[0].translate[1];
44 
45    /* The viewport shouldn't flip the X axis for the small prim culling to work. */
46    assert(-info.scale[0] + info.translate[0] <= info.scale[0] + info.translate[0]);
47 
48    /* Compute the line width used by the rasterizer. */
49    float line_width = sctx->queued.named.rasterizer->line_width;
50    if (num_samples == 1)
51       line_width = roundf(line_width);
52    line_width = MAX2(line_width, 1);
53 
54    info.clip_half_line_width[0] = line_width * 0.5 / fabs(info.scale[0]);
55    info.clip_half_line_width[1] = line_width * 0.5 / fabs(info.scale[1]);
56 
57    /* If the Y axis is inverted (OpenGL default framebuffer), reverse it.
58     * This is because the viewport transformation inverts the clip space
59     * bounding box, so min becomes max, which breaks small primitive
60     * culling.
61     */
62    if (sctx->viewport0_y_inverted) {
63       info.scale[1] = -info.scale[1];
64       info.translate[1] = -info.translate[1];
65    }
66 
67    /* This is what the hardware does. */
68    if (!sctx->queued.named.rasterizer->half_pixel_center) {
69       info.translate[0] += 0.5;
70       info.translate[1] += 0.5;
71    }
72 
73    memcpy(info.scale_no_aa, info.scale, sizeof(info.scale));
74    memcpy(info.translate_no_aa, info.translate, sizeof(info.translate));
75 
76    /* Scale the framebuffer up, so that samples become pixels and small
77     * primitive culling is the same for all sample counts.
78     * This only works with the standard DX sample positions, because
79     * the samples are evenly spaced on both X and Y axes.
80     */
81    for (unsigned i = 0; i < 2; i++) {
82       info.scale[i] *= num_samples;
83       info.translate[i] *= num_samples;
84    }
85 
86    *out = info;
87 }
88 
si_emit_cull_state(struct si_context * sctx)89 static void si_emit_cull_state(struct si_context *sctx)
90 {
91    assert(sctx->screen->use_ngg_culling);
92 
93    struct si_small_prim_cull_info info;
94    si_get_small_prim_cull_info(sctx, &info);
95 
96    if (!sctx->small_prim_cull_info_buf ||
97        memcmp(&info, &sctx->last_small_prim_cull_info, sizeof(info))) {
98       unsigned offset = 0;
99 
100       u_upload_data(sctx->b.const_uploader, 0, sizeof(info),
101                     si_optimal_tcc_alignment(sctx, sizeof(info)), &info, &offset,
102                     (struct pipe_resource **)&sctx->small_prim_cull_info_buf);
103 
104       sctx->small_prim_cull_info_address = sctx->small_prim_cull_info_buf->gpu_address + offset;
105       sctx->last_small_prim_cull_info = info;
106    }
107 
108    /* This will end up in SGPR6 as (value << 8), shifted by the hw. */
109    radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->small_prim_cull_info_buf,
110                              RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER);
111    radeon_begin(&sctx->gfx_cs);
112    radeon_set_sh_reg(R_00B230_SPI_SHADER_USER_DATA_GS_0 + GFX9_SGPR_SMALL_PRIM_CULL_INFO * 4,
113                      sctx->small_prim_cull_info_address);
114    radeon_end();
115 
116    /* Better subpixel precision increases the efficiency of small
117     * primitive culling. (more precision means a tighter bounding box
118     * around primitives and more accurate elimination)
119     */
120    unsigned quant_mode = sctx->viewports.as_scissor[0].quant_mode;
121    float small_prim_precision_no_aa = 0;
122    unsigned num_samples = si_get_num_coverage_samples(sctx);
123 
124    if (quant_mode == SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH)
125       small_prim_precision_no_aa = 1.0 / 4096.0;
126    else if (quant_mode == SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH)
127       small_prim_precision_no_aa = 1.0 / 1024.0;
128    else
129       small_prim_precision_no_aa = 1.0 / 256.0;
130 
131    float small_prim_precision = num_samples * small_prim_precision_no_aa;
132 
133    /* Set VS_STATE.SMALL_PRIM_PRECISION for NGG culling.
134     *
135     * small_prim_precision is 1 / 2^n. We only need n between 5 (1/32) and 12 (1/4096).
136     * Such a floating point value can be packed into 4 bits as follows:
137     * If we pass the first 4 bits of the exponent to the shader and set the next 3 bits
138     * to 1, we'll get the number exactly because all other bits are always 0. See:
139     *                                                               1
140     * value  =  (0x70 | value.exponent[0:3]) << 23  =  ------------------------------
141     *                                                  2 ^ (15 - value.exponent[0:3])
142     *
143     * So pass only the first 4 bits of the float exponent to the shader.
144     */
145    SET_FIELD(sctx->current_gs_state, GS_STATE_SMALL_PRIM_PRECISION_NO_AA,
146              (fui(small_prim_precision_no_aa) >> 23) & 0xf);
147    SET_FIELD(sctx->current_gs_state, GS_STATE_SMALL_PRIM_PRECISION,
148              (fui(small_prim_precision) >> 23) & 0xf);
149 }
150 
si_set_scissor_states(struct pipe_context * pctx,unsigned start_slot,unsigned num_scissors,const struct pipe_scissor_state * state)151 static void si_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
152                                   unsigned num_scissors, const struct pipe_scissor_state *state)
153 {
154    struct si_context *ctx = (struct si_context *)pctx;
155    int i;
156 
157    for (i = 0; i < num_scissors; i++)
158       ctx->scissors[start_slot + i] = state[i];
159 
160    if (!ctx->queued.named.rasterizer->scissor_enable)
161       return;
162 
163    si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
164 }
165 
166 /* Since the guard band disables clipping, we have to clip per-pixel
167  * using a scissor.
168  */
si_get_scissor_from_viewport(struct si_context * ctx,const struct pipe_viewport_state * vp,struct si_signed_scissor * scissor)169 static void si_get_scissor_from_viewport(struct si_context *ctx,
170                                          const struct pipe_viewport_state *vp,
171                                          struct si_signed_scissor *scissor)
172 {
173    float tmp, minx, miny, maxx, maxy;
174 
175    /* Convert (-1, -1) and (1, 1) from clip space into window space. */
176    minx = -vp->scale[0] + vp->translate[0];
177    miny = -vp->scale[1] + vp->translate[1];
178    maxx = vp->scale[0] + vp->translate[0];
179    maxy = vp->scale[1] + vp->translate[1];
180 
181    /* Handle inverted viewports. */
182    if (minx > maxx) {
183       tmp = minx;
184       minx = maxx;
185       maxx = tmp;
186    }
187    if (miny > maxy) {
188       tmp = miny;
189       miny = maxy;
190       maxy = tmp;
191    }
192 
193    /* Convert to integer and round up the max bounds. */
194    scissor->minx = minx;
195    scissor->miny = miny;
196    scissor->maxx = ceilf(maxx);
197    scissor->maxy = ceilf(maxy);
198 }
199 
si_clamp_scissor(struct si_context * ctx,struct pipe_scissor_state * out,struct si_signed_scissor * scissor)200 static void si_clamp_scissor(struct si_context *ctx, struct pipe_scissor_state *out,
201                              struct si_signed_scissor *scissor)
202 {
203    out->minx = CLAMP(scissor->minx, 0, SI_MAX_SCISSOR);
204    out->miny = CLAMP(scissor->miny, 0, SI_MAX_SCISSOR);
205    out->maxx = CLAMP(scissor->maxx, 0, SI_MAX_SCISSOR);
206    out->maxy = CLAMP(scissor->maxy, 0, SI_MAX_SCISSOR);
207 }
208 
si_clip_scissor(struct pipe_scissor_state * out,struct pipe_scissor_state * clip)209 static void si_clip_scissor(struct pipe_scissor_state *out, struct pipe_scissor_state *clip)
210 {
211    out->minx = MAX2(out->minx, clip->minx);
212    out->miny = MAX2(out->miny, clip->miny);
213    out->maxx = MIN2(out->maxx, clip->maxx);
214    out->maxy = MIN2(out->maxy, clip->maxy);
215 }
216 
si_scissor_make_union(struct si_signed_scissor * out,struct si_signed_scissor * in)217 static void si_scissor_make_union(struct si_signed_scissor *out, struct si_signed_scissor *in)
218 {
219    out->minx = MIN2(out->minx, in->minx);
220    out->miny = MIN2(out->miny, in->miny);
221    out->maxx = MAX2(out->maxx, in->maxx);
222    out->maxy = MAX2(out->maxy, in->maxy);
223    out->quant_mode = MIN2(out->quant_mode, in->quant_mode);
224 }
225 
si_emit_one_scissor(struct si_context * ctx,struct radeon_cmdbuf * cs,struct si_signed_scissor * vp_scissor,struct pipe_scissor_state * scissor)226 static void si_emit_one_scissor(struct si_context *ctx, struct radeon_cmdbuf *cs,
227                                 struct si_signed_scissor *vp_scissor,
228                                 struct pipe_scissor_state *scissor)
229 {
230    struct pipe_scissor_state final;
231 
232    if (ctx->vs_disables_clipping_viewport) {
233       final.minx = final.miny = 0;
234       final.maxx = final.maxy = SI_MAX_SCISSOR;
235    } else {
236       si_clamp_scissor(ctx, &final, vp_scissor);
237    }
238 
239    if (scissor)
240       si_clip_scissor(&final, scissor);
241 
242    radeon_begin(cs);
243 
244    /* Workaround for a hw bug on GFX6 that occurs when PA_SU_HARDWARE_-
245     * SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
246     */
247    if (ctx->gfx_level == GFX6 && (final.maxx == 0 || final.maxy == 0)) {
248       radeon_emit(S_028250_TL_X(1) | S_028250_TL_Y(1) | S_028250_WINDOW_OFFSET_DISABLE(1));
249       radeon_emit(S_028254_BR_X(1) | S_028254_BR_Y(1));
250       radeon_end();
251       return;
252    }
253 
254    radeon_emit(S_028250_TL_X(final.minx) | S_028250_TL_Y(final.miny) |
255                   S_028250_WINDOW_OFFSET_DISABLE(1));
256    radeon_emit(S_028254_BR_X(final.maxx) | S_028254_BR_Y(final.maxy));
257    radeon_end();
258 }
259 
260 #define MAX_PA_SU_HARDWARE_SCREEN_OFFSET 8176
261 
si_emit_guardband(struct si_context * ctx)262 static void si_emit_guardband(struct si_context *ctx)
263 {
264    const struct si_state_rasterizer *rs = ctx->queued.named.rasterizer;
265    struct si_signed_scissor vp_as_scissor;
266    struct pipe_viewport_state vp;
267    float left, top, right, bottom, max_range, guardband_x, guardband_y;
268    float discard_x, discard_y;
269 
270    if (ctx->vs_writes_viewport_index) {
271       /* Shaders can draw to any viewport. Make a union of all
272        * viewports. */
273       vp_as_scissor = ctx->viewports.as_scissor[0];
274       for (unsigned i = 1; i < SI_MAX_VIEWPORTS; i++) {
275          si_scissor_make_union(&vp_as_scissor, &ctx->viewports.as_scissor[i]);
276       }
277    } else {
278       vp_as_scissor = ctx->viewports.as_scissor[0];
279    }
280 
281    /* Blits don't set the viewport state. The vertex shader determines
282     * the viewport size by scaling the coordinates, so we don't know
283     * how large the viewport is. Assume the worst case.
284     */
285    if (ctx->vs_disables_clipping_viewport)
286       vp_as_scissor.quant_mode = SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;
287 
288    /* Determine the optimal hardware screen offset to center the viewport
289     * within the viewport range in order to maximize the guardband size.
290     */
291    int hw_screen_offset_x = (vp_as_scissor.maxx + vp_as_scissor.minx) / 2;
292    int hw_screen_offset_y = (vp_as_scissor.maxy + vp_as_scissor.miny) / 2;
293 
294    /* GFX6-GFX7 need to align the offset to an ubertile consisting of all SEs. */
295    const unsigned hw_screen_offset_alignment =
296       ctx->gfx_level >= GFX11 ? 32 :
297       ctx->gfx_level >= GFX8 ? 16 : MAX2(ctx->screen->se_tile_repeat, 16);
298 
299    /* Indexed by quantization modes */
300    static int max_viewport_size[] = {65535, 16383, 4095};
301 
302    /* Ensure that the whole viewport stays representable in
303     * absolute coordinates.
304     * See comment in si_set_viewport_states.
305     */
306    assert(vp_as_scissor.maxx <= max_viewport_size[vp_as_scissor.quant_mode] &&
307           vp_as_scissor.maxy <= max_viewport_size[vp_as_scissor.quant_mode]);
308 
309    hw_screen_offset_x = CLAMP(hw_screen_offset_x, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET);
310    hw_screen_offset_y = CLAMP(hw_screen_offset_y, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET);
311 
312    /* Align the screen offset by dropping the low bits. */
313    hw_screen_offset_x &= ~(hw_screen_offset_alignment - 1);
314    hw_screen_offset_y &= ~(hw_screen_offset_alignment - 1);
315 
316    /* Apply the offset to center the viewport and maximize the guardband. */
317    vp_as_scissor.minx -= hw_screen_offset_x;
318    vp_as_scissor.maxx -= hw_screen_offset_x;
319    vp_as_scissor.miny -= hw_screen_offset_y;
320    vp_as_scissor.maxy -= hw_screen_offset_y;
321 
322    /* Reconstruct the viewport transformation from the scissor. */
323    vp.translate[0] = (vp_as_scissor.minx + vp_as_scissor.maxx) / 2.0;
324    vp.translate[1] = (vp_as_scissor.miny + vp_as_scissor.maxy) / 2.0;
325    vp.scale[0] = vp_as_scissor.maxx - vp.translate[0];
326    vp.scale[1] = vp_as_scissor.maxy - vp.translate[1];
327 
328    /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
329    if (vp_as_scissor.minx == vp_as_scissor.maxx)
330       vp.scale[0] = 0.5;
331    if (vp_as_scissor.miny == vp_as_scissor.maxy)
332       vp.scale[1] = 0.5;
333 
334    /* Find the biggest guard band that is inside the supported viewport
335     * range. The guard band is specified as a horizontal and vertical
336     * distance from (0,0) in clip space.
337     *
338     * This is done by applying the inverse viewport transformation
339     * on the viewport limits to get those limits in clip space.
340     *
341     * The viewport range is [-max_viewport_size/2 - 1, max_viewport_size/2].
342     * (-1 to the min coord because max_viewport_size is odd and ViewportBounds
343     * Min/Max are -32768, 32767).
344     */
345    assert(vp_as_scissor.quant_mode < ARRAY_SIZE(max_viewport_size));
346    max_range = max_viewport_size[vp_as_scissor.quant_mode] / 2;
347    left = (-max_range - 1 - vp.translate[0]) / vp.scale[0];
348    right = (max_range - vp.translate[0]) / vp.scale[0];
349    top = (-max_range - 1 - vp.translate[1]) / vp.scale[1];
350    bottom = (max_range - vp.translate[1]) / vp.scale[1];
351 
352    assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
353 
354    guardband_x = MIN2(-left, right);
355    guardband_y = MIN2(-top, bottom);
356 
357    discard_x = 1.0;
358    discard_y = 1.0;
359 
360    if (unlikely(util_prim_is_points_or_lines(ctx->current_rast_prim))) {
361       /* When rendering wide points or lines, we need to be more
362        * conservative about when to discard them entirely. */
363       float pixels;
364 
365       if (ctx->current_rast_prim == PIPE_PRIM_POINTS)
366          pixels = rs->max_point_size;
367       else
368          pixels = rs->line_width;
369 
370       /* Add half the point size / line width */
371       discard_x += pixels / (2.0 * vp.scale[0]);
372       discard_y += pixels / (2.0 * vp.scale[1]);
373 
374       /* Discard primitives that would lie entirely outside the clip
375        * region. */
376       discard_x = MIN2(discard_x, guardband_x);
377       discard_y = MIN2(discard_y, guardband_y);
378    }
379 
380    /* If any of the GB registers is updated, all of them must be updated.
381     * R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
382     * R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
383     */
384    radeon_begin(&ctx->gfx_cs);
385    radeon_opt_set_context_reg4(ctx, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ,
386                                SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, fui(guardband_y), fui(discard_y),
387                                fui(guardband_x), fui(discard_x));
388    radeon_opt_set_context_reg(ctx, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET,
389                               SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
390                               S_028234_HW_SCREEN_OFFSET_X(hw_screen_offset_x >> 4) |
391                                  S_028234_HW_SCREEN_OFFSET_Y(hw_screen_offset_y >> 4));
392    radeon_opt_set_context_reg(
393       ctx, R_028BE4_PA_SU_VTX_CNTL, SI_TRACKED_PA_SU_VTX_CNTL,
394       S_028BE4_PIX_CENTER(rs->half_pixel_center) | S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
395          S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH + vp_as_scissor.quant_mode));
396    radeon_end_update_context_roll(ctx);
397 }
398 
si_emit_scissors(struct si_context * ctx)399 static void si_emit_scissors(struct si_context *ctx)
400 {
401    struct radeon_cmdbuf *cs = &ctx->gfx_cs;
402    struct pipe_scissor_state *states = ctx->scissors;
403    bool scissor_enabled = ctx->queued.named.rasterizer->scissor_enable;
404 
405    /* The simple case: Only 1 viewport is active. */
406    if (!ctx->vs_writes_viewport_index) {
407       struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
408 
409       radeon_begin(cs);
410       radeon_set_context_reg_seq(R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
411       radeon_end();
412 
413       si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] : NULL);
414       return;
415    }
416 
417    /* All registers in the array need to be updated if any of them is changed.
418     * This is a hardware requirement.
419     */
420    radeon_begin(cs);
421    radeon_set_context_reg_seq(R_028250_PA_SC_VPORT_SCISSOR_0_TL, SI_MAX_VIEWPORTS * 2);
422    radeon_end();
423 
424    for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++) {
425       si_emit_one_scissor(ctx, cs, &ctx->viewports.as_scissor[i],
426                           scissor_enabled ? &states[i] : NULL);
427    }
428 }
429 
si_set_viewport_states(struct pipe_context * pctx,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * state)430 static void si_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
431                                    unsigned num_viewports, const struct pipe_viewport_state *state)
432 {
433    struct si_context *ctx = (struct si_context *)pctx;
434    int i;
435 
436    for (i = 0; i < num_viewports; i++) {
437       unsigned index = start_slot + i;
438       struct si_signed_scissor *scissor = &ctx->viewports.as_scissor[index];
439 
440       ctx->viewports.states[index] = state[i];
441 
442       si_get_scissor_from_viewport(ctx, &state[i], scissor);
443 
444       int max_corner = MAX2(
445          MAX2(abs(scissor->maxx), abs(scissor->maxy)),
446          MAX2(abs(scissor->minx), abs(scissor->miny)));
447 
448       /* Determine the best quantization mode (subpixel precision),
449        * but also leave enough space for the guardband.
450        *
451        * Note that primitive binning requires QUANT_MODE == 16_8 on Vega10
452        * and Raven1 for line and rectangle primitive types to work correctly.
453        * Always use 16_8 if primitive binning is possible to occur.
454        */
455       if ((ctx->family == CHIP_VEGA10 || ctx->family == CHIP_RAVEN) && ctx->screen->dpbb_allowed)
456          max_corner = 16384; /* Use QUANT_MODE == 16_8. */
457 
458       /* Another constraint is that all coordinates in the viewport
459        * are representable in fixed point with respect to the
460        * surface origin.
461        *
462        * It means that PA_SU_HARDWARE_SCREEN_OFFSET can't be given
463        * an offset that would make the upper corner of the viewport
464        * greater than the maximum representable number post
465        * quantization, ie 2^quant_bits.
466        *
467        * This does not matter for 14.10 and 16.8 formats since the
468        * offset is already limited at 8k, but it means we can't use
469        * 12.12 if we are drawing to some pixels outside the lower
470        * 4k x 4k of the render target.
471        */
472 
473       if (max_corner <= 1024) /* 4K scanline area for guardband */
474          scissor->quant_mode = SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH;
475       else if (max_corner <= 4096) /* 16K scanline area for guardband */
476          scissor->quant_mode = SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH;
477       else /* 64K scanline area for guardband */
478          scissor->quant_mode = SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;
479    }
480 
481    if (start_slot == 0) {
482       ctx->viewport0_y_inverted =
483          -state->scale[1] + state->translate[1] > state->scale[1] + state->translate[1];
484 
485       /* NGG cull state uses the viewport and quant mode. */
486       if (ctx->screen->use_ngg_culling)
487          si_mark_atom_dirty(ctx, &ctx->atoms.s.ngg_cull_state);
488    }
489 
490    si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
491    si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
492    si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
493 }
494 
si_emit_one_viewport(struct si_context * ctx,struct pipe_viewport_state * state)495 static void si_emit_one_viewport(struct si_context *ctx, struct pipe_viewport_state *state)
496 {
497    struct radeon_cmdbuf *cs = &ctx->gfx_cs;
498 
499    radeon_begin(cs);
500    radeon_emit(fui(state->scale[0]));
501    radeon_emit(fui(state->translate[0]));
502    radeon_emit(fui(state->scale[1]));
503    radeon_emit(fui(state->translate[1]));
504    radeon_emit(fui(state->scale[2]));
505    radeon_emit(fui(state->translate[2]));
506    radeon_end();
507 }
508 
si_emit_viewports(struct si_context * ctx)509 static void si_emit_viewports(struct si_context *ctx)
510 {
511    struct radeon_cmdbuf *cs = &ctx->gfx_cs;
512    struct pipe_viewport_state *states = ctx->viewports.states;
513 
514    /* The simple case: Only 1 viewport is active. */
515    if (!ctx->vs_writes_viewport_index) {
516       radeon_begin(cs);
517       radeon_set_context_reg_seq(R_02843C_PA_CL_VPORT_XSCALE, 6);
518       radeon_end();
519 
520       si_emit_one_viewport(ctx, &states[0]);
521       return;
522    }
523 
524    /* All registers in the array need to be updated if any of them is changed.
525     * This is a hardware requirement.
526     */
527    radeon_begin(cs);
528    radeon_set_context_reg_seq(R_02843C_PA_CL_VPORT_XSCALE + 0, SI_MAX_VIEWPORTS * 6);
529    radeon_end();
530 
531    for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++)
532       si_emit_one_viewport(ctx, &states[i]);
533 }
534 
si_viewport_zmin_zmax(const struct pipe_viewport_state * vp,bool halfz,bool window_space_position,float * zmin,float * zmax)535 static inline void si_viewport_zmin_zmax(const struct pipe_viewport_state *vp, bool halfz,
536                                          bool window_space_position, float *zmin, float *zmax)
537 {
538    if (window_space_position) {
539       *zmin = 0;
540       *zmax = 1;
541       return;
542    }
543    util_viewport_zmin_zmax(vp, halfz, zmin, zmax);
544 }
545 
si_emit_depth_ranges(struct si_context * ctx)546 static void si_emit_depth_ranges(struct si_context *ctx)
547 {
548    struct radeon_cmdbuf *cs = &ctx->gfx_cs;
549    struct pipe_viewport_state *states = ctx->viewports.states;
550    bool clip_halfz = ctx->queued.named.rasterizer->clip_halfz;
551    bool window_space = ctx->vs_disables_clipping_viewport;
552    float zmin, zmax;
553 
554    /* The simple case: Only 1 viewport is active. */
555    if (!ctx->vs_writes_viewport_index) {
556       si_viewport_zmin_zmax(&states[0], clip_halfz, window_space, &zmin, &zmax);
557 
558       radeon_begin(cs);
559       radeon_set_context_reg_seq(R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
560       radeon_emit(fui(zmin));
561       radeon_emit(fui(zmax));
562       radeon_end();
563       return;
564    }
565 
566    /* All registers in the array need to be updated if any of them is changed.
567     * This is a hardware requirement.
568     */
569    radeon_begin(cs);
570    radeon_set_context_reg_seq(R_0282D0_PA_SC_VPORT_ZMIN_0, SI_MAX_VIEWPORTS * 2);
571    for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++) {
572       si_viewport_zmin_zmax(&states[i], clip_halfz, window_space, &zmin, &zmax);
573       radeon_emit(fui(zmin));
574       radeon_emit(fui(zmax));
575    }
576    radeon_end();
577 }
578 
si_emit_viewport_states(struct si_context * ctx)579 static void si_emit_viewport_states(struct si_context *ctx)
580 {
581    si_emit_viewports(ctx);
582    si_emit_depth_ranges(ctx);
583 }
584 
585 /**
586  * This reacts to 2 state changes:
587  * - VS.writes_viewport_index
588  * - VS output position in window space (enable/disable)
589  *
590  * Normally, we only emit 1 viewport and 1 scissor if no shader is using
591  * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
592  * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
593  * called to emit the rest.
594  */
si_update_vs_viewport_state(struct si_context * ctx)595 void si_update_vs_viewport_state(struct si_context *ctx)
596 {
597    struct si_shader_ctx_state *vs = si_get_vs(ctx);
598    struct si_shader_info *info = vs->cso ? &vs->cso->info : NULL;
599    bool vs_window_space;
600 
601    if (!info)
602       return;
603 
604    /* When the VS disables clipping and viewport transformation. */
605    vs_window_space = vs->cso->stage == MESA_SHADER_VERTEX && info->base.vs.window_space_position;
606 
607    if (ctx->vs_disables_clipping_viewport != vs_window_space) {
608       ctx->vs_disables_clipping_viewport = vs_window_space;
609       si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
610       si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
611    }
612 
613    /* Viewport index handling. */
614    if (ctx->vs_writes_viewport_index == info->writes_viewport_index)
615       return;
616 
617    /* This changes how the guardband is computed. */
618    ctx->vs_writes_viewport_index = info->writes_viewport_index;
619    si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
620 
621    /* Emit scissors and viewports that were enabled by having
622     * the ViewportIndex output.
623     */
624    if (info->writes_viewport_index) {
625       si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
626       si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
627    }
628 }
629 
si_emit_window_rectangles(struct si_context * sctx)630 static void si_emit_window_rectangles(struct si_context *sctx)
631 {
632    /* There are four clipping rectangles. Their corner coordinates are inclusive.
633     * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
634     * on whether the pixel is inside cliprects 0-3, respectively. For example,
635     * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
636     * the number 3 (binary 0011).
637     *
638     * If CLIPRECT_RULE & (1 << number), the pixel is rasterized.
639     */
640    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
641    static const unsigned outside[4] = {
642       /* outside rectangle 0 */
643       V_02820C_OUT | V_02820C_IN_1 | V_02820C_IN_2 | V_02820C_IN_21 | V_02820C_IN_3 |
644          V_02820C_IN_31 | V_02820C_IN_32 | V_02820C_IN_321,
645       /* outside rectangles 0, 1 */
646       V_02820C_OUT | V_02820C_IN_2 | V_02820C_IN_3 | V_02820C_IN_32,
647       /* outside rectangles 0, 1, 2 */
648       V_02820C_OUT | V_02820C_IN_3,
649       /* outside rectangles 0, 1, 2, 3 */
650       V_02820C_OUT,
651    };
652    const unsigned disabled = 0xffff; /* all inside and outside cases */
653    unsigned num_rectangles = sctx->num_window_rectangles;
654    struct pipe_scissor_state *rects = sctx->window_rectangles;
655    unsigned rule;
656 
657    assert(num_rectangles <= 4);
658 
659    if (num_rectangles == 0)
660       rule = disabled;
661    else if (sctx->window_rectangles_include)
662       rule = ~outside[num_rectangles - 1];
663    else
664       rule = outside[num_rectangles - 1];
665 
666    radeon_begin(cs);
667    radeon_opt_set_context_reg(sctx, R_02820C_PA_SC_CLIPRECT_RULE, SI_TRACKED_PA_SC_CLIPRECT_RULE,
668                               rule);
669    if (num_rectangles == 0) {
670       radeon_end();
671       return;
672    }
673 
674    radeon_set_context_reg_seq(R_028210_PA_SC_CLIPRECT_0_TL, num_rectangles * 2);
675    for (unsigned i = 0; i < num_rectangles; i++) {
676       radeon_emit(S_028210_TL_X(rects[i].minx) | S_028210_TL_Y(rects[i].miny));
677       radeon_emit(S_028214_BR_X(rects[i].maxx) | S_028214_BR_Y(rects[i].maxy));
678    }
679    radeon_end();
680 }
681 
si_set_window_rectangles(struct pipe_context * ctx,bool include,unsigned num_rectangles,const struct pipe_scissor_state * rects)682 static void si_set_window_rectangles(struct pipe_context *ctx, bool include,
683                                      unsigned num_rectangles,
684                                      const struct pipe_scissor_state *rects)
685 {
686    struct si_context *sctx = (struct si_context *)ctx;
687 
688    sctx->num_window_rectangles = num_rectangles;
689    sctx->window_rectangles_include = include;
690    if (num_rectangles) {
691       memcpy(sctx->window_rectangles, rects, sizeof(*rects) * num_rectangles);
692    }
693 
694    si_mark_atom_dirty(sctx, &sctx->atoms.s.window_rectangles);
695 }
696 
si_init_viewport_functions(struct si_context * ctx)697 void si_init_viewport_functions(struct si_context *ctx)
698 {
699    ctx->atoms.s.guardband.emit = si_emit_guardband;
700    ctx->atoms.s.scissors.emit = si_emit_scissors;
701    ctx->atoms.s.viewports.emit = si_emit_viewport_states;
702    ctx->atoms.s.window_rectangles.emit = si_emit_window_rectangles;
703    ctx->atoms.s.ngg_cull_state.emit = si_emit_cull_state;
704 
705    ctx->b.set_scissor_states = si_set_scissor_states;
706    ctx->b.set_viewport_states = si_set_viewport_states;
707    ctx->b.set_window_rectangles = si_set_window_rectangles;
708 
709    for (unsigned i = 0; i < 16; i++)
710       ctx->viewports.as_scissor[i].quant_mode = SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;
711 }
712