1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> 5 6<enum name="vgt_event_type" varset="chip"> 7 <value name="VS_DEALLOC" value="0"/> 8 <value name="PS_DEALLOC" value="1"/> 9 <value name="VS_DONE_TS" value="2"/> 10 <value name="PS_DONE_TS" value="3"/> 11 <value name="CACHE_FLUSH_TS" value="4"/> 12 <value name="CONTEXT_DONE" value="5"/> 13 <value name="CACHE_FLUSH" value="6"/> 14 <value name="VIZQUERY_START" value="7" variants="A2XX"/> 15 <value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/> 16 <value name="VIZQUERY_END" value="8" variants="A2XX"/> 17 <value name="SC_WAIT_WC" value="9" variants="A2XX"/> 18 <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/> 19 <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/> 20 <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/> 21 <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ --> 22 <value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/> 23 <value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/> 24 <value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/> 25 <value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/> 26 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/> 27 <value name="ZPASS_DONE" value="21"/> 28 <value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/> 29 <value name="RB_DONE_TS" value="22" variants="A3XX-"/> 30 <value name="PERFCOUNTER_START" value="23" variants="A2XX-A4XX"/> 31 <value name="PERFCOUNTER_STOP" value="24" variants="A2XX-A4XX"/> 32 <value name="VS_FETCH_DONE" value="27"/> 33 <value name="FACENESS_FLUSH" value="28" variants="A2XX-A4XX"/> 34 35 <!-- a5xx events --> 36 <value name="WT_DONE_TS" value="8" variants="A5XX-"/> 37 <value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/> 38 <value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/> 39 <value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/> 40 <value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/> 41 <value name="FLUSH_SO_0" value="17" variants="A5XX-"/> 42 <value name="FLUSH_SO_1" value="18" variants="A5XX-"/> 43 <value name="FLUSH_SO_2" value="19" variants="A5XX-"/> 44 <value name="FLUSH_SO_3" value="20" variants="A5XX-"/> 45 <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/> 46 <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/> 47 <value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/> 48 <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/> 49 <value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/> 50 <value name="BLIT" value="30" variants="A5XX-"/> 51 <doc> 52 Clears based on GRAS_LRZ_CNTL configuration, could clear 53 fast-clear buffer or LRZ direction. 54 LRZ direction is stored at lrz_fc_offset + 0x200, has 1 byte which 55 could be expressed by enum: 56 CUR_DIR_DISABLED = 0x0 57 CUR_DIR_GE = 0x1 58 CUR_DIR_LE = 0x2 59 CUR_DIR_UNSET = 0x3 60 Clear of direction means setting the direction to CUR_DIR_UNSET. 61 </doc> 62 <value name="LRZ_CLEAR" value="37" variants="A5XX-"/> 63 <value name="LRZ_FLUSH" value="38" variants="A5XX-"/> 64 <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/> 65 <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-"/> 66 <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/> 67 <value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/> 68 <value name="UNK_2C" value="44" variants="A5XX-"/> 69 <value name="UNK_2D" value="45" variants="A5XX-"/> 70 71 <!-- a6xx events --> 72 <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/> 73 74 <!-- note, some of these are the same as a6xx, just named differently --> 75 <value name="CCU_INVALIDATE_DEPTH" value="24" variants="A7XX"/> 76 <value name="CCU_INVALIDATE_COLOR" value="25" variants="A7XX"/> 77 <value name="CCU_RESOLVE_CLEAN" value="26" variants="A7XX"/> 78 <value name="CCU_FLUSH_DEPTH" value="28" variants="A7XX"/> 79 <value name="CCU_FLUSH_COLOR" value="29" variants="A7XX"/> 80 <value name="CCU_RESOLVE" value="30" variants="A7XX"/> 81 <value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX"/> 82 <value name="CCU_CLEAN_DEPTH" value="32" variants="A7XX"/> 83 <value name="CCU_CLEAN_COLOR" value="33" variants="A7XX"/> 84 <value name="CACHE_RESET" value="48" variants="A7XX"/> 85 <value name="CACHE_CLEAN" value="49" variants="A7XX"/> 86 <!-- TODO: deal with name conflicts with other gens --> 87 <value name="CACHE_FLUSH7" value="50" variants="A7XX"/> 88 <value name="CACHE_INVALIDATE7" value="51" variants="A7XX"/> 89</enum> 90 91<enum name="pc_di_primtype"> 92 <value name="DI_PT_NONE" value="0"/> 93 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: --> 94 <value name="DI_PT_POINTLIST_PSIZE" value="1"/> 95 <value name="DI_PT_LINELIST" value="2"/> 96 <value name="DI_PT_LINESTRIP" value="3"/> 97 <value name="DI_PT_TRILIST" value="4"/> 98 <value name="DI_PT_TRIFAN" value="5"/> 99 <value name="DI_PT_TRISTRIP" value="6"/> 100 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx --> 101 <value name="DI_PT_RECTLIST" value="8"/> 102 <value name="DI_PT_POINTLIST" value="9"/> 103 <value name="DI_PT_LINE_ADJ" value="0xa"/> 104 <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/> 105 <value name="DI_PT_TRI_ADJ" value="0xc"/> 106 <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/> 107 108 <value name="DI_PT_PATCHES0" value="0x1f"/> 109 <value name="DI_PT_PATCHES1" value="0x20"/> 110 <value name="DI_PT_PATCHES2" value="0x21"/> 111 <value name="DI_PT_PATCHES3" value="0x22"/> 112 <value name="DI_PT_PATCHES4" value="0x23"/> 113 <value name="DI_PT_PATCHES5" value="0x24"/> 114 <value name="DI_PT_PATCHES6" value="0x25"/> 115 <value name="DI_PT_PATCHES7" value="0x26"/> 116 <value name="DI_PT_PATCHES8" value="0x27"/> 117 <value name="DI_PT_PATCHES9" value="0x28"/> 118 <value name="DI_PT_PATCHES10" value="0x29"/> 119 <value name="DI_PT_PATCHES11" value="0x2a"/> 120 <value name="DI_PT_PATCHES12" value="0x2b"/> 121 <value name="DI_PT_PATCHES13" value="0x2c"/> 122 <value name="DI_PT_PATCHES14" value="0x2d"/> 123 <value name="DI_PT_PATCHES15" value="0x2e"/> 124 <value name="DI_PT_PATCHES16" value="0x2f"/> 125 <value name="DI_PT_PATCHES17" value="0x30"/> 126 <value name="DI_PT_PATCHES18" value="0x31"/> 127 <value name="DI_PT_PATCHES19" value="0x32"/> 128 <value name="DI_PT_PATCHES20" value="0x33"/> 129 <value name="DI_PT_PATCHES21" value="0x34"/> 130 <value name="DI_PT_PATCHES22" value="0x35"/> 131 <value name="DI_PT_PATCHES23" value="0x36"/> 132 <value name="DI_PT_PATCHES24" value="0x37"/> 133 <value name="DI_PT_PATCHES25" value="0x38"/> 134 <value name="DI_PT_PATCHES26" value="0x39"/> 135 <value name="DI_PT_PATCHES27" value="0x3a"/> 136 <value name="DI_PT_PATCHES28" value="0x3b"/> 137 <value name="DI_PT_PATCHES29" value="0x3c"/> 138 <value name="DI_PT_PATCHES30" value="0x3d"/> 139 <value name="DI_PT_PATCHES31" value="0x3e"/> 140</enum> 141 142<enum name="pc_di_src_sel"> 143 <value name="DI_SRC_SEL_DMA" value="0"/> 144 <value name="DI_SRC_SEL_IMMEDIATE" value="1"/> 145 <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/> 146 <value name="DI_SRC_SEL_AUTO_XFB" value="3"/> 147</enum> 148 149<enum name="pc_di_face_cull_sel"> 150 <value name="DI_FACE_CULL_NONE" value="0"/> 151 <value name="DI_FACE_CULL_FETCH" value="1"/> 152 <value name="DI_FACE_BACKFACE_CULL" value="2"/> 153 <value name="DI_FACE_FRONTFACE_CULL" value="3"/> 154</enum> 155 156<enum name="pc_di_index_size"> 157 <value name="INDEX_SIZE_IGN" value="0"/> 158 <value name="INDEX_SIZE_16_BIT" value="0"/> 159 <value name="INDEX_SIZE_32_BIT" value="1"/> 160 <value name="INDEX_SIZE_8_BIT" value="2"/> 161 <value name="INDEX_SIZE_INVALID"/> 162</enum> 163 164<enum name="pc_di_vis_cull_mode"> 165 <value name="IGNORE_VISIBILITY" value="0"/> 166 <value name="USE_VISIBILITY" value="1"/> 167</enum> 168 169<enum name="adreno_pm4_packet_type"> 170 <value name="CP_TYPE0_PKT" value="0x00000000"/> 171 <value name="CP_TYPE1_PKT" value="0x40000000"/> 172 <value name="CP_TYPE2_PKT" value="0x80000000"/> 173 <value name="CP_TYPE3_PKT" value="0xc0000000"/> 174 <value name="CP_TYPE4_PKT" value="0x40000000"/> 175 <value name="CP_TYPE7_PKT" value="0x70000000"/> 176</enum> 177 178<!-- 179 Note that in some cases, the same packet id is recycled on a later 180 generation, so variants attribute is used to distinguish. They 181 may not be completely accurate, we would probably have to analyze 182 the pfp and me/pm4 firmware to verify the packet is actually 183 handled on a particular generation. But it is at least enough to 184 disambiguate the packet-id's that were re-used for different 185 packets starting with a5xx. 186 --> 187<enum name="adreno_pm4_type3_packets" varset="chip"> 188 <doc>initialize CP's micro-engine</doc> 189 <value name="CP_ME_INIT" value="0x48"/> 190 <doc>skip N 32-bit words to get to the next packet</doc> 191 <value name="CP_NOP" value="0x10"/> 192 <doc> 193 indirect buffer dispatch. prefetch parser uses this packet 194 type to determine whether to pre-fetch the IB 195 </doc> 196 <value name="CP_PREEMPT_ENABLE" value="0x1c"/> 197 <value name="CP_PREEMPT_TOKEN" value="0x1e"/> 198 <value name="CP_INDIRECT_BUFFER" value="0x3f"/> 199 <doc> 200 Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to 201 another buffer at the same level. Must be at the end of IB, and 202 doesn't work with draw state IB's. 203 </doc> 204 <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/> 205 <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc> 206 <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/> 207 <doc>wait for the IDLE state of the engine</doc> 208 <value name="CP_WAIT_FOR_IDLE" value="0x26"/> 209 <doc>wait until a register or memory location is a specific value</doc> 210 <value name="CP_WAIT_REG_MEM" value="0x3c"/> 211 <doc>wait until a register location is equal to a specific value</doc> 212 <value name="CP_WAIT_REG_EQ" value="0x52"/> 213 <doc>wait until a register location is >= a specific value</doc> 214 <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX-A4XX"/> 215 <doc>wait until a read completes</doc> 216 <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX-A4XX"/> 217 <doc>wait until all base/size writes from an IB_PFD packet have completed</doc> 218 <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/> 219 <doc>register read/modify/write</doc> 220 <value name="CP_REG_RMW" value="0x21"/> 221 <doc>Set binning configuration registers</doc> 222 <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX-A4XX"/> 223 <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX-"/> 224 <doc>reads register in chip and writes to memory</doc> 225 <value name="CP_REG_TO_MEM" value="0x3e"/> 226 <doc>write N 32-bit words to memory</doc> 227 <value name="CP_MEM_WRITE" value="0x3d"/> 228 <doc>write CP_PROG_COUNTER value to memory</doc> 229 <value name="CP_MEM_WRITE_CNTR" value="0x4f"/> 230 <doc>conditional execution of a sequence of packets</doc> 231 <value name="CP_COND_EXEC" value="0x44"/> 232 <doc>conditional write to memory or register</doc> 233 <value name="CP_COND_WRITE" value="0x45" variants="A2XX-A4XX"/> 234 <value name="CP_COND_WRITE5" value="0x45" variants="A5XX-"/> 235 <doc>generate an event that creates a write to memory when completed</doc> 236 <value name="CP_EVENT_WRITE" value="0x46"/> 237 <doc>generate a VS|PS_done event</doc> 238 <value name="CP_EVENT_WRITE_SHD" value="0x58"/> 239 <doc>generate a cache flush done event</doc> 240 <value name="CP_EVENT_WRITE_CFL" value="0x59"/> 241 <doc>generate a z_pass done event</doc> 242 <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/> 243 <doc> 244 not sure the real name, but this seems to be what is used for 245 opencl, instead of CP_DRAW_INDX.. 246 </doc> 247 <value name="CP_RUN_OPENCL" value="0x31"/> 248 <doc>initiate fetch of index buffer and draw</doc> 249 <value name="CP_DRAW_INDX" value="0x22"/> 250 <doc>draw using supplied indices in packet</doc> 251 <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX-A4XX"/> <!-- this is something different on a6xx and unused on a5xx --> 252 <doc>initiate fetch of index buffer and binIDs and draw</doc> 253 <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX-A4XX"/> 254 <doc>initiate fetch of bin IDs and draw using supplied indices</doc> 255 <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX-A4XX"/> 256 <doc>begin/end initiator for viz query extent processing</doc> 257 <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX-A4XX"/> 258 <doc>fetch state sub-blocks and initiate shader code DMAs</doc> 259 <value name="CP_SET_STATE" value="0x25"/> 260 <doc>load constant into chip and to memory</doc> 261 <value name="CP_SET_CONSTANT" value="0x2d"/> 262 <doc>load sequencer instruction memory (pointer-based)</doc> 263 <value name="CP_IM_LOAD" value="0x27"/> 264 <doc>load sequencer instruction memory (code embedded in packet)</doc> 265 <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/> 266 <doc>load constants from a location in memory</doc> 267 <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/> 268 <doc>selective invalidation of state pointers</doc> 269 <value name="CP_INVALIDATE_STATE" value="0x3b"/> 270 <doc>dynamically changes shader instruction memory partition</doc> 271 <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX-A4XX"/> 272 <doc>sets the 64-bit BIN_MASK register in the PFP</doc> 273 <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX-A4XX"/> 274 <doc>sets the 64-bit BIN_SELECT register in the PFP</doc> 275 <value name="CP_SET_BIN_SELECT" value="0x51" variants="A2XX-A4XX"/> 276 <doc>updates the current context, if needed</doc> 277 <value name="CP_CONTEXT_UPDATE" value="0x5e"/> 278 <doc>generate interrupt from the command stream</doc> 279 <value name="CP_INTERRUPT" value="0x40"/> 280 <doc>copy sequencer instruction memory to system memory</doc> 281 <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/> 282 283 <!-- For a20x --> 284<!-- TODO handle variants.. 285 <doc> 286 Program an offset that will added to the BIN_BASE value of 287 the 3D_DRAW_INDX_BIN packet 288 </doc> 289 <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/> 290 --> 291 292 <!-- for a22x --> 293 <doc> 294 sets draw initiator flags register in PFP, gets bitwise-ORed into 295 every draw initiator 296 </doc> 297 <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/> 298 <doc>sets the register protection mode</doc> 299 <value name="CP_SET_PROTECTED_MODE" value="0x5f"/> 300 301 <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/> 302 303 <!-- for a3xx --> 304 <doc>load high level sequencer command</doc> 305 <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/> 306 <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/> 307 <doc>Conditionally load a IB based on a flag, prefetch enabled</doc> 308 <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/> 309 <doc>Conditionally load a IB based on a flag, prefetch disabled</doc> 310 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/> 311 <doc>Load a buffer with pre-fetch enabled</doc> 312 <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/> 313 <doc>Set bin (?)</doc> 314 <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/> 315 316 <doc>test 2 memory locations to dword values specified</doc> 317 <value name="CP_TEST_TWO_MEMS" value="0x71"/> 318 319 <doc>Write register, ignoring context state for context sensitive registers</doc> 320 <value name="CP_REG_WR_NO_CTXT" value="0x78"/> 321 322 <doc>Record the real-time when this packet is processed by PFP</doc> 323 <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/> 324 325 <!-- Used to switch GPU between secure and non-secure modes --> 326 <value name="CP_SET_SECURE_MODE" value="0x66"/> 327 328 <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc> 329 <value name="CP_WAIT_FOR_ME" value="0x13"/> 330 331 <!-- for a4xx --> 332 <doc> 333 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple 334 groups of registers. Looks like it can be used to create state 335 objects in GPU memory, and on state change only emit pointer 336 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU 337 overhead: 338 339 (A4x) save PM4 stream pointers to execute upon a visible draw 340 </doc> 341 <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX-"/> 342 <value name="CP_DRAW_INDX_OFFSET" value="0x38"/> 343 <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX-"/> 344 <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX-"/> 345 <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX"/> 346 <value name="CP_DRAW_AUTO" value="0x24"/> 347 348 <doc> 349 Enable or disable predication globally. Also resets the 350 predicate to "passing" and the local bit to enabled when 351 enabling global predication. 352 </doc> 353 <value name="CP_DRAW_PRED_ENABLE_GLOBAL" value="0x19"/> 354 355 <doc> 356 Enable or disable predication locally. Unlike globally enabling 357 predication, this packet doesn't touch any other state. 358 Predication only happens when enabled globally and locally and a 359 predicate has been set. This should be used for internal draws 360 which aren't supposed to use the predication state: 361 362 CP_DRAW_PRED_ENABLE_LOCAL(0) 363 ... do draw... 364 CP_DRAW_PRED_ENABLE_LOCAL(1) 365 </doc> 366 <value name="CP_DRAW_PRED_ENABLE_LOCAL" value="0x1a"/> 367 368 <doc> 369 Latch a draw predicate into the internal register. 370 </doc> 371 <value name="CP_DRAW_PRED_SET" value="0x4e"/> 372 373 <doc> 374 for A4xx 375 Write to register with address that does not fit into type-0 pkt 376 </doc> 377 <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/> 378 379 <doc>copy from ME scratch RAM to a register</doc> 380 <value name="CP_SCRATCH_TO_REG" value="0x4d"/> 381 382 <doc>Copy from REG to ME scratch RAM</doc> 383 <value name="CP_REG_TO_SCRATCH" value="0x4a"/> 384 385 <doc>Wait for memory writes to complete</doc> 386 <value name="CP_WAIT_MEM_WRITES" value="0x12"/> 387 388 <doc>Conditional execution based on register comparison</doc> 389 <value name="CP_COND_REG_EXEC" value="0x47"/> 390 391 <doc>Memory to REG copy</doc> 392 <value name="CP_MEM_TO_REG" value="0x42"/> 393 394 <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX-"/> 395 <value name="CP_EXEC_CS" value="0x33"/> 396 397 <doc> 398 for a5xx 399 </doc> 400 <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/> 401 <!-- switches SMMU pagetable, used on a5xx+ only --> 402 <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX-"/> 403 <!-- for a6xx --> 404 <doc>Tells CP the current mode of GPU operation</doc> 405 <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/> 406 <doc>Instruct CP to set a few internal CP registers</doc> 407 <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/> 408 <!-- 409 pairs of regid and value.. seems to be used to program some TF 410 related regs: 411 --> 412 <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX-"/> 413 <!-- A5XX Enable yield in RB only --> 414 <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/> 415 <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX-"/> 416 <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX-"/> 417 <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX-"/> 418 <value name="CP_WHERE_AM_I" value="0x62" variants="A5XX-"/> 419 <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX-"/> 420 <!-- Enable/Disable/Defer A5x global preemption model --> 421 <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/> 422 <!-- Enable/Disable A5x local preemption model --> 423 <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/> 424 <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx --> 425 <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX"/> 426 <!-- Inform CP about current render mode (needed for a5xx preemption) --> 427 <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/> 428 <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/> 429 <!-- check if this works on earlier.. --> 430 <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX-"/> 431 <value name="CP_BLIT" value="0x2c" variants="A5XX-"/> 432 433 <!-- Test specified bit in specified register and set predicate --> 434 <value name="CP_REG_TEST" value="0x39" variants="A5XX-"/> 435 436 <!-- 437 Seems to set the mode flags which control which CP_SET_DRAW_STATE 438 packets are executed, based on their ENABLE_MASK values 439 440 CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE 441 packets w/ ENABLE_MASK & 0x6 to execute immediately 442 --> 443 <value name="CP_SET_MODE" value="0x63" variants="A6XX"/> 444 445 <!-- 446 Seems like there are now separate blocks of state for VS vs FS/CS 447 (probably these amounts to geometry vs fragments so that geometry 448 stage of the pipeline for next draw can start while fragment stage 449 of current draw is still running. The format of the payload of the 450 packets is the same, the only difference is the offsets of the regs 451 the firmware code that handles the packet writes. 452 453 Note that for CL, starting with a6xx, the preferred # of local 454 threads is no longer the same as the max, implying that the shader 455 core can now run warps from unrelated shaders (ie. 456 CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs 457 CL_KERNEL_WORK_GROUP_SIZE) 458 --> 459 <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/> 460 <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/> 461 <!-- 462 Note: For IBO state (Image/SSBOs) which have shared state across 463 shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for 464 compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are 465 interchangable. 466 --> 467 <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/> 468 469 <!-- internal packets: --> 470 <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/> 471 <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/> 472 <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/> 473 <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/> 474 <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/> 475 <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/> 476 <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/> 477 <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/> 478 479 <!-- jmptable entry used to handle type4 packet on a5xx+: --> 480 <value name="PKT4" value="0x04" variants="A5XX-"/> 481 482 <!-- TODO do these exist on A5xx? --> 483 <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/> 484 <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX"/> 485 <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX"/> 486 <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/> 487 <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/> 488 <value name="CP_MEMCPY" value="0x75" variants="A6XX"/> 489 <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX"/> 490 <!-- Note, kgsl calls this CP_SET_AMBLE: --> 491 <value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX"/> 492 493 <!-- 494 Seems to always have the payload: 495 00000002 00008801 00004010 496 or: 497 00000002 00008801 00004090 498 or: 499 00000002 00008801 00000010 500 00000002 00008801 00010010 501 00000002 00008801 00d64010 502 ... 503 Note set for compute shaders.. 504 Is 0x8801 a register offset? 505 This appears to be a special sort of register write packet 506 more or less, but the firmware has some special handling.. 507 Seems like it intercepts/modifies certain register offsets, 508 but others are treated like a normal PKT4 reg write. I 509 guess there are some registers that the fw controls certain 510 bits. 511 --> 512 <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/> 513 514 <doc> 515 These first appear in a650_sqe.bin. They can in theory be used 516 to loop any sequence of IB1 commands, but in practice they are 517 used to loop over bins. There is a fixed-size per-iteration 518 prefix, used to set per-bin state, and then the following IB1 519 commands are executed until CP_END_BIN which are always the same 520 for each iteration and usually contain a list of 521 CP_INDIRECT_BUFFER calls to IB2 commands which setup state and 522 execute restore/draw/save commands. This replaces the previous 523 technique of just repeating the CP_INDIRECT_BUFFER calls and 524 "unrolling" the loop. 525 </doc> 526 <value name="CP_START_BIN" value="0x50" variants="A6XX"/> 527 <value name="CP_END_BIN" value="0x51" variants="A6XX"/> 528 529 <value name="CP_WAIT_TIMESTAMP" value="0x14" variants="A7XX-"/> 530 <value name="CP_THREAD_CONTROL" value="0x17" variants="A7XX-"/> 531</enum> 532 533 534<domain name="CP_LOAD_STATE" width="32"> 535 <doc>Load state, a3xx (and later?)</doc> 536 <enum name="adreno_state_block"> 537 <value name="SB_VERT_TEX" value="0"/> 538 <value name="SB_VERT_MIPADDR" value="1"/> 539 <value name="SB_FRAG_TEX" value="2"/> 540 <value name="SB_FRAG_MIPADDR" value="3"/> 541 <value name="SB_VERT_SHADER" value="4"/> 542 <value name="SB_GEOM_SHADER" value="5"/> 543 <value name="SB_FRAG_SHADER" value="6"/> 544 <value name="SB_COMPUTE_SHADER" value="7"/> 545 </enum> 546 <enum name="adreno_state_type"> 547 <value name="ST_SHADER" value="0"/> 548 <value name="ST_CONSTANTS" value="1"/> 549 </enum> 550 <enum name="adreno_state_src"> 551 <value name="SS_DIRECT" value="0"> 552 <doc>inline with the CP_LOAD_STATE packet</doc> 553 </value> 554 <value name="SS_INVALID_ALL_IC" value="2"/> 555 <value name="SS_INVALID_PART_IC" value="3"/> 556 <value name="SS_INDIRECT" value="4"> 557 <doc>in buffer pointed to by EXT_SRC_ADDR</doc> 558 </value> 559 <value name="SS_INDIRECT_TCM" value="5"/> 560 <value name="SS_INDIRECT_STM" value="6"/> 561 </enum> 562 <reg32 offset="0" name="0"> 563 <bitfield name="DST_OFF" low="0" high="15" type="uint"/> 564 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/> 565 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/> 566 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 567 </reg32> 568 <reg32 offset="1" name="1"> 569 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/> 570 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 571 </reg32> 572</domain> 573 574<domain name="CP_LOAD_STATE4" width="32" varset="chip"> 575 <doc>Load state, a4xx+</doc> 576 <enum name="a4xx_state_block"> 577 <!-- 578 unknown: 0x7 and 0xf <- seen in compute shader 579 580 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption? 581 Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains 582 the gpuaddr of the following shader constants block. DST_OFF seems 583 to specify which shader stage: 584 585 16 -> vert 586 36 -> tcs 587 56 -> tes 588 76 -> geom 589 96 -> frag 590 591 Example: 592 593opcode: CP_LOAD_STATE4 (30) (12 dwords) 594 { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 } 595 { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 } 596 { EXT_SRC_ADDR_HI = 0 } 597 0000: c0264100 00000000 00000000 00000000 598 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000 599 600opcode: CP_LOAD_STATE4 (30) (4 dwords) 601 { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 602 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 } 603 { EXT_SRC_ADDR_HI = 0 } 604 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 605 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 606 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000 607 608 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords. 609 610 --> 611 <value name="SB4_VS_TEX" value="0x0"/> 612 <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS --> 613 <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES --> 614 <value name="SB4_GS_TEX" value="0x3"/> 615 <value name="SB4_FS_TEX" value="0x4"/> 616 <value name="SB4_CS_TEX" value="0x5"/> 617 <value name="SB4_VS_SHADER" value="0x8"/> 618 <value name="SB4_HS_SHADER" value="0x9"/> 619 <value name="SB4_DS_SHADER" value="0xa"/> 620 <value name="SB4_GS_SHADER" value="0xb"/> 621 <value name="SB4_FS_SHADER" value="0xc"/> 622 <value name="SB4_CS_SHADER" value="0xd"/> 623 <!-- 624 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each), 625 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each) 626 627 Compute has it's own dedicated SSBO state, it seems, but the rest 628 of the stages share state 629 --> 630 <value name="SB4_SSBO" value="0xe"/> 631 <value name="SB4_CS_SSBO" value="0xf"/> 632 </enum> 633 <enum name="a4xx_state_type"> 634 <value name="ST4_SHADER" value="0"/> 635 <value name="ST4_CONSTANTS" value="1"/> 636 <value name="ST4_UBO" value="2"/> 637 </enum> 638 <enum name="a4xx_state_src"> 639 <value name="SS4_DIRECT" value="0"/> 640 <value name="SS4_INDIRECT" value="2"/> 641 </enum> 642 <reg32 offset="0" name="0"> 643 <bitfield name="DST_OFF" low="0" high="13" type="uint"/> 644 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/> 645 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/> 646 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 647 </reg32> 648 <reg32 offset="1" name="1"> 649 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/> 650 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 651 </reg32> 652 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 653 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/> 654 </reg32> 655</domain> 656 657<!-- looks basically same CP_LOAD_STATE4 --> 658<domain name="CP_LOAD_STATE6" width="32" varset="chip"> 659 <doc>Load state, a6xx+</doc> 660 <enum name="a6xx_state_block"> 661 <value name="SB6_VS_TEX" value="0x0"/> 662 <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS --> 663 <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES --> 664 <value name="SB6_GS_TEX" value="0x3"/> 665 <value name="SB6_FS_TEX" value="0x4"/> 666 <value name="SB6_CS_TEX" value="0x5"/> 667 <value name="SB6_VS_SHADER" value="0x8"/> 668 <value name="SB6_HS_SHADER" value="0x9"/> 669 <value name="SB6_DS_SHADER" value="0xa"/> 670 <value name="SB6_GS_SHADER" value="0xb"/> 671 <value name="SB6_FS_SHADER" value="0xc"/> 672 <value name="SB6_CS_SHADER" value="0xd"/> 673 <value name="SB6_IBO" value="0xe"/> 674 <value name="SB6_CS_IBO" value="0xf"/> 675 </enum> 676 <enum name="a6xx_state_type"> 677 <value name="ST6_SHADER" value="0"/> 678 <value name="ST6_CONSTANTS" value="1"/> 679 <value name="ST6_UBO" value="2"/> 680 <value name="ST6_IBO" value="3"/> 681 </enum> 682 <enum name="a6xx_state_src"> 683 <value name="SS6_DIRECT" value="0"/> 684 <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? --> 685 <value name="SS6_INDIRECT" value="2"/> 686 <doc> 687 SS6_UBO used by the a6xx vulkan blob with tesselation constants 688 in this case, EXT_SRC_ADDR is (ubo_id shl 16 | offset) 689 to load constants from a UBO loaded with DST_OFF = 14 and offset 0, 690 EXT_SRC_ADDR = 0xe0000 691 (offset is a guess, should be in bytes given that maxUniformBufferRange=64k) 692 </doc> 693 <value name="SS6_UBO" value="3"/> 694 </enum> 695 <reg32 offset="0" name="0"> 696 <bitfield name="DST_OFF" low="0" high="13" type="uint"/> 697 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/> 698 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/> 699 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/> 700 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 701 </reg32> 702 <reg32 offset="1" name="1"> 703 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 704 </reg32> 705 <reg32 offset="2" name="2"> 706 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/> 707 </reg32> 708 <reg64 offset="1" name="EXT_SRC_ADDR" type="address"/> 709</domain> 710 711<bitset name="vgt_draw_initiator" inline="yes"> 712 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/> 713 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/> 714 <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/> 715 <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/> 716 <bitfield name="NOT_EOP" pos="12" type="boolean"/> 717 <bitfield name="SMALL_INDEX" pos="13" type="boolean"/> 718 <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/> 719 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/> 720</bitset> 721 722<!-- changed on a4xx: --> 723<enum name="a4xx_index_size"> 724 <value name="INDEX4_SIZE_8_BIT" value="0"/> 725 <value name="INDEX4_SIZE_16_BIT" value="1"/> 726 <value name="INDEX4_SIZE_32_BIT" value="2"/> 727</enum> 728 729<enum name="a6xx_patch_type"> 730 <value name="TESS_QUADS" value="0"/> 731 <value name="TESS_TRIANGLES" value="1"/> 732 <value name="TESS_ISOLINES" value="2"/> 733</enum> 734 735<bitset name="vgt_draw_initiator_a4xx" inline="yes"> 736 <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 --> 737 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/> 738 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/> 739 <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/> 740 <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/> 741 <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/> 742 <bitfield name="GS_ENABLE" pos="16" type="boolean"/> 743 <bitfield name="TESS_ENABLE" pos="17" type="boolean"/> 744</bitset> 745 746<domain name="CP_DRAW_INDX" width="32"> 747 <reg32 offset="0" name="0"> 748 <bitfield name="VIZ_QUERY" low="0" high="31"/> 749 </reg32> 750 <reg32 offset="1" name="1" type="vgt_draw_initiator"/> 751 <reg32 offset="2" name="2"> 752 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 753 </reg32> 754 <reg32 offset="3" name="3"> 755 <bitfield name="INDX_BASE" low="0" high="31"/> 756 </reg32> 757 <reg32 offset="4" name="4"> 758 <bitfield name="INDX_SIZE" low="0" high="31"/> 759 </reg32> 760</domain> 761 762<domain name="CP_DRAW_INDX_2" width="32"> 763 <reg32 offset="0" name="0"> 764 <bitfield name="VIZ_QUERY" low="0" high="31"/> 765 </reg32> 766 <reg32 offset="1" name="1" type="vgt_draw_initiator"/> 767 <reg32 offset="2" name="2"> 768 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 769 </reg32> 770 <!-- followed by NUM_INDICES indices.. --> 771</domain> 772 773<domain name="CP_DRAW_INDX_OFFSET" width="32"> 774 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 775 <reg32 offset="1" name="1"> 776 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/> 777 </reg32> 778 <reg32 offset="2" name="2"> 779 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 780 </reg32> 781 <reg32 offset="3" name="3"> 782 <bitfield name="FIRST_INDX" low="0" high="31"/> 783 </reg32> 784 785 <stripe varset="chip" variants="A5XX-"> 786 <reg32 offset="4" name="4"> 787 <bitfield name="INDX_BASE_LO" low="0" high="31"/> 788 </reg32> 789 <reg32 offset="5" name="5"> 790 <bitfield name="INDX_BASE_HI" low="0" high="31"/> 791 </reg32> 792 <reg64 offset="4" name="INDX_BASE" type="address"/> 793 <reg32 offset="6" name="6"> 794 <!-- max # of elements in index buffer --> 795 <bitfield name="MAX_INDICES" low="0" high="31"/> 796 </reg32> 797 </stripe> 798 799 <reg32 offset="4" name="4"> 800 <bitfield name="INDX_BASE" low="0" high="31" type="address"/> 801 </reg32> 802 803 <reg32 offset="5" name="5"> 804 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/> 805 </reg32> 806</domain> 807 808<domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 809 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 810 <stripe varset="chip" variants="A4XX"> 811 <reg32 offset="1" name="1"> 812 <bitfield name="INDIRECT" low="0" high="31"/> 813 </reg32> 814 </stripe> 815 <stripe varset="chip" variants="A5XX-"> 816 <reg32 offset="1" name="1"> 817 <bitfield name="INDIRECT_LO" low="0" high="31"/> 818 </reg32> 819 <reg32 offset="2" name="2"> 820 <bitfield name="INDIRECT_HI" low="0" high="31"/> 821 </reg32> 822 <reg64 offset="1" name="INDIRECT" type="address"/> 823 </stripe> 824</domain> 825 826<domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 827 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 828 <stripe varset="chip" variants="A4XX"> 829 <reg32 offset="1" name="1"> 830 <bitfield name="INDX_BASE" low="0" high="31"/> 831 </reg32> 832 <reg32 offset="2" name="2"> 833 <!-- max # of bytes in index buffer --> 834 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/> 835 </reg32> 836 <reg32 offset="3" name="3"> 837 <bitfield name="INDIRECT" low="0" high="31"/> 838 </reg32> 839 </stripe> 840 <stripe varset="chip" variants="A5XX-"> 841 <reg32 offset="1" name="1"> 842 <bitfield name="INDX_BASE_LO" low="0" high="31"/> 843 </reg32> 844 <reg32 offset="2" name="2"> 845 <bitfield name="INDX_BASE_HI" low="0" high="31"/> 846 </reg32> 847 <reg64 offset="1" name="INDX_BASE" type="address"/> 848 <reg32 offset="3" name="3"> 849 <!-- max # of elements in index buffer --> 850 <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/> 851 </reg32> 852 <reg32 offset="4" name="4"> 853 <bitfield name="INDIRECT_LO" low="0" high="31"/> 854 </reg32> 855 <reg32 offset="5" name="5"> 856 <bitfield name="INDIRECT_HI" low="0" high="31"/> 857 </reg32> 858 <reg64 offset="4" name="INDIRECT" type="address"/> 859 </stripe> 860</domain> 861 862<domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-"> 863 <enum name="a6xx_draw_indirect_opcode"> 864 <value name="INDIRECT_OP_NORMAL" value="0x2"/> 865 <value name="INDIRECT_OP_INDEXED" value="0x4"/> 866 <value name="INDIRECT_OP_INDIRECT_COUNT" value="0x6"/> 867 <value name="INDIRECT_OP_INDIRECT_COUNT_INDEXED" value="0x7"/> 868 </enum> 869 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 870 <reg32 offset="1" name="1"> 871 <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode" addvariant="yes"/> 872 <doc> 873 DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will 874 be updated for each draw to {draw_id, first_vertex, first_instance, 0} 875 value of 0 disables it 876 </doc> 877 <bitfield name="DST_OFF" low="8" high="21" type="hex"/> 878 </reg32> 879 <reg32 offset="2" name="DRAW_COUNT" type="uint"/> 880 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_NORMAL"> 881 <reg64 offset="3" name="INDIRECT" type="address"/> 882 <reg32 offset="5" name="STRIDE" type="uint"/> 883 </stripe> 884 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDEXED" prefix="INDEXED"> 885 <reg64 offset="3" name="INDEX" type="address"/> 886 <reg32 offset="5" name="MAX_INDICES" type="uint"/> 887 <reg64 offset="6" name="INDIRECT" type="address"/> 888 <reg32 offset="8" name="STRIDE" type="uint"/> 889 </stripe> 890 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT" prefix="INDIRECT"> 891 <reg64 offset="3" name="INDIRECT" type="address"/> 892 <reg64 offset="5" name="INDIRECT_COUNT" type="address"/> 893 <reg32 offset="7" name="STRIDE" type="uint"/> 894 </stripe> 895 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT_INDEXED" prefix="INDIRECT_INDEXED"> 896 <reg64 offset="3" name="INDEX" type="address"/> 897 <reg32 offset="5" name="MAX_INDICES" type="uint"/> 898 <reg64 offset="6" name="INDIRECT" type="address"/> 899 <reg64 offset="8" name="INDIRECT_COUNT" type="address"/> 900 <reg32 offset="10" name="STRIDE" type="uint"/> 901 </stripe> 902</domain> 903 904<domain name="CP_DRAW_PRED_ENABLE_GLOBAL" width="32" varset="chip"> 905 <reg32 offset="0" name="0"> 906 <bitfield name="ENABLE" pos="0" type="boolean"/> 907 </reg32> 908</domain> 909 910<domain name="CP_DRAW_PRED_ENABLE_LOCAL" width="32" varset="chip"> 911 <reg32 offset="0" name="0"> 912 <bitfield name="ENABLE" pos="0" type="boolean"/> 913 </reg32> 914</domain> 915 916<domain name="CP_DRAW_PRED_SET" width="32" varset="chip"> 917 <enum name="cp_draw_pred_src"> 918 <!-- 919 Sources 1-4 seem to be about combining reading 920 SO/primitive queries and setting the predicate, which is 921 a DX11-specific optimization (since in DX11 you can only 922 predicate on the result of queries). 923 --> 924 <value name="PRED_SRC_MEM" value="5"> 925 <doc> 926 Read a 64-bit value at the given address and 927 test if it equals/doesn't equal 0. 928 </doc> 929 </value> 930 </enum> 931 <enum name="cp_draw_pred_test"> 932 <value name="NE_0_PASS" value="0"/> 933 <value name="EQ_0_PASS" value="1"/> 934 </enum> 935 <reg32 offset="0" name="0"> 936 <bitfield name="SRC" low="4" high="7" type="cp_draw_pred_src"/> 937 <bitfield name="TEST" pos="8" type="cp_draw_pred_test"/> 938 </reg32> 939 <reg64 offset="1" name="MEM_ADDR" type="address"/> 940</domain> 941 942<domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-"> 943 <array offset="0" stride="3" length="100"> 944 <reg32 offset="0" name="0"> 945 <bitfield name="COUNT" low="0" high="15" type="uint"/> 946 <bitfield name="DIRTY" pos="16" type="boolean"/> 947 <bitfield name="DISABLE" pos="17" type="boolean"/> 948 <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/> 949 <bitfield name="LOAD_IMMED" pos="19" type="boolean"/> 950 <bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/> 951 <bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/> 952 <bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/> 953 <bitfield name="GROUP_ID" low="24" high="28" type="uint"/> 954 </reg32> 955 <reg32 offset="1" name="1"> 956 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/> 957 </reg32> 958 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 959 <bitfield name="ADDR_HI" low="0" high="31" type="hex"/> 960 </reg32> 961 </array> 962</domain> 963 964<domain name="CP_SET_BIN" width="32"> 965 <doc>value at offset 0 always seems to be 0x00000000..</doc> 966 <reg32 offset="0" name="0"/> 967 <reg32 offset="1" name="1"> 968 <bitfield name="X1" low="0" high="15" type="uint"/> 969 <bitfield name="Y1" low="16" high="31" type="uint"/> 970 </reg32> 971 <reg32 offset="2" name="2"> 972 <bitfield name="X2" low="0" high="15" type="uint"/> 973 <bitfield name="Y2" low="16" high="31" type="uint"/> 974 </reg32> 975</domain> 976 977<domain name="CP_SET_BIN_DATA" width="32"> 978 <reg32 offset="0" name="0"> 979 <!-- corresponds to VSC_PIPE[n].DATA_ADDR --> 980 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/> 981 </reg32> 982 <reg32 offset="1" name="1"> 983 <!-- seesm to correspond to VSC_SIZE_ADDRESS --> 984 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/> 985 </reg32> 986</domain> 987 988<domain name="CP_SET_BIN_DATA5" width="32"> 989 <reg32 offset="0" name="0"> 990 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> 991 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 992 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> 993 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 994 </reg32> 995 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 996 <reg32 offset="1" name="1"> 997 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> 998 </reg32> 999 <reg32 offset="2" name="2"> 1000 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> 1001 </reg32> 1002 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1003 <reg32 offset="3" name="3"> 1004 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> 1005 </reg32> 1006 <reg32 offset="4" name="4"> 1007 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> 1008 </reg32> 1009 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1010 <reg32 offset="5" name="5"> 1011 <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> 1012 </reg32> 1013 <reg32 offset="6" name="6"> 1014 <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> 1015 </reg32> 1016</domain> 1017 1018<domain name="CP_SET_BIN_DATA5_OFFSET" width="32"> 1019 <doc> 1020 Like CP_SET_BIN_DATA5, but set the pointers as offsets from the 1021 pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful 1022 for Vulkan where these values aren't known when the command 1023 stream is recorded. 1024 </doc> 1025 <reg32 offset="0" name="0"> 1026 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> 1027 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 1028 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> 1029 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 1030 </reg32> 1031 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1032 <reg32 offset="1" name="1"> 1033 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> 1034 </reg32> 1035 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1036 <reg32 offset="2" name="2"> 1037 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> 1038 </reg32> 1039 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> 1040 <reg32 offset="3" name="3"> 1041 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> 1042 </reg32> 1043</domain> 1044 1045<domain name="CP_REG_RMW" width="32"> 1046 <doc> 1047 Modifies DST_REG using two sources that can either be registers 1048 or immediates. If SRC1_ADD is set, then do the following: 1049 1050 $dst = (($dst & $src0) rot $rotate) + $src1 1051 1052 Otherwise: 1053 1054 $dst = (($dst & $src0) rot $rotate) | $src1 1055 1056 Here "rot" means rotate left. 1057 </doc> 1058 <reg32 offset="0" name="0"> 1059 <bitfield name="DST_REG" low="0" high="17" type="hex"/> 1060 <bitfield name="ROTATE" low="24" high="28" type="uint"/> 1061 <bitfield name="SRC1_ADD" pos="29" type="boolean"/> 1062 <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/> 1063 <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/> 1064 </reg32> 1065 <reg32 offset="1" name="1"> 1066 <bitfield name="SRC0" low="0" high="31" type="uint"/> 1067 </reg32> 1068 <reg32 offset="2" name="2"> 1069 <bitfield name="SRC1" low="0" high="31" type="uint"/> 1070 </reg32> 1071</domain> 1072 1073<domain name="CP_REG_TO_MEM" width="32"> 1074 <reg32 offset="0" name="0"> 1075 <bitfield name="REG" low="0" high="17" type="hex"/> 1076 <!-- number of registers/dwords copied is max(CNT, 1). --> 1077 <bitfield name="CNT" low="18" high="29" type="uint"/> 1078 <bitfield name="64B" pos="30" type="boolean"/> 1079 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1080 </reg32> 1081 <reg32 offset="1" name="1"> 1082 <bitfield name="DEST" low="0" high="31"/> 1083 </reg32> 1084 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1085 <bitfield name="DEST_HI" low="0" high="31"/> 1086 </reg32> 1087</domain> 1088 1089<domain name="CP_REG_TO_MEM_OFFSET_REG" width="32"> 1090 <doc> 1091 Like CP_REG_TO_MEM, but the memory address to write to can be 1092 offsetted using either one or two registers or scratch 1093 registers. 1094 </doc> 1095 <reg32 offset="0" name="0"> 1096 <bitfield name="REG" low="0" high="17" type="hex"/> 1097 <!-- number of registers/dwords copied is max(CNT, 1). --> 1098 <bitfield name="CNT" low="18" high="29" type="uint"/> 1099 <bitfield name="64B" pos="30" type="boolean"/> 1100 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1101 </reg32> 1102 <reg32 offset="1" name="1"> 1103 <bitfield name="DEST" low="0" high="31"/> 1104 </reg32> 1105 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1106 <bitfield name="DEST_HI" low="0" high="31"/> 1107 </reg32> 1108 <reg32 offset="3" name="3"> 1109 <bitfield name="OFFSET0" low="0" high="17" type="hex"/> 1110 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/> 1111 </reg32> 1112 <!-- followed by an optional identical OFFSET1 dword --> 1113</domain> 1114 1115<domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32"> 1116 <doc> 1117 Like CP_REG_TO_MEM, but the memory address to write to can be 1118 offsetted using a DWORD in memory. 1119 </doc> 1120 <reg32 offset="0" name="0"> 1121 <bitfield name="REG" low="0" high="17" type="hex"/> 1122 <!-- number of registers/dwords copied is max(CNT, 1). --> 1123 <bitfield name="CNT" low="18" high="29" type="uint"/> 1124 <bitfield name="64B" pos="30" type="boolean"/> 1125 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1126 </reg32> 1127 <reg32 offset="1" name="1"> 1128 <bitfield name="DEST" low="0" high="31"/> 1129 </reg32> 1130 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1131 <bitfield name="DEST_HI" low="0" high="31"/> 1132 </reg32> 1133 <reg32 offset="3" name="3"> 1134 <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/> 1135 </reg32> 1136 <reg32 offset="4" name="4"> 1137 <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/> 1138 </reg32> 1139</domain> 1140 1141<domain name="CP_MEM_TO_REG" width="32"> 1142 <reg32 offset="0" name="0"> 1143 <bitfield name="REG" low="0" high="17" type="hex"/> 1144 <!-- number of registers/dwords copied is max(CNT, 1). --> 1145 <bitfield name="CNT" low="19" high="29" type="uint"/> 1146 <!-- shift each DWORD left by 2 while copying --> 1147 <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/> 1148 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 --> 1149 <bitfield name="UNK31" pos="31" type="boolean"/> 1150 </reg32> 1151 <reg32 offset="1" name="1"> 1152 <bitfield name="SRC" low="0" high="31"/> 1153 </reg32> 1154 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1155 <bitfield name="SRC_HI" low="0" high="31"/> 1156 </reg32> 1157</domain> 1158 1159<domain name="CP_MEM_TO_MEM" width="32"> 1160 <reg32 offset="0" name="0"> 1161 <!-- 1162 not sure how many src operands we have, but the low 1163 bits negate the n'th src argument. 1164 --> 1165 <bitfield name="NEG_A" pos="0" type="boolean"/> 1166 <bitfield name="NEG_B" pos="1" type="boolean"/> 1167 <bitfield name="NEG_C" pos="2" type="boolean"/> 1168 1169 <!-- if set treat src/dst as 64bit values --> 1170 <bitfield name="DOUBLE" pos="29" type="boolean"/> 1171 <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand --> 1172 <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/> 1173 <!-- some other kind of wait --> 1174 <bitfield name="UNK31" pos="31" type="boolean"/> 1175 </reg32> 1176 <!-- 1177 followed by sequence of addresses.. the first is the 1178 destination and the rest are N src addresses which are 1179 summed (after being negated if NEG_x bit set) allowing 1180 to do things like 'result += end - start' (which turns 1181 out to be useful for queries and accumulating results 1182 across multiple tiles) 1183 --> 1184</domain> 1185 1186<domain name="CP_MEMCPY" width="32"> 1187 <reg32 offset="0" name="0"> 1188 <bitfield name="DWORDS" low="0" high="31" type="uint"/> 1189 </reg32> 1190 <reg32 offset="1" name="1"> 1191 <bitfield name="SRC_LO" low="0" high="31" type="hex"/> 1192 </reg32> 1193 <reg32 offset="2" name="2"> 1194 <bitfield name="SRC_HI" low="0" high="31" type="hex"/> 1195 </reg32> 1196 <reg32 offset="3" name="3"> 1197 <bitfield name="DST_LO" low="0" high="31" type="hex"/> 1198 </reg32> 1199 <reg32 offset="4" name="4"> 1200 <bitfield name="DST_HI" low="0" high="31" type="hex"/> 1201 </reg32> 1202</domain> 1203 1204<domain name="CP_REG_TO_SCRATCH" width="32"> 1205 <reg32 offset="0" name="0"> 1206 <bitfield name="REG" low="0" high="17" type="hex"/> 1207 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1208 <!-- number of registers/dwords copied is CNT + 1. --> 1209 <bitfield name="CNT" low="24" high="26" type="uint"/> 1210 </reg32> 1211</domain> 1212 1213<domain name="CP_SCRATCH_TO_REG" width="32"> 1214 <reg32 offset="0" name="0"> 1215 <bitfield name="REG" low="0" high="17" type="hex"/> 1216 <!-- note: CP_MEM_TO_REG always sets this when writing to the register --> 1217 <bitfield name="UNK18" pos="18" type="boolean"/> 1218 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1219 <!-- number of registers/dwords copied is CNT + 1. --> 1220 <bitfield name="CNT" low="24" high="26" type="uint"/> 1221 </reg32> 1222</domain> 1223 1224<domain name="CP_SCRATCH_WRITE" width="32"> 1225 <reg32 offset="0" name="0"> 1226 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1227 </reg32> 1228 <!-- followed by one or more DWORDs to write to scratch registers --> 1229</domain> 1230 1231<domain name="CP_MEM_WRITE" width="32"> 1232 <reg32 offset="0" name="0"> 1233 <bitfield name="ADDR_LO" low="0" high="31"/> 1234 </reg32> 1235 <reg32 offset="1" name="1"> 1236 <bitfield name="ADDR_HI" low="0" high="31"/> 1237 </reg32> 1238 <!-- followed by the DWORDs to write --> 1239</domain> 1240 1241<enum name="cp_cond_function"> 1242 <value value="0" name="WRITE_ALWAYS"/> 1243 <value value="1" name="WRITE_LT"/> 1244 <value value="2" name="WRITE_LE"/> 1245 <value value="3" name="WRITE_EQ"/> 1246 <value value="4" name="WRITE_NE"/> 1247 <value value="5" name="WRITE_GE"/> 1248 <value value="6" name="WRITE_GT"/> 1249</enum> 1250 1251<domain name="CP_COND_WRITE" width="32"> 1252 <reg32 offset="0" name="0"> 1253 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1254 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> 1255 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1256 </reg32> 1257 <reg32 offset="1" name="1"> 1258 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/> 1259 </reg32> 1260 <reg32 offset="2" name="2"> 1261 <bitfield name="REF" low="0" high="31"/> 1262 </reg32> 1263 <reg32 offset="3" name="3"> 1264 <bitfield name="MASK" low="0" high="31"/> 1265 </reg32> 1266 <reg32 offset="4" name="4"> 1267 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/> 1268 </reg32> 1269 <reg32 offset="5" name="5"> 1270 <bitfield name="WRITE_DATA" low="0" high="31"/> 1271 </reg32> 1272</domain> 1273 1274<domain name="CP_COND_WRITE5" width="32"> 1275 <reg32 offset="0" name="0"> 1276 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1277 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/> 1278 <!-- if both POLL_MEMORY and POLL_SCRATCH are false, it polls a register at POLL_ADDR_LO instead. --> 1279 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> 1280 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/> 1281 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1282 </reg32> 1283 <reg32 offset="1" name="1"> 1284 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1285 </reg32> 1286 <reg32 offset="2" name="2"> 1287 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1288 </reg32> 1289 <reg32 offset="3" name="3"> 1290 <bitfield name="REF" low="0" high="31"/> 1291 </reg32> 1292 <reg32 offset="4" name="4"> 1293 <bitfield name="MASK" low="0" high="31"/> 1294 </reg32> 1295 <reg32 offset="5" name="5"> 1296 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/> 1297 </reg32> 1298 <reg32 offset="6" name="6"> 1299 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/> 1300 </reg32> 1301 <reg32 offset="7" name="7"> 1302 <bitfield name="WRITE_DATA" low="0" high="31"/> 1303 </reg32> 1304</domain> 1305 1306<domain name="CP_WAIT_MEM_GTE" width="32"> 1307 <doc> 1308 Wait until a memory value is greater than or equal to the 1309 reference, using signed comparison. 1310 </doc> 1311 <reg32 offset="0" name="0"> 1312 <!-- Reserved for flags, presumably? Unused in FW --> 1313 <bitfield name="RESERVED" low="0" high="31" type="hex"/> 1314 </reg32> 1315 <reg32 offset="1" name="1"> 1316 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1317 </reg32> 1318 <reg32 offset="2" name="2"> 1319 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1320 </reg32> 1321 <reg32 offset="3" name="3"> 1322 <bitfield name="REF" low="0" high="31"/> 1323 </reg32> 1324</domain> 1325 1326<domain name="CP_WAIT_REG_MEM" width="32"> 1327 <doc> 1328 This uses the same internal comparison as CP_COND_WRITE, 1329 but waits until the comparison is true instead. It busy-loops in 1330 the CP for the given number of cycles before trying again. 1331 </doc> 1332 <reg32 offset="0" name="0"> 1333 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1334 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/> 1335 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> 1336 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/> 1337 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1338 </reg32> 1339 <reg32 offset="1" name="1"> 1340 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1341 </reg32> 1342 <reg32 offset="2" name="2"> 1343 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1344 </reg32> 1345 <reg32 offset="3" name="3"> 1346 <bitfield name="REF" low="0" high="31"/> 1347 </reg32> 1348 <reg32 offset="4" name="4"> 1349 <bitfield name="MASK" low="0" high="31"/> 1350 </reg32> 1351 <reg32 offset="5" name="5"> 1352 <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/> 1353 </reg32> 1354</domain> 1355 1356<domain name="CP_WAIT_TWO_REGS" width="32"> 1357 <doc> 1358 Waits for REG0 to not be 0 or REG1 to not equal REF 1359 </doc> 1360 <reg32 offset="0" name="0"> 1361 <bitfield name="REG0" low="0" high="17" type="hex"/> 1362 </reg32> 1363 <reg32 offset="1" name="1"> 1364 <bitfield name="REG1" low="0" high="17" type="hex"/> 1365 </reg32> 1366 <reg32 offset="2" name="2"> 1367 <bitfield name="REF" low="0" high="31" type="uint"/> 1368 </reg32> 1369</domain> 1370 1371<domain name="CP_DISPATCH_COMPUTE" width="32"> 1372 <reg32 offset="0" name="0"/> 1373 <reg32 offset="1" name="1"> 1374 <bitfield name="X" low="0" high="31"/> 1375 </reg32> 1376 <reg32 offset="2" name="2"> 1377 <bitfield name="Y" low="0" high="31"/> 1378 </reg32> 1379 <reg32 offset="3" name="3"> 1380 <bitfield name="Z" low="0" high="31"/> 1381 </reg32> 1382</domain> 1383 1384<domain name="CP_SET_RENDER_MODE" width="32"> 1385 <enum name="render_mode_cmd"> 1386 <value value="1" name="BYPASS"/> 1387 <value value="2" name="BINNING"/> 1388 <value value="3" name="GMEM"/> 1389 <value value="5" name="BLIT2D"/> 1390 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? --> 1391 <value value="7" name="BLIT2DSCALE"/> 1392 <!-- 8 set before going back to BYPASS exiting 2D --> 1393 <value value="8" name="END2D"/> 1394 </enum> 1395 <reg32 offset="0" name="0"> 1396 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/> 1397 <!-- 1398 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in 1399 0x21xx range.. possibly (at least some) a5xx variants have a 1400 2d core? 1401 --> 1402 </reg32> 1403 <!-- I think first buffer is for GPU to save context in case of ctx switch? --> 1404 <reg32 offset="1" name="1"> 1405 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1406 </reg32> 1407 <reg32 offset="2" name="2"> 1408 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1409 </reg32> 1410 <reg32 offset="3" name="3"> 1411 <!-- 1412 set when in GMEM.. maybe indicates GMEM contents need to be 1413 preserved on ctx switch? 1414 --> 1415 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/> 1416 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/> 1417 </reg32> 1418 <reg32 offset="4" name="4"/> 1419 <!-- second buffer looks like some cmdstream.. length in dwords: --> 1420 <reg32 offset="5" name="5"> 1421 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/> 1422 </reg32> 1423 <reg32 offset="6" name="6"> 1424 <bitfield name="ADDR_1_LO" low="0" high="31"/> 1425 </reg32> 1426 <reg32 offset="7" name="7"> 1427 <bitfield name="ADDR_1_HI" low="0" high="31"/> 1428 </reg32> 1429</domain> 1430 1431<!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword --> 1432<domain name="CP_COMPUTE_CHECKPOINT" width="32"> 1433 <!-- I think first buffer is for GPU to save context in case of ctx switch? --> 1434 <reg32 offset="0" name="0"> 1435 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1436 </reg32> 1437 <reg32 offset="1" name="1"> 1438 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1439 </reg32> 1440 <reg32 offset="2" name="2"> 1441 </reg32> 1442 <!-- second buffer looks like some cmdstream.. length in dwords: --> 1443 <reg32 offset="3" name="3"> 1444 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/> 1445 </reg32> 1446 <reg32 offset="4" name="4"/> 1447 <reg32 offset="5" name="5"> 1448 <bitfield name="ADDR_1_LO" low="0" high="31"/> 1449 </reg32> 1450 <reg32 offset="6" name="6"> 1451 <bitfield name="ADDR_1_HI" low="0" high="31"/> 1452 </reg32> 1453 <reg32 offset="7" name="7"/> 1454</domain> 1455 1456<domain name="CP_PERFCOUNTER_ACTION" width="32"> 1457 <reg32 offset="0" name="0"> 1458 </reg32> 1459 <reg32 offset="1" name="1"> 1460 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1461 </reg32> 1462 <reg32 offset="2" name="2"> 1463 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1464 </reg32> 1465</domain> 1466 1467<domain name="CP_EVENT_WRITE" width="32"> 1468 <reg32 offset="0" name="0"> 1469 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/> 1470 <!-- when set, write back timestamp instead of value from packet: --> 1471 <bitfield name="TIMESTAMP" pos="30" type="boolean"/> 1472 <bitfield name="IRQ" pos="31" type="boolean"/> 1473 </reg32> 1474 <!-- 1475 TODO what is gpuaddr for, seems to be all 0's.. maybe needed for 1476 context switch? 1477 --> 1478 <reg32 offset="1" name="1"> 1479 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1480 </reg32> 1481 <reg32 offset="2" name="2"> 1482 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1483 </reg32> 1484 <reg32 offset="3" name="3"> 1485 <!-- ??? --> 1486 </reg32> 1487</domain> 1488 1489<domain name="CP_BLIT" width="32"> 1490 <enum name="cp_blit_cmd"> 1491 <value value="0" name="BLIT_OP_FILL"/> 1492 <value value="1" name="BLIT_OP_COPY"/> 1493 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation --> 1494 </enum> 1495 <reg32 offset="0" name="0"> 1496 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/> 1497 </reg32> 1498 <reg32 offset="1" name="1"> 1499 <bitfield name="SRC_X1" low="0" high="13" type="uint"/> 1500 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/> 1501 </reg32> 1502 <reg32 offset="2" name="2"> 1503 <bitfield name="SRC_X2" low="0" high="13" type="uint"/> 1504 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/> 1505 </reg32> 1506 <reg32 offset="3" name="3"> 1507 <bitfield name="DST_X1" low="0" high="13" type="uint"/> 1508 <bitfield name="DST_Y1" low="16" high="29" type="uint"/> 1509 </reg32> 1510 <reg32 offset="4" name="4"> 1511 <bitfield name="DST_X2" low="0" high="13" type="uint"/> 1512 <bitfield name="DST_Y2" low="16" high="29" type="uint"/> 1513 </reg32> 1514</domain> 1515 1516<domain name="CP_EXEC_CS" width="32"> 1517 <reg32 offset="0" name="0"> 1518 </reg32> 1519 <reg32 offset="1" name="1"> 1520 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/> 1521 </reg32> 1522 <reg32 offset="2" name="2"> 1523 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/> 1524 </reg32> 1525 <reg32 offset="3" name="3"> 1526 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/> 1527 </reg32> 1528</domain> 1529 1530<domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 1531 <reg32 offset="0" name="0"> 1532 </reg32> 1533 <stripe varset="chip" variants="A4XX"> 1534 <reg32 offset="1" name="1"> 1535 <bitfield name="ADDR" low="0" high="31"/> 1536 </reg32> 1537 <reg32 offset="2" name="2"> 1538 <!-- localsize is value minus one: --> 1539 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 1540 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 1541 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 1542 </reg32> 1543 </stripe> 1544 <stripe varset="chip" variants="A5XX-"> 1545 <reg32 offset="1" name="1"> 1546 <bitfield name="ADDR_LO" low="0" high="31"/> 1547 </reg32> 1548 <reg32 offset="2" name="2"> 1549 <bitfield name="ADDR_HI" low="0" high="31"/> 1550 </reg32> 1551 <reg32 offset="3" name="3"> 1552 <!-- localsize is value minus one: --> 1553 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 1554 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 1555 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 1556 </reg32> 1557 </stripe> 1558</domain> 1559 1560<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1561 <doc>Tell CP the current operation mode, indicates save and restore procedure</doc> 1562 <enum name="a6xx_marker"> 1563 <value value="1" name="RM6_BYPASS"/> 1564 <value value="2" name="RM6_BINNING"/> 1565 <value value="4" name="RM6_GMEM"/> 1566 <value value="5" name="RM6_ENDVIS"/> 1567 <value value="6" name="RM6_RESOLVE"/> 1568 <value value="7" name="RM6_YIELD"/> 1569 <value value="8" name="RM6_COMPUTE"/> 1570 <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) --> 1571 1572 <!-- 1573 These values come from a6xx_set_marker() in the 1574 downstream kernel, and they can only be set by the kernel 1575 --> 1576 <value value="0xd" name="RM6_IB1LIST_START"/> 1577 <value value="0xe" name="RM6_IB1LIST_END"/> 1578 <!-- IFPC - inter-frame power collapse --> 1579 <value value="0x100" name="RM6_IFPC_ENABLE"/> 1580 <value value="0x101" name="RM6_IFPC_DISABLE"/> 1581 </enum> 1582 <reg32 offset="0" name="0"> 1583 <!-- 1584 NOTE: blob driver and some versions of freedreno/turnip set 1585 b4, which is unused (at least by current sqe fw), but interferes 1586 with parsing if we extend the size of the bitfield to include 1587 b8 (only sent by kernel mode driver). Really, the way the 1588 parsing works in the firmware, only b0-b3 are considered, but 1589 if b8 is set, the low bits are interpreted differently. To 1590 model this, without getting confused by spurious b4, this is 1591 described as two overlapping bitfields: 1592 --> 1593 <bitfield name="MODE" low="0" high="8" type="a6xx_marker"/> 1594 <bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/> 1595 </reg32> 1596</domain> 1597 1598<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1599 <doc>Set internal CP registers, used to indicate context save data addresses</doc> 1600 <enum name="pseudo_reg"> 1601 <value value="0" name="SMMU_INFO"/> 1602 <value value="1" name="NON_SECURE_SAVE_ADDR"/> 1603 <value value="2" name="SECURE_SAVE_ADDR"/> 1604 <value value="3" name="NON_PRIV_SAVE_ADDR"/> 1605 <value value="4" name="COUNTER"/> 1606 </enum> 1607 <array offset="0" stride="3" length="100"> 1608 <reg32 offset="0" name="0"> 1609 <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/> 1610 </reg32> 1611 <reg32 offset="1" name="1"> 1612 <bitfield name="LO" low="0" high="31"/> 1613 </reg32> 1614 <reg32 offset="2" name="2"> 1615 <bitfield name="HI" low="0" high="31"/> 1616 </reg32> 1617 </array> 1618</domain> 1619 1620<domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1621 <doc> 1622 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC. 1623 So: 1624 1625 opcode: CP_REG_TEST (39) (2 dwords) 1626 { REG = 0xc10 | BIT = 0 } 1627 0000: 70b90001 00000c10 1628 opcode: CP_COND_REG_EXEC (47) (3 dwords) 1629 0000: 70c70002 10000000 00000004 1630 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) 1631 1632 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at 1633 offset 0x0c10 is 1 1634 </doc> 1635 <reg32 offset="0" name="0"> 1636 <!-- the register to test --> 1637 <bitfield name="REG" low="0" high="17"/> 1638 <!-- the bit to test --> 1639 <bitfield name="BIT" low="20" high="24" type="uint"/> 1640 <!-- execute CP_WAIT_FOR_ME beforehand --> 1641 <bitfield name="WAIT_FOR_ME" pos="25" type="boolean"/> 1642 <!-- 1643 Appears only in: 1644 opcode: CP_REG_TEST (39) (4 dwords) 1645 { REG = 0 | BIT = 0 | WAIT_FOR_ME | UNK31 } 1646 Seem to force CP_REG_TEST to write false 1647 --> 1648 <bitfield name="UNK31" pos="31" type="boolean"/> 1649 </reg32> 1650</domain> 1651 1652<!-- I *think* this existed at least as far back as a4xx --> 1653<domain name="CP_COND_REG_EXEC" width="32"> 1654 <enum name="compare_mode"> 1655 <!-- use the predicate bit set by CP_REG_TEST --> 1656 <value value="1" name="PRED_TEST"/> 1657 <!-- compare two registers directly for equality --> 1658 <value value="2" name="REG_COMPARE"/> 1659 <!-- test if certain render modes are set via CP_SET_MARKER --> 1660 <value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/> 1661 </enum> 1662 <reg32 offset="0" name="0"> 1663 <bitfield name="REG0" low="0" high="17" type="hex"/> 1664 1665 <!-- 1666 Blob uses them for vkCmdClearAttachments in gmem mode. Examples: 1667 opcode: CP_COND_REG_EXEC (47) (3 dwords) 1668 { REG0 = 0 | MODE = PRED_TEST | 0x140000 } 1669 opcode: CP_COND_REG_EXEC (47) (3 dwords) 1670 { REG0 = 0 | MODE = PRED_TEST | 0x100000 } 1671 --> 1672 <bitfield name="UNK18" pos="18" varset="chip" variants="A6XX-" type="boolean"/> 1673 <bitfield name="UNK20" pos="20" varset="chip" variants="A6XX-" type="boolean"/> 1674 1675 <!-- 1676 Note: these bits have the same meaning, and use the same 1677 internal mechanism as the bits in CP_SET_DRAW_STATE. 1678 When RENDER_MODE is selected, they're used as 1679 a bitmask of which modes pass the test. 1680 --> 1681 1682 <!-- RM6_BINNING --> 1683 <bitfield name="BINNING" pos="25" varset="chip" variants="A6XX-" type="boolean"/> 1684 <!-- all others --> 1685 <bitfield name="GMEM" pos="26" varset="chip" variants="A6XX-" type="boolean"/> 1686 <!-- RM6_BYPASS --> 1687 <bitfield name="SYSMEM" pos="27" varset="chip" variants="A6XX-" type="boolean"/> 1688 1689 <bitfield name="MODE" low="28" high="31" type="compare_mode"/> 1690 </reg32> 1691 1692 <!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 --> 1693 1694 <reg32 offset="1" name="1"> 1695 <bitfield name="DWORDS" low="0" high="31" type="uint"/> 1696 </reg32> 1697</domain> 1698 1699<domain name="CP_COND_EXEC" width="32"> 1700 <doc> 1701 Executes the following DWORDs of commands if the dword at ADDR0 1702 is not equal to 0 and the dword at ADDR1 is less than REF 1703 (signed comparison). 1704 </doc> 1705 <reg32 offset="0" name="0"> 1706 <bitfield name="ADDR0_LO" low="0" high="31"/> 1707 </reg32> 1708 <reg32 offset="1" name="1"> 1709 <bitfield name="ADDR0_HI" low="0" high="31"/> 1710 </reg32> 1711 <reg32 offset="2" name="2"> 1712 <bitfield name="ADDR1_LO" low="0" high="31"/> 1713 </reg32> 1714 <reg32 offset="3" name="3"> 1715 <bitfield name="ADDR1_HI" low="0" high="31"/> 1716 </reg32> 1717 <reg32 offset="4" name="4"> 1718 <bitfield name="REF" low="0" high="31"/> 1719 </reg32> 1720 <reg32 offset="5" name="5"> 1721 <bitfield name="DWORDS" low="0" high="31" type="uint"/> 1722 </reg32> 1723</domain> 1724 1725<domain name="CP_SET_CTXSWITCH_IB" width="32"> 1726 <doc> 1727 Used by the userspace driver to set various IB's which are 1728 executed during context save/restore for handling 1729 state that isn't restored by the 1730 context switch routine itself. 1731 </doc> 1732 <enum name="ctxswitch_ib"> 1733 <value name="RESTORE_IB" value="0"> 1734 <doc>Executed unconditionally when switching back to the context.</doc> 1735 </value> 1736 <value name="YIELD_RESTORE_IB" value="1"> 1737 <doc> 1738 Executed when switching back after switching 1739 away during execution of 1740 a CP_SET_MARKER packet with RM6_YIELD as the 1741 payload *and* the normal save routine was 1742 bypassed for a shorter one. I think this is 1743 connected to the "skipsaverestore" bit set by 1744 the kernel when preempting. 1745 </doc> 1746 </value> 1747 <value name="SAVE_IB" value="2"> 1748 <doc> 1749 Executed when switching away from the context, 1750 except for context switches initiated via 1751 CP_YIELD. 1752 </doc> 1753 </value> 1754 <value name="RB_SAVE_IB" value="3"> 1755 <doc> 1756 This can only be set by the RB (i.e. the kernel) 1757 and executes with protected mode off, but 1758 is otherwise similar to SAVE_IB. 1759 1760 Note, kgsl calls this CP_KMD_AMBLE_TYPE 1761 </doc> 1762 </value> 1763 </enum> 1764 <reg32 offset="0" name="0"> 1765 <bitfield name="ADDR_LO" low="0" high="31"/> 1766 </reg32> 1767 <reg32 offset="1" name="1"> 1768 <bitfield name="ADDR_HI" low="0" high="31"/> 1769 </reg32> 1770 <reg32 offset="2" name="2"> 1771 <bitfield name="DWORDS" low="0" high="19" type="uint"/> 1772 <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/> 1773 </reg32> 1774</domain> 1775 1776<domain name="CP_REG_WRITE" width="32"> 1777 <enum name="reg_tracker"> 1778 <doc> 1779 Keep shadow copies of these registers and only set them 1780 when drawing, avoiding redundant writes: 1781 - VPC_CNTL_0 1782 - HLSQ_CONTROL_1_REG 1783 - HLSQ_UNKNOWN_B980 1784 </doc> 1785 <value name="TRACK_CNTL_REG" value="0x1"/> 1786 <doc> 1787 Track RB_RENDER_CNTL, and insert a WFI in the following 1788 situation: 1789 - There is a write that disables binning 1790 - There was a draw with binning left enabled, but in 1791 BYPASS mode 1792 Presumably this is a hang workaround? 1793 </doc> 1794 <value name="TRACK_RENDER_CNTL" value="0x2"/> 1795 <doc> 1796 Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of 1797 the data to write is 0. Used by the Vulkan blob with 1798 PC_MULTIVIEW_CNTL, but this isn't predicated on particular 1799 register(s) like the others. 1800 </doc> 1801 <value name="UNK_EVENT_WRITE" value="0x4"/> 1802 <doc> 1803 Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and 1804 GRAS_LRZ_DEPTH_VIEW with previous values, and if one of 1805 the following is true: 1806 - GRAS_LRZ_CNTL::GREATER has changed 1807 - GRAS_LRZ_CNTL::DIR has changed, the old value is not 1808 CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED 1809 - GRAS_LRZ_DEPTH_VIEW has changed 1810 then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE 1811 forced to 1. 1812 Only exists in a650_sqe.fw. 1813 </doc> 1814 <value name="TRACK_LRZ" value="0x8"/> 1815 </enum> 1816 <reg32 offset="0" name="0"> 1817 <bitfield name="TRACKER" low="0" high="3" type="reg_tracker"/> 1818 </reg32> 1819</domain> 1820 1821<domain name="CP_SMMU_TABLE_UPDATE" width="32"> 1822 <doc> 1823 Note that the SMMU's definition of TTBRn can take different forms 1824 depending on the pgtable format. But a5xx+ only uses aarch64 1825 format. 1826 </doc> 1827 <reg32 offset="0" name="0"> 1828 <bitfield name="TTBR0_LO" low="0" high="31"/> 1829 </reg32> 1830 <reg32 offset="1" name="1"> 1831 <bitfield name="TTBR0_HI" low="0" high="15"/> 1832 <bitfield name="ASID" low="16" high="31"/> 1833 </reg32> 1834 <reg32 offset="2" name="2"> 1835 <doc>Unused, does not apply to aarch64 pgtable format</doc> 1836 <bitfield name="CONTEXTIDR" low="0" high="31"/> 1837 </reg32> 1838 <reg32 offset="3" name="3"> 1839 <bitfield name="CONTEXTBANK" low="0" high="31"/> 1840 </reg32> 1841</domain> 1842 1843<domain name="CP_START_BIN" width="32"> 1844 <reg32 offset="0" name="BIN_COUNT" type="uint"/> 1845 <reg64 offset="1" name="PREFIX_ADDR" type="address"/> 1846 <reg32 offset="3" name="PREFIX_DWORDS"> 1847 <doc> 1848 Size of prefix for each bin. For each bin index i, the 1849 prefix commands at PREFIX_ADDR + i * PREFIX_DWORDS are 1850 executed in an IB2 before the IB1 commands following 1851 this packet. 1852 </doc> 1853 </reg32> 1854 <reg32 offset="4" name="BODY_DWORDS"> 1855 <doc>Number of dwords after this packet until CP_END_BIN</doc> 1856 </reg32> 1857</domain> 1858 1859<domain name="CP_THREAD_CONTROL" width="32"> 1860 <enum name="cp_thread"> 1861 <value name="CP_SET_THREAD_BR" value="1"/> 1862 <value name="CP_SET_THREAD_BV" value="2"/> 1863 <value name="CP_SET_THREAD_BOTH" value="3"/> 1864 </enum> 1865 <reg32 offset="0" name="0"> 1866 <bitfield low="0" high="1" name="THREAD" type="cp_thread"/> 1867 <bitfield pos="27" name="CONCURRENT_BIN_DISABLE" type="boolean"/> 1868 <bitfield pos="31" name="SYNC_THREADS" type="boolean"/> 1869 </reg32> 1870</domain> 1871 1872</database> 1873 1874