1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE 23 * 24 ***********************************************************************************************************************/ 25 26 #if !defined (__GFX9_GB_REG_H__) 27 #define __GFX9_GB_REG_H__ 28 29 /* 30 * gfx9_gb_reg.h 31 * 32 * Register Spec Release: 1.0 33 * 34 */ 35 36 // 37 // Make sure the necessary endian defines are there. 38 // 39 #if defined(LITTLEENDIAN_CPU) 40 #elif defined(BIGENDIAN_CPU) 41 #else 42 #error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" 43 #endif 44 45 union GB_ADDR_CONFIG_GFX9 { 46 struct { 47 #if defined(LITTLEENDIAN_CPU) 48 unsigned int NUM_PIPES : 3; 49 unsigned int PIPE_INTERLEAVE_SIZE : 3; 50 unsigned int MAX_COMPRESSED_FRAGS : 2; 51 unsigned int BANK_INTERLEAVE_SIZE : 3; 52 unsigned int : 1; 53 unsigned int NUM_BANKS : 3; 54 unsigned int : 1; 55 unsigned int SHADER_ENGINE_TILE_SIZE : 3; 56 unsigned int NUM_SHADER_ENGINES : 2; 57 unsigned int NUM_GPUS : 3; 58 unsigned int MULTI_GPU_TILE_SIZE : 2; 59 unsigned int NUM_RB_PER_SE : 2; 60 unsigned int ROW_SIZE : 2; 61 unsigned int NUM_LOWER_PIPES : 1; 62 unsigned int SE_ENABLE : 1; 63 #elif defined(BIGENDIAN_CPU) 64 unsigned int SE_ENABLE : 1; 65 unsigned int NUM_LOWER_PIPES : 1; 66 unsigned int ROW_SIZE : 2; 67 unsigned int NUM_RB_PER_SE : 2; 68 unsigned int MULTI_GPU_TILE_SIZE : 2; 69 unsigned int NUM_GPUS : 3; 70 unsigned int NUM_SHADER_ENGINES : 2; 71 unsigned int SHADER_ENGINE_TILE_SIZE : 3; 72 unsigned int : 1; 73 unsigned int NUM_BANKS : 3; 74 unsigned int : 1; 75 unsigned int BANK_INTERLEAVE_SIZE : 3; 76 unsigned int MAX_COMPRESSED_FRAGS : 2; 77 unsigned int PIPE_INTERLEAVE_SIZE : 3; 78 unsigned int NUM_PIPES : 3; 79 #endif 80 } bitfields, bits; 81 unsigned int u32All; 82 signed int i32All; 83 float f32All; 84 }; 85 86 #endif 87 88