1 /************************************************************************** 2 * 3 * Copyright 2017 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #ifndef _RADEON_VCN_ENC_H 29 #define _RADEON_VCN_ENC_H 30 31 #include "radeon_vcn.h" 32 33 #define RENCODE_IB_OP_INITIALIZE 0x01000001 34 #define RENCODE_IB_OP_CLOSE_SESSION 0x01000002 35 #define RENCODE_IB_OP_ENCODE 0x01000003 36 #define RENCODE_IB_OP_INIT_RC 0x01000004 37 #define RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x01000005 38 #define RENCODE_IB_OP_SET_SPEED_ENCODING_MODE 0x01000006 39 #define RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE 0x01000007 40 #define RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE 0x01000008 41 42 #define RENCODE_IF_MAJOR_VERSION_MASK 0xFFFF0000 43 #define RENCODE_IF_MAJOR_VERSION_SHIFT 16 44 #define RENCODE_IF_MINOR_VERSION_MASK 0x0000FFFF 45 #define RENCODE_IF_MINOR_VERSION_SHIFT 0 46 47 #define RENCODE_ENGINE_TYPE_ENCODE 1 48 49 #define RENCODE_ENCODE_STANDARD_HEVC 0 50 #define RENCODE_ENCODE_STANDARD_H264 1 51 52 #define RENCODE_PREENCODE_MODE_NONE 0x00000000 53 #define RENCODE_PREENCODE_MODE_1X 0x00000001 54 #define RENCODE_PREENCODE_MODE_2X 0x00000002 55 #define RENCODE_PREENCODE_MODE_4X 0x00000004 56 57 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS 0x00000000 58 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001 59 60 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS 0x00000000 61 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001 62 63 #define RENCODE_RATE_CONTROL_METHOD_NONE 0x00000000 64 #define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001 65 #define RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR 0x00000002 66 #define RENCODE_RATE_CONTROL_METHOD_CBR 0x00000003 67 68 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD 0x00000000 69 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS 0x00000001 70 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS 0x00000002 71 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS 0x00000003 72 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX 0x00000004 73 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_END_OF_SEQUENCE 0x00000005 74 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SEI 0x00000006 75 76 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS 16 77 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS 16 78 79 #define RENCODE_HEADER_INSTRUCTION_END 0x00000000 80 #define RENCODE_HEADER_INSTRUCTION_COPY 0x00000001 81 82 #define RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END 0x00010000 83 #define RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE 0x00010001 84 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT 0x00010002 85 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00010003 86 #define RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE 0x00010004 87 #define RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE 0x00010005 88 89 #define RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB 0x00020000 90 #define RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00020001 91 92 #define RENCODE_PICTURE_TYPE_B 0 93 #define RENCODE_PICTURE_TYPE_P 1 94 #define RENCODE_PICTURE_TYPE_I 2 95 #define RENCODE_PICTURE_TYPE_P_SKIP 3 96 97 #define RENCODE_INPUT_SWIZZLE_MODE_LINEAR 0 98 #define RENCODE_INPUT_SWIZZLE_MODE_256B_S 1 99 #define RENCODE_INPUT_SWIZZLE_MODE_4kB_S 5 100 #define RENCODE_INPUT_SWIZZLE_MODE_64kB_S 9 101 102 #define RENCODE_H264_PICTURE_STRUCTURE_FRAME 0 103 #define RENCODE_H264_PICTURE_STRUCTURE_TOP_FIELD 1 104 #define RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD 2 105 106 #define RENCODE_H264_INTERLACING_MODE_PROGRESSIVE 0 107 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_STACKED 1 108 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_INTERLEAVED 2 109 110 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE 0 111 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE 1 112 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISALBE_ACROSS_SLICE_BOUNDARY 2 113 114 #define RENCODE_INTRA_REFRESH_MODE_NONE 0 115 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_ROWS 1 116 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_COLUMNS 2 117 118 #define RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES 34 119 120 #define RENCODE_REC_SWIZZLE_MODE_LINEAR 0 121 #define RENCODE_REC_SWIZZLE_MODE_256B_S 1 122 123 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR 0 124 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1 125 126 #define RENCODE_FEEDBACK_BUFFER_MODE_LINEAR 0 127 #define RENCODE_FEEDBACK_BUFFER_MODE_CIRCULAR 1 128 129 #define RENCODE_MAX_NUM_TEMPORAL_LAYERS 4 130 131 #define RADEON_ENC_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value)) 132 #define RADEON_ENC_BEGIN(cmd) \ 133 { \ 134 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \ 135 RADEON_ENC_CS(cmd) 136 #define RADEON_ENC_READ(buf, domain, off) \ 137 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off)) 138 #define RADEON_ENC_WRITE(buf, domain, off) \ 139 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off)) 140 #define RADEON_ENC_READWRITE(buf, domain, off) \ 141 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off)) 142 #define RADEON_ENC_END() \ 143 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \ 144 enc->total_task_size += *begin; \ 145 } 146 147 typedef struct rvcn_enc_session_info_s { 148 uint32_t interface_version; 149 uint32_t sw_context_address_hi; 150 uint32_t sw_context_address_lo; 151 } rvcn_enc_session_info_t; 152 153 typedef struct rvcn_enc_task_info_s { 154 uint32_t total_size_of_all_packages; 155 uint32_t task_id; 156 uint32_t allowed_max_num_feedbacks; 157 } rvcn_enc_task_info_t; 158 159 typedef struct rvcn_enc_session_init_s { 160 uint32_t encode_standard; 161 uint32_t aligned_picture_width; 162 uint32_t aligned_picture_height; 163 uint32_t padding_width; 164 uint32_t padding_height; 165 uint32_t pre_encode_mode; 166 uint32_t pre_encode_chroma_enabled; 167 uint32_t slice_output_enabled; 168 uint32_t display_remote; 169 } rvcn_enc_session_init_t; 170 171 typedef struct rvcn_enc_layer_control_s { 172 uint32_t max_num_temporal_layers; 173 uint32_t num_temporal_layers; 174 } rvcn_enc_layer_control_t; 175 176 typedef struct rvcn_enc_layer_select_s { 177 uint32_t temporal_layer_index; 178 } rvcn_enc_layer_select_t; 179 180 typedef struct rvcn_enc_h264_slice_control_s { 181 uint32_t slice_control_mode; 182 union { 183 uint32_t num_mbs_per_slice; 184 uint32_t num_bits_per_slice; 185 }; 186 } rvcn_enc_h264_slice_control_t; 187 188 typedef struct rvcn_enc_hevc_slice_control_s { 189 uint32_t slice_control_mode; 190 union { 191 struct { 192 uint32_t num_ctbs_per_slice; 193 uint32_t num_ctbs_per_slice_segment; 194 } fixed_ctbs_per_slice; 195 196 struct { 197 uint32_t num_bits_per_slice; 198 uint32_t num_bits_per_slice_segment; 199 } fixed_bits_per_slice; 200 }; 201 } rvcn_enc_hevc_slice_control_t; 202 203 typedef struct rvcn_enc_h264_spec_misc_s { 204 uint32_t constrained_intra_pred_flag; 205 uint32_t cabac_enable; 206 uint32_t cabac_init_idc; 207 uint32_t half_pel_enabled; 208 uint32_t quarter_pel_enabled; 209 uint32_t profile_idc; 210 uint32_t level_idc; 211 uint32_t b_picture_enabled; 212 uint32_t weighted_bipred_idc; 213 } rvcn_enc_h264_spec_misc_t; 214 215 typedef struct rvcn_enc_hevc_spec_misc_s { 216 uint32_t log2_min_luma_coding_block_size_minus3; 217 uint32_t amp_disabled; 218 uint32_t strong_intra_smoothing_enabled; 219 uint32_t constrained_intra_pred_flag; 220 uint32_t cabac_init_flag; 221 uint32_t half_pel_enabled; 222 uint32_t quarter_pel_enabled; 223 } rvcn_enc_hevc_spec_misc_t; 224 225 typedef struct rvcn_enc_rate_ctl_session_init_s { 226 uint32_t rate_control_method; 227 uint32_t vbv_buffer_level; 228 } rvcn_enc_rate_ctl_session_init_t; 229 230 typedef struct rvcn_enc_rate_ctl_layer_init_s { 231 uint32_t target_bit_rate; 232 uint32_t peak_bit_rate; 233 uint32_t frame_rate_num; 234 uint32_t frame_rate_den; 235 uint32_t vbv_buffer_size; 236 uint32_t avg_target_bits_per_picture; 237 uint32_t peak_bits_per_picture_integer; 238 uint32_t peak_bits_per_picture_fractional; 239 } rvcn_enc_rate_ctl_layer_init_t; 240 241 typedef struct rvcn_enc_rate_ctl_per_picture_s { 242 uint32_t qp; 243 uint32_t min_qp_app; 244 uint32_t max_qp_app; 245 uint32_t max_au_size; 246 uint32_t enabled_filler_data; 247 uint32_t skip_frame_enable; 248 uint32_t enforce_hrd; 249 } rvcn_enc_rate_ctl_per_picture_t; 250 251 typedef struct rvcn_enc_quality_params_s { 252 uint32_t vbaq_mode; 253 uint32_t scene_change_sensitivity; 254 uint32_t scene_change_min_idr_interval; 255 uint32_t two_pass_search_center_map_mode; 256 } rvcn_enc_quality_params_t; 257 258 typedef struct rvcn_enc_direct_output_nalu_s { 259 uint32_t type; 260 uint32_t size; 261 uint32_t data[1]; 262 } rvcn_enc_direct_output_nalu_t; 263 264 typedef struct rvcn_enc_slice_header_s { 265 uint32_t bitstream_template[RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS]; 266 struct { 267 uint32_t instruction; 268 uint32_t num_bits; 269 } instructions[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS]; 270 } rvcn_enc_slice_header_t; 271 272 typedef struct rvcn_enc_h264_reference_picture_info_s { 273 unsigned int pic_type; 274 unsigned int is_long_term; 275 unsigned int picture_structure; 276 unsigned int pic_order_cnt; 277 } rvcn_enc_h264_reference_picture_info_t; 278 279 typedef struct rvcn_enc_encode_params_s { 280 uint32_t pic_type; 281 uint32_t allowed_max_bitstream_size; 282 uint32_t input_picture_luma_address_hi; 283 uint32_t input_picture_luma_address_lo; 284 uint32_t input_picture_chroma_address_hi; 285 uint32_t input_picture_chroma_address_lo; 286 uint32_t input_pic_luma_pitch; 287 uint32_t input_pic_chroma_pitch; 288 uint8_t input_pic_swizzle_mode; 289 uint32_t reference_picture_index; 290 uint32_t reconstructed_picture_index; 291 } rvcn_enc_encode_params_t; 292 293 typedef struct rvcn_enc_h264_encode_params_s { 294 uint32_t input_picture_structure; 295 uint32_t input_pic_order_cnt; 296 uint32_t interlaced_mode; 297 uint32_t reference_picture_structure; 298 uint32_t reference_picture1_index; 299 rvcn_enc_h264_reference_picture_info_t picture_info_l0_reference_picture0; 300 uint32_t l0_reference_picture1_index; 301 rvcn_enc_h264_reference_picture_info_t picture_info_l0_reference_picture1; 302 uint32_t l1_reference_picture0_index; 303 rvcn_enc_h264_reference_picture_info_t picture_info_l1_reference_picture0; 304 } rvcn_enc_h264_encode_params_t; 305 306 typedef struct rvcn_enc_h264_deblocking_filter_s { 307 uint32_t disable_deblocking_filter_idc; 308 int32_t alpha_c0_offset_div2; 309 int32_t beta_offset_div2; 310 int32_t cb_qp_offset; 311 int32_t cr_qp_offset; 312 } rvcn_enc_h264_deblocking_filter_t; 313 314 typedef struct rvcn_enc_hevc_deblocking_filter_s { 315 uint32_t loop_filter_across_slices_enabled; 316 int32_t deblocking_filter_disabled; 317 int32_t beta_offset_div2; 318 int32_t tc_offset_div2; 319 int32_t cb_qp_offset; 320 int32_t cr_qp_offset; 321 } rvcn_enc_hevc_deblocking_filter_t; 322 323 typedef struct rvcn_enc_intra_refresh_s { 324 uint32_t intra_refresh_mode; 325 uint32_t offset; 326 uint32_t region_size; 327 } rvcn_enc_intra_refresh_t; 328 329 typedef struct rvcn_enc_reconstructed_picture_s { 330 uint32_t luma_offset; 331 uint32_t chroma_offset; 332 } rvcn_enc_reconstructed_picture_t; 333 334 typedef struct rvcn_enc_reconstructed_picture_v4_0_s { 335 uint32_t luma_offset; 336 uint32_t chroma_offset; 337 union { 338 struct 339 { 340 uint32_t unused_offset1; 341 uint32_t unused_offset2; 342 } unused; 343 }; 344 } rvcn_enc_reconstructed_picture_v4_0_t; 345 346 typedef struct rvcn_enc_picture_info_s 347 { 348 bool in_use; 349 uint32_t frame_num; 350 } rvcn_enc_picture_info_t; 351 352 typedef struct rvcn_enc_pre_encode_input_picture_s { 353 union { 354 struct { 355 uint32_t luma_offset; 356 uint32_t chroma_offset; 357 } yuv; 358 struct { 359 uint32_t red_offset; 360 uint32_t green_offset; 361 uint32_t blue_offset; 362 } rgb; 363 }; 364 } rvcn_enc_pre_encode_input_picture_t; 365 366 typedef struct rvcn_enc_encode_context_buffer_s { 367 uint32_t encode_context_address_hi; 368 uint32_t encode_context_address_lo; 369 uint32_t swizzle_mode; 370 uint32_t rec_luma_pitch; 371 uint32_t rec_chroma_pitch; 372 uint32_t num_reconstructed_pictures; 373 rvcn_enc_reconstructed_picture_t reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 374 rvcn_enc_reconstructed_picture_v4_0_t reconstructed_pictures_v4_0[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 375 uint32_t pre_encode_picture_luma_pitch; 376 uint32_t pre_encode_picture_chroma_pitch; 377 rvcn_enc_reconstructed_picture_t 378 pre_encode_reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 379 rvcn_enc_reconstructed_picture_t pre_encode_input_picture; 380 uint32_t two_pass_search_center_map_offset; 381 uint32_t colloc_buffer_offset; 382 } rvcn_enc_encode_context_buffer_t; 383 384 typedef struct rvcn_enc_video_bitstream_buffer_s { 385 uint32_t mode; 386 uint32_t video_bitstream_buffer_address_hi; 387 uint32_t video_bitstream_buffer_address_lo; 388 uint32_t video_bitstream_buffer_size; 389 uint32_t video_bitstream_data_offset; 390 } rvcn_enc_video_bitstream_buffer_t; 391 392 typedef struct rvcn_enc_feedback_buffer_s { 393 uint32_t mode; 394 uint32_t feedback_buffer_address_hi; 395 uint32_t feedback_buffer_address_lo; 396 uint32_t feedback_buffer_size; 397 uint32_t feedback_data_size; 398 } rvcn_enc_feedback_buffer_t; 399 400 typedef struct rvcn_enc_cmd_s { 401 uint32_t session_info; 402 uint32_t task_info; 403 uint32_t session_init; 404 uint32_t layer_control; 405 uint32_t layer_select; 406 uint32_t rc_session_init; 407 uint32_t rc_layer_init; 408 uint32_t rc_per_pic; 409 uint32_t quality_params; 410 uint32_t slice_header; 411 uint32_t enc_params; 412 uint32_t intra_refresh; 413 uint32_t ctx; 414 uint32_t bitstream; 415 uint32_t feedback; 416 uint32_t nalu; 417 uint32_t slice_control_hevc; 418 uint32_t spec_misc_hevc; 419 uint32_t enc_params_hevc; 420 uint32_t deblocking_filter_hevc; 421 uint32_t slice_control_h264; 422 uint32_t spec_misc_h264; 423 uint32_t enc_params_h264; 424 uint32_t deblocking_filter_h264; 425 uint32_t input_format; 426 uint32_t output_format; 427 } rvcn_enc_cmd_t; 428 429 typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource, struct pb_buffer **handle, 430 struct radeon_surf **surface); 431 432 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context, 433 const struct pipe_video_codec *templat, 434 struct radeon_winsys *ws, 435 radeon_enc_get_buffer get_buffer); 436 437 struct radeon_enc_pic { 438 enum pipe_h2645_enc_picture_type picture_type; 439 440 unsigned frame_num; 441 unsigned pic_order_cnt; 442 unsigned pic_order_cnt_type; 443 unsigned ref_idx_l0; 444 unsigned ref_idx_l1; 445 unsigned crop_left; 446 unsigned crop_right; 447 unsigned crop_top; 448 unsigned crop_bottom; 449 unsigned general_tier_flag; 450 unsigned general_profile_idc; 451 unsigned general_level_idc; 452 unsigned max_poc; 453 unsigned log2_max_poc; 454 unsigned chroma_format_idc; 455 unsigned pic_width_in_luma_samples; 456 unsigned pic_height_in_luma_samples; 457 unsigned log2_diff_max_min_luma_coding_block_size; 458 unsigned log2_min_transform_block_size_minus2; 459 unsigned log2_diff_max_min_transform_block_size; 460 unsigned max_transform_hierarchy_depth_inter; 461 unsigned max_transform_hierarchy_depth_intra; 462 unsigned log2_parallel_merge_level_minus2; 463 unsigned bit_depth_luma_minus8; 464 unsigned bit_depth_chroma_minus8; 465 unsigned nal_unit_type; 466 unsigned max_num_merge_cand; 467 unsigned temporal_id; 468 unsigned num_temporal_layers; 469 unsigned temporal_layer_pattern_index; 470 471 bool not_referenced; 472 bool is_idr; 473 bool is_even_frame; 474 bool sample_adaptive_offset_enabled_flag; 475 bool pcm_enabled_flag; 476 bool sps_temporal_mvp_enabled_flag; 477 478 rvcn_enc_session_info_t session_info; 479 rvcn_enc_task_info_t task_info; 480 rvcn_enc_session_init_t session_init; 481 rvcn_enc_layer_control_t layer_ctrl; 482 rvcn_enc_layer_select_t layer_sel; 483 rvcn_enc_h264_slice_control_t slice_ctrl; 484 rvcn_enc_hevc_slice_control_t hevc_slice_ctrl; 485 rvcn_enc_h264_spec_misc_t spec_misc; 486 rvcn_enc_hevc_spec_misc_t hevc_spec_misc; 487 rvcn_enc_rate_ctl_session_init_t rc_session_init; 488 rvcn_enc_rate_ctl_layer_init_t rc_layer_init[RENCODE_MAX_NUM_TEMPORAL_LAYERS]; 489 rvcn_enc_h264_encode_params_t h264_enc_params; 490 rvcn_enc_h264_deblocking_filter_t h264_deblock; 491 rvcn_enc_hevc_deblocking_filter_t hevc_deblock; 492 rvcn_enc_rate_ctl_per_picture_t rc_per_pic; 493 rvcn_enc_quality_params_t quality_params; 494 rvcn_enc_encode_context_buffer_t ctx_buf; 495 rvcn_enc_video_bitstream_buffer_t bit_buf; 496 rvcn_enc_feedback_buffer_t fb_buf; 497 rvcn_enc_intra_refresh_t intra_ref; 498 rvcn_enc_encode_params_t enc_params; 499 }; 500 501 struct radeon_encoder { 502 struct pipe_video_codec base; 503 504 void (*begin)(struct radeon_encoder *enc); 505 void (*before_encode)(struct radeon_encoder *enc); 506 void (*encode)(struct radeon_encoder *enc); 507 void (*destroy)(struct radeon_encoder *enc); 508 void (*session_info)(struct radeon_encoder *enc); 509 void (*task_info)(struct radeon_encoder *enc, bool need_feedback); 510 void (*session_init)(struct radeon_encoder *enc); 511 void (*layer_control)(struct radeon_encoder *enc); 512 void (*layer_select)(struct radeon_encoder *enc); 513 void (*slice_control)(struct radeon_encoder *enc); 514 void (*spec_misc)(struct radeon_encoder *enc); 515 void (*rc_session_init)(struct radeon_encoder *enc); 516 void (*rc_layer_init)(struct radeon_encoder *enc); 517 void (*deblocking_filter)(struct radeon_encoder *enc); 518 void (*quality_params)(struct radeon_encoder *enc); 519 void (*nalu_sps)(struct radeon_encoder *enc); 520 void (*nalu_pps)(struct radeon_encoder *enc); 521 void (*nalu_vps)(struct radeon_encoder *enc); 522 void (*nalu_aud)(struct radeon_encoder *enc); 523 void (*nalu_sei)(struct radeon_encoder *enc); 524 void (*nalu_prefix)(struct radeon_encoder *enc); 525 void (*slice_header)(struct radeon_encoder *enc); 526 void (*ctx)(struct radeon_encoder *enc); 527 void (*bitstream)(struct radeon_encoder *enc); 528 void (*feedback)(struct radeon_encoder *enc); 529 void (*intra_refresh)(struct radeon_encoder *enc); 530 void (*rc_per_pic)(struct radeon_encoder *enc); 531 void (*encode_params)(struct radeon_encoder *enc); 532 void (*encode_params_codec_spec)(struct radeon_encoder *enc); 533 void (*op_init)(struct radeon_encoder *enc); 534 void (*op_close)(struct radeon_encoder *enc); 535 void (*op_enc)(struct radeon_encoder *enc); 536 void (*op_init_rc)(struct radeon_encoder *enc); 537 void (*op_init_rc_vbv)(struct radeon_encoder *enc); 538 void (*op_preset)(struct radeon_encoder *enc); 539 void (*encode_headers)(struct radeon_encoder *enc); 540 void (*input_format)(struct radeon_encoder *enc); 541 void (*output_format)(struct radeon_encoder *enc); 542 /* mq is used for preversing multiple queue ibs */ 543 void (*mq_begin)(struct radeon_encoder *enc); 544 void (*mq_encode)(struct radeon_encoder *enc); 545 void (*mq_destroy)(struct radeon_encoder *enc); 546 547 unsigned stream_handle; 548 549 struct pipe_screen *screen; 550 struct radeon_winsys *ws; 551 struct radeon_cmdbuf cs; 552 553 radeon_enc_get_buffer get_buffer; 554 555 struct pb_buffer *handle; 556 struct radeon_surf *luma; 557 struct radeon_surf *chroma; 558 559 struct pb_buffer *bs_handle; 560 unsigned bs_size; 561 562 unsigned cpb_num; 563 564 struct rvid_buffer *si; 565 struct rvid_buffer *fb; 566 struct rvid_buffer cpb; 567 struct radeon_enc_pic enc_pic; 568 rvcn_enc_cmd_t cmd; 569 570 unsigned alignment; 571 unsigned shifter; 572 unsigned bits_in_shifter; 573 unsigned num_zeros; 574 unsigned byte_index; 575 unsigned bits_output; 576 unsigned bits_size; 577 uint32_t total_task_size; 578 uint32_t *p_task_size; 579 struct rvcn_sq_var sq; 580 581 bool emulation_prevention; 582 bool need_feedback; 583 unsigned dpb_size; 584 rvcn_enc_picture_info_t dpb[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 585 }; 586 587 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf, 588 unsigned usage, enum radeon_bo_domain domain, signed offset); 589 590 void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set); 591 592 void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte); 593 594 void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte); 595 596 void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value, 597 unsigned int num_bits); 598 599 void radeon_enc_reset(struct radeon_encoder *enc); 600 601 void radeon_enc_byte_align(struct radeon_encoder *enc); 602 603 void radeon_enc_flush_headers(struct radeon_encoder *enc); 604 605 void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value); 606 607 void radeon_enc_code_se(struct radeon_encoder *enc, int value); 608 609 void radeon_enc_1_2_init(struct radeon_encoder *enc); 610 611 void radeon_enc_2_0_init(struct radeon_encoder *enc); 612 613 void radeon_enc_3_0_init(struct radeon_encoder *enc); 614 615 void radeon_enc_4_0_init(struct radeon_encoder *enc); 616 617 #endif // _RADEON_VCN_ENC_H 618