1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE 23 * 24 ***********************************************************************************************************************/ 25 26 /** 27 ************************************************************************************************************************ 28 * @file gfx9addrlib.h 29 * @brief Contgfx9ns the Gfx9Lib class definition. 30 ************************************************************************************************************************ 31 */ 32 33 #ifndef __GFX9_ADDR_LIB_H__ 34 #define __GFX9_ADDR_LIB_H__ 35 36 #include "addrlib2.h" 37 #include "coord.h" 38 39 namespace Addr 40 { 41 namespace V2 42 { 43 44 /** 45 ************************************************************************************************************************ 46 * @brief GFX9 specific settings structure. 47 ************************************************************************************************************************ 48 */ 49 struct Gfx9ChipSettings 50 { 51 struct 52 { 53 // Asic/Generation name 54 UINT_32 isArcticIsland : 1; 55 UINT_32 isVega10 : 1; 56 UINT_32 isRaven : 1; 57 UINT_32 isVega12 : 1; 58 UINT_32 isVega20 : 1; 59 UINT_32 reserved0 : 27; 60 61 // Display engine IP version name 62 UINT_32 isDce12 : 1; 63 UINT_32 isDcn1 : 1; 64 UINT_32 isDcn2 : 1; 65 UINT_32 reserved1 : 29; 66 67 // Misc configuration bits 68 UINT_32 metaBaseAlignFix : 1; 69 UINT_32 depthPipeXorDisable : 1; 70 UINT_32 htileAlignFix : 1; 71 UINT_32 applyAliasFix : 1; 72 UINT_32 htileCacheRbConflict: 1; 73 UINT_32 reserved2 : 27; 74 }; 75 }; 76 77 /** 78 ************************************************************************************************************************ 79 * @brief GFX9 data surface type. 80 ************************************************************************************************************************ 81 */ 82 enum Gfx9DataType 83 { 84 Gfx9DataColor, 85 Gfx9DataDepthStencil, 86 Gfx9DataFmask 87 }; 88 89 const UINT_32 Gfx9LinearSwModeMask = (1u << ADDR_SW_LINEAR); 90 91 const UINT_32 Gfx9Blk256BSwModeMask = (1u << ADDR_SW_256B_S) | 92 (1u << ADDR_SW_256B_D) | 93 (1u << ADDR_SW_256B_R); 94 95 const UINT_32 Gfx9Blk4KBSwModeMask = (1u << ADDR_SW_4KB_Z) | 96 (1u << ADDR_SW_4KB_S) | 97 (1u << ADDR_SW_4KB_D) | 98 (1u << ADDR_SW_4KB_R) | 99 (1u << ADDR_SW_4KB_Z_X) | 100 (1u << ADDR_SW_4KB_S_X) | 101 (1u << ADDR_SW_4KB_D_X) | 102 (1u << ADDR_SW_4KB_R_X); 103 104 const UINT_32 Gfx9Blk64KBSwModeMask = (1u << ADDR_SW_64KB_Z) | 105 (1u << ADDR_SW_64KB_S) | 106 (1u << ADDR_SW_64KB_D) | 107 (1u << ADDR_SW_64KB_R) | 108 (1u << ADDR_SW_64KB_Z_T) | 109 (1u << ADDR_SW_64KB_S_T) | 110 (1u << ADDR_SW_64KB_D_T) | 111 (1u << ADDR_SW_64KB_R_T) | 112 (1u << ADDR_SW_64KB_Z_X) | 113 (1u << ADDR_SW_64KB_S_X) | 114 (1u << ADDR_SW_64KB_D_X) | 115 (1u << ADDR_SW_64KB_R_X); 116 117 const UINT_32 Gfx9ZSwModeMask = (1u << ADDR_SW_4KB_Z) | 118 (1u << ADDR_SW_64KB_Z) | 119 (1u << ADDR_SW_64KB_Z_T) | 120 (1u << ADDR_SW_4KB_Z_X) | 121 (1u << ADDR_SW_64KB_Z_X); 122 123 const UINT_32 Gfx9StandardSwModeMask = (1u << ADDR_SW_256B_S) | 124 (1u << ADDR_SW_4KB_S) | 125 (1u << ADDR_SW_64KB_S) | 126 (1u << ADDR_SW_64KB_S_T) | 127 (1u << ADDR_SW_4KB_S_X) | 128 (1u << ADDR_SW_64KB_S_X); 129 130 const UINT_32 Gfx9DisplaySwModeMask = (1u << ADDR_SW_256B_D) | 131 (1u << ADDR_SW_4KB_D) | 132 (1u << ADDR_SW_64KB_D) | 133 (1u << ADDR_SW_64KB_D_T) | 134 (1u << ADDR_SW_4KB_D_X) | 135 (1u << ADDR_SW_64KB_D_X); 136 137 const UINT_32 Gfx9RotateSwModeMask = (1u << ADDR_SW_256B_R) | 138 (1u << ADDR_SW_4KB_R) | 139 (1u << ADDR_SW_64KB_R) | 140 (1u << ADDR_SW_64KB_R_T) | 141 (1u << ADDR_SW_4KB_R_X) | 142 (1u << ADDR_SW_64KB_R_X); 143 144 const UINT_32 Gfx9XSwModeMask = (1u << ADDR_SW_4KB_Z_X) | 145 (1u << ADDR_SW_4KB_S_X) | 146 (1u << ADDR_SW_4KB_D_X) | 147 (1u << ADDR_SW_4KB_R_X) | 148 (1u << ADDR_SW_64KB_Z_X) | 149 (1u << ADDR_SW_64KB_S_X) | 150 (1u << ADDR_SW_64KB_D_X) | 151 (1u << ADDR_SW_64KB_R_X); 152 153 const UINT_32 Gfx9TSwModeMask = (1u << ADDR_SW_64KB_Z_T) | 154 (1u << ADDR_SW_64KB_S_T) | 155 (1u << ADDR_SW_64KB_D_T) | 156 (1u << ADDR_SW_64KB_R_T); 157 158 const UINT_32 Gfx9XorSwModeMask = Gfx9XSwModeMask | 159 Gfx9TSwModeMask; 160 161 const UINT_32 Gfx9AllSwModeMask = Gfx9LinearSwModeMask | 162 Gfx9ZSwModeMask | 163 Gfx9StandardSwModeMask | 164 Gfx9DisplaySwModeMask | 165 Gfx9RotateSwModeMask; 166 167 const UINT_32 Gfx9Rsrc1dSwModeMask = Gfx9LinearSwModeMask; 168 169 const UINT_32 Gfx9Rsrc2dSwModeMask = Gfx9AllSwModeMask; 170 171 const UINT_32 Gfx9Rsrc3dSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9RotateSwModeMask; 172 173 const UINT_32 Gfx9Rsrc2dPrtSwModeMask = (Gfx9Blk4KBSwModeMask | Gfx9Blk64KBSwModeMask) & ~Gfx9XSwModeMask; 174 175 const UINT_32 Gfx9Rsrc3dPrtSwModeMask = Gfx9Rsrc2dPrtSwModeMask & ~Gfx9RotateSwModeMask & ~Gfx9DisplaySwModeMask; 176 177 const UINT_32 Gfx9Rsrc3dThinSwModeMask = Gfx9DisplaySwModeMask & ~Gfx9Blk256BSwModeMask; 178 179 const UINT_32 Gfx9Rsrc3dThin4KBSwModeMask = Gfx9Rsrc3dThinSwModeMask & Gfx9Blk4KBSwModeMask; 180 181 const UINT_32 Gfx9Rsrc3dThin64KBSwModeMask = Gfx9Rsrc3dThinSwModeMask & Gfx9Blk64KBSwModeMask; 182 183 const UINT_32 Gfx9Rsrc3dThickSwModeMask = Gfx9Rsrc3dSwModeMask & ~(Gfx9Rsrc3dThinSwModeMask | Gfx9LinearSwModeMask); 184 185 const UINT_32 Gfx9Rsrc3dThick4KBSwModeMask = Gfx9Rsrc3dThickSwModeMask & Gfx9Blk4KBSwModeMask; 186 187 const UINT_32 Gfx9Rsrc3dThick64KBSwModeMask = Gfx9Rsrc3dThickSwModeMask & Gfx9Blk64KBSwModeMask; 188 189 const UINT_32 Gfx9MsaaSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9LinearSwModeMask; 190 191 const UINT_32 Dce12NonBpp32SwModeMask = (1u << ADDR_SW_LINEAR) | 192 (1u << ADDR_SW_4KB_D) | 193 (1u << ADDR_SW_4KB_R) | 194 (1u << ADDR_SW_64KB_D) | 195 (1u << ADDR_SW_64KB_R) | 196 (1u << ADDR_SW_4KB_D_X) | 197 (1u << ADDR_SW_4KB_R_X) | 198 (1u << ADDR_SW_64KB_D_X) | 199 (1u << ADDR_SW_64KB_R_X); 200 201 const UINT_32 Dce12Bpp32SwModeMask = (1u << ADDR_SW_256B_D) | 202 (1u << ADDR_SW_256B_R) | 203 Dce12NonBpp32SwModeMask; 204 205 const UINT_32 Dcn1NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 206 (1u << ADDR_SW_4KB_S) | 207 (1u << ADDR_SW_64KB_S) | 208 (1u << ADDR_SW_64KB_S_T) | 209 (1u << ADDR_SW_4KB_S_X) | 210 (1u << ADDR_SW_64KB_S_X); 211 const UINT_32 Dcn1Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) | 212 (1u << ADDR_SW_64KB_D) | 213 (1u << ADDR_SW_64KB_D_T) | 214 (1u << ADDR_SW_4KB_D_X) | 215 (1u << ADDR_SW_64KB_D_X) | 216 Dcn1NonBpp64SwModeMask; 217 218 const UINT_32 Dcn2NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 219 (1u << ADDR_SW_64KB_S) | 220 (1u << ADDR_SW_64KB_S_T) | 221 (1u << ADDR_SW_64KB_S_X); 222 223 const UINT_32 Dcn2Bpp64SwModeMask = (1u << ADDR_SW_64KB_D) | 224 (1u << ADDR_SW_64KB_D_T) | 225 (1u << ADDR_SW_64KB_D_X) | 226 Dcn2NonBpp64SwModeMask; 227 228 /** 229 ************************************************************************************************************************ 230 * @brief GFX9 meta equation parameters 231 ************************************************************************************************************************ 232 */ 233 struct MetaEqParams 234 { 235 UINT_32 maxMip; 236 UINT_32 elementBytesLog2; 237 UINT_32 numSamplesLog2; 238 ADDR2_META_FLAGS metaFlag; 239 Gfx9DataType dataSurfaceType; 240 AddrSwizzleMode swizzleMode; 241 AddrResourceType resourceType; 242 UINT_32 metaBlkWidthLog2; 243 UINT_32 metaBlkHeightLog2; 244 UINT_32 metaBlkDepthLog2; 245 UINT_32 compBlkWidthLog2; 246 UINT_32 compBlkHeightLog2; 247 UINT_32 compBlkDepthLog2; 248 }; 249 250 /** 251 ************************************************************************************************************************ 252 * @brief This class is the GFX9 specific address library 253 * function set. 254 ************************************************************************************************************************ 255 */ 256 class Gfx9Lib : public Lib 257 { 258 public: 259 /// Creates Gfx9Lib object CreateObj(const Client * pClient)260 static Addr::Lib* CreateObj(const Client* pClient) 261 { 262 VOID* pMem = Object::ClientAlloc(sizeof(Gfx9Lib), pClient); 263 return (pMem != NULL) ? new (pMem) Gfx9Lib(pClient) : NULL; 264 } 265 266 protected: 267 Gfx9Lib(const Client* pClient); 268 virtual ~Gfx9Lib(); 269 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)270 virtual BOOL_32 HwlIsStandardSwizzle( 271 AddrResourceType resourceType, 272 AddrSwizzleMode swizzleMode) const 273 { 274 return m_swizzleModeTable[swizzleMode].isStd || 275 (IsTex3d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp); 276 } 277 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)278 virtual BOOL_32 HwlIsDisplaySwizzle( 279 AddrResourceType resourceType, 280 AddrSwizzleMode swizzleMode) const 281 { 282 return IsTex2d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp; 283 } 284 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)285 virtual BOOL_32 HwlIsThin( 286 AddrResourceType resourceType, 287 AddrSwizzleMode swizzleMode) const 288 { 289 return ((IsTex2d(resourceType) == TRUE) || 290 ((IsTex3d(resourceType) == TRUE) && 291 (m_swizzleModeTable[swizzleMode].isZ == FALSE) && 292 (m_swizzleModeTable[swizzleMode].isStd == FALSE))); 293 } 294 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)295 virtual BOOL_32 HwlIsThick( 296 AddrResourceType resourceType, 297 AddrSwizzleMode swizzleMode) const 298 { 299 return (IsTex3d(resourceType) && 300 (m_swizzleModeTable[swizzleMode].isZ || m_swizzleModeTable[swizzleMode].isStd)); 301 } 302 303 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 304 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 305 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 306 307 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 308 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 309 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 310 311 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 312 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 313 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 314 315 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 316 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 317 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 318 319 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 320 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 321 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 322 323 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 324 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 325 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 326 327 virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord( 328 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn); 329 330 virtual VOID HwlComputeDccAddrFromCoord( 331 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 332 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 333 334 virtual UINT_32 HwlGetEquationIndex( 335 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 336 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 337 338 virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation( 339 AddrResourceType rsrcType, 340 AddrSwizzleMode swMode, 341 UINT_32 elementBytesLog2, 342 ADDR_EQUATION* pEquation) const; 343 344 virtual ADDR_E_RETURNCODE HwlComputeThinEquation( 345 AddrResourceType rsrcType, 346 AddrSwizzleMode swMode, 347 UINT_32 elementBytesLog2, 348 ADDR_EQUATION* pEquation) const; 349 350 virtual ADDR_E_RETURNCODE HwlComputeThickEquation( 351 AddrResourceType rsrcType, 352 AddrSwizzleMode swMode, 353 UINT_32 elementBytesLog2, 354 ADDR_EQUATION* pEquation) const; 355 356 // Get equation table pointer and number of equations HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)357 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 358 { 359 *ppEquationTable = m_equationTable; 360 361 return m_numEquations; 362 } 363 364 virtual BOOL_32 IsEquationSupported( 365 AddrResourceType rsrcType, 366 AddrSwizzleMode swMode, 367 UINT_32 elementBytesLog2) const; 368 369 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 370 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 371 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const; 372 373 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 374 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 375 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const; 376 377 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 378 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 379 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const; 380 381 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 382 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 383 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 384 385 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 386 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 387 388 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 389 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 390 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 391 392 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 393 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 394 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 395 396 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 397 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 398 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 399 400 virtual UINT_32 HwlComputeMaxBaseAlignments() const; 401 402 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const; 403 404 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn); 405 406 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 407 408 virtual VOID ComputeThinBlockDimension( 409 UINT_32* pWidth, 410 UINT_32* pHeight, 411 UINT_32* pDepth, 412 UINT_32 bpp, 413 UINT_32 numSamples, 414 AddrResourceType resourceType, 415 AddrSwizzleMode swizzleMode) const; 416 417 private: 418 VOID GetRbEquation(CoordEq* pRbEq, UINT_32 rbPerSeLog2, UINT_32 seLog2) const; 419 420 VOID GetDataEquation(CoordEq* pDataEq, Gfx9DataType dataSurfaceType, 421 AddrSwizzleMode swizzleMode, AddrResourceType resourceType, 422 UINT_32 elementBytesLog2, UINT_32 numSamplesLog2) const; 423 424 VOID GetPipeEquation(CoordEq* pPipeEq, CoordEq* pDataEq, 425 UINT_32 pipeInterleaveLog2, UINT_32 numPipesLog2, 426 UINT_32 numSamplesLog2, Gfx9DataType dataSurfaceType, 427 AddrSwizzleMode swizzleMode, AddrResourceType resourceType) const; 428 429 VOID GenMetaEquation(CoordEq* pMetaEq, UINT_32 maxMip, 430 UINT_32 elementBytesLog2, UINT_32 numSamplesLog2, 431 ADDR2_META_FLAGS metaFlag, Gfx9DataType dataSurfaceType, 432 AddrSwizzleMode swizzleMode, AddrResourceType resourceType, 433 UINT_32 metaBlkWidthLog2, UINT_32 metaBlkHeightLog2, 434 UINT_32 metaBlkDepthLog2, UINT_32 compBlkWidthLog2, 435 UINT_32 compBlkHeightLog2, UINT_32 compBlkDepthLog2) const; 436 437 const CoordEq* GetMetaEquation(const MetaEqParams& metaEqParams); 438 439 VOID GetMetaMipInfo(UINT_32 numMipLevels, Dim3d* pMetaBlkDim, 440 BOOL_32 dataThick, ADDR2_META_MIP_INFO* pInfo, 441 UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth, 442 UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const; 443 444 BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 445 446 ADDR_E_RETURNCODE ComputeSurfaceLinearPadding( 447 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 448 UINT_32* pMipmap0PaddedWidth, 449 UINT_32* pSlice0PaddedHeight, 450 ADDR2_MIP_INFO* pMipInfo = NULL) const; 451 GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet,AddrResourceType rsrcType)452 static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType) 453 { 454 ADDR2_BLOCK_SET allowedBlockSet = {}; 455 456 allowedBlockSet.micro = (allowedSwModeSet.value & Gfx9Blk256BSwModeMask) ? TRUE : FALSE; 457 allowedBlockSet.linear = (allowedSwModeSet.value & Gfx9LinearSwModeMask) ? TRUE : FALSE; 458 459 if (rsrcType == ADDR_RSRC_TEX_3D) 460 { 461 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx9Rsrc3dThin4KBSwModeMask) ? TRUE : FALSE; 462 allowedBlockSet.macroThick4KB = (allowedSwModeSet.value & Gfx9Rsrc3dThick4KBSwModeMask) ? TRUE : FALSE; 463 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx9Rsrc3dThin64KBSwModeMask) ? TRUE : FALSE; 464 allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx9Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE; 465 } 466 else 467 { 468 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx9Blk4KBSwModeMask) ? TRUE : FALSE; 469 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx9Blk64KBSwModeMask) ? TRUE : FALSE; 470 } 471 472 return allowedBlockSet; 473 } 474 GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)475 static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet) 476 { 477 ADDR2_SWTYPE_SET allowedSwSet = {}; 478 479 allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx9ZSwModeMask) ? TRUE : FALSE; 480 allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx9StandardSwModeMask) ? TRUE : FALSE; 481 allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx9DisplaySwModeMask) ? TRUE : FALSE; 482 allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx9RotateSwModeMask) ? TRUE : FALSE; 483 484 return allowedSwSet; 485 } 486 IsInMipTail(AddrResourceType resourceType,AddrSwizzleMode swizzleMode,Dim3d mipTailDim,UINT_32 width,UINT_32 height,UINT_32 depth)487 BOOL_32 IsInMipTail( 488 AddrResourceType resourceType, 489 AddrSwizzleMode swizzleMode, 490 Dim3d mipTailDim, 491 UINT_32 width, 492 UINT_32 height, 493 UINT_32 depth) const 494 { 495 BOOL_32 inTail = ((width <= mipTailDim.w) && 496 (height <= mipTailDim.h) && 497 (IsThin(resourceType, swizzleMode) || (depth <= mipTailDim.d))); 498 499 return inTail; 500 } 501 502 BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 503 BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 504 GetBankXorBits(UINT_32 macroBlockBits)505 UINT_32 GetBankXorBits(UINT_32 macroBlockBits) const 506 { 507 UINT_32 pipeBits = GetPipeXorBits(macroBlockBits); 508 509 // Bank xor bits 510 UINT_32 bankBits = Min(macroBlockBits - pipeBits - m_pipeInterleaveLog2, m_banksLog2); 511 512 return bankBits; 513 } 514 ComputeSurfaceBaseAlignTiled(AddrSwizzleMode swizzleMode)515 UINT_32 ComputeSurfaceBaseAlignTiled(AddrSwizzleMode swizzleMode) const 516 { 517 UINT_32 baseAlign; 518 519 if (IsXor(swizzleMode)) 520 { 521 baseAlign = GetBlockSize(swizzleMode); 522 } 523 else 524 { 525 baseAlign = 256; 526 } 527 528 return baseAlign; 529 } 530 531 // Initialize equation table 532 VOID InitEquationTable(); 533 534 ADDR_E_RETURNCODE ComputeStereoInfo( 535 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 536 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut, 537 UINT_32* pHeightAlign) const; 538 539 UINT_32 GetMipChainInfo( 540 AddrResourceType resourceType, 541 AddrSwizzleMode swizzleMode, 542 UINT_32 bpp, 543 UINT_32 mip0Width, 544 UINT_32 mip0Height, 545 UINT_32 mip0Depth, 546 UINT_32 blockWidth, 547 UINT_32 blockHeight, 548 UINT_32 blockDepth, 549 UINT_32 numMipLevel, 550 ADDR2_MIP_INFO* pMipInfo) const; 551 552 VOID GetMetaMiptailInfo( 553 ADDR2_META_MIP_INFO* pInfo, 554 Dim3d mipCoord, 555 UINT_32 numMipInTail, 556 Dim3d* pMetaBlkDim) const; 557 558 Dim3d GetMipStartPos( 559 AddrResourceType resourceType, 560 AddrSwizzleMode swizzleMode, 561 UINT_32 width, 562 UINT_32 height, 563 UINT_32 depth, 564 UINT_32 blockWidth, 565 UINT_32 blockHeight, 566 UINT_32 blockDepth, 567 UINT_32 mipId, 568 UINT_32 log2ElementBytes, 569 UINT_32* pMipTailBytesOffset) const; 570 GetMajorMode(AddrResourceType resourceType,AddrSwizzleMode swizzleMode,UINT_32 mip0WidthInBlk,UINT_32 mip0HeightInBlk,UINT_32 mip0DepthInBlk)571 AddrMajorMode GetMajorMode( 572 AddrResourceType resourceType, 573 AddrSwizzleMode swizzleMode, 574 UINT_32 mip0WidthInBlk, 575 UINT_32 mip0HeightInBlk, 576 UINT_32 mip0DepthInBlk) const 577 { 578 BOOL_32 yMajor = (mip0WidthInBlk < mip0HeightInBlk); 579 BOOL_32 xMajor = (yMajor == FALSE); 580 581 if (IsThick(resourceType, swizzleMode)) 582 { 583 yMajor = yMajor && (mip0HeightInBlk >= mip0DepthInBlk); 584 xMajor = xMajor && (mip0WidthInBlk >= mip0DepthInBlk); 585 } 586 587 AddrMajorMode majorMode; 588 if (xMajor) 589 { 590 majorMode = ADDR_MAJOR_X; 591 } 592 else if (yMajor) 593 { 594 majorMode = ADDR_MAJOR_Y; 595 } 596 else 597 { 598 majorMode = ADDR_MAJOR_Z; 599 } 600 601 return majorMode; 602 } 603 GetDccCompressBlk(AddrResourceType resourceType,AddrSwizzleMode swizzleMode,UINT_32 bpp)604 Dim3d GetDccCompressBlk( 605 AddrResourceType resourceType, 606 AddrSwizzleMode swizzleMode, 607 UINT_32 bpp) const 608 { 609 UINT_32 index = Log2(bpp >> 3); 610 Dim3d compressBlkDim; 611 612 if (IsThin(resourceType, swizzleMode)) 613 { 614 compressBlkDim.w = Block256_2d[index].w; 615 compressBlkDim.h = Block256_2d[index].h; 616 compressBlkDim.d = 1; 617 } 618 else if (IsStandardSwizzle(resourceType, swizzleMode)) 619 { 620 compressBlkDim = Block256_3dS[index]; 621 } 622 else 623 { 624 compressBlkDim = Block256_3dZ[index]; 625 } 626 627 return compressBlkDim; 628 } 629 630 static const UINT_32 MaxSeLog2 = 3; 631 static const UINT_32 MaxRbPerSeLog2 = 2; 632 633 static const Dim3d Block256_3dS[MaxNumOfBpp]; 634 static const Dim3d Block256_3dZ[MaxNumOfBpp]; 635 636 static const UINT_32 MipTailOffset256B[]; 637 638 static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE]; 639 640 static const UINT_32 MaxCachedMetaEq = 2; 641 642 Gfx9ChipSettings m_settings; 643 644 CoordEq m_cachedMetaEq[MaxCachedMetaEq]; 645 MetaEqParams m_cachedMetaEqKey[MaxCachedMetaEq]; 646 UINT_32 m_metaEqOverrideIndex; 647 }; 648 649 } // V2 650 } // Addr 651 652 #endif 653 654