Searched refs:SCK (Results 1 – 22 of 22) sorted by relevance
/kernel/linux/linux-5.10/arch/arm/mach-sa1100/ |
D | assabet.c | 119 #define SCK GPIO_GPIO(18) macro 124 GPSR = SCK; in adv7171_start() 133 GPSR = SCK; in adv7171_stop() 144 GPCR = SCK; in adv7171_send() 151 GPSR = SCK; in adv7171_send() 154 GPCR = SCK; in adv7171_send() 159 GPSR = SCK; in adv7171_send() 164 GPCR = SCK | SDA; in adv7171_send() 178 GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */ in adv7171_write() 179 GPDR = (GPDR | SCK | MOD) & ~SDA; in adv7171_write() [all …]
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/kernel/linux/linux-5.10/Documentation/spi/ |
D | butterfly.rst | 34 SCK J403.PB1/SCK pin 2/D0 67 SCK J403.PE4/USCK pin 5/D3
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D | spi-summary.rst | 14 The three signal wires hold a clock (SCK, often on the order of 10 MHz), 62 chips described as using "three wire" signaling: SCK, data, nCSx. 519 SPI bus (shared SCK, MOSI, MISO). Valid bus numbers start at zero. On
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
D | fsl,esai.txt | 31 derive HCK, SCK and FS. 33 derive HCK, SCK and FS.
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/fpga/ |
D | lattice-ice40-fpga-mgr.txt | 10 FPGA will enter Master SPI mode and drive SCK with a
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
D | renesas,drif.txt | 8 | |-----SCK------->|CLK | 91 | |-----SCK------->|CLK | 139 | |-----SCK------->|CLK |
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/ |
D | meson-gxl-s905x-khadas-vim.dts | 154 "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
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D | meson-gxbb-nanopi-k2.dts | 228 "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
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D | meson-gxbb-odroidc2.dts | 284 "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/leds/ |
D | leds-bcm6358.txt | 16 - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8.
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/kernel/linux/linux-5.10/drivers/mfd/ |
D | mt6358-irq.c | 20 MT6358_TOP_GEN(SCK),
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/kernel/linux/linux-5.10/Documentation/driver-api/ |
D | spi.rst | 6 multiplexed shift register. Its three signal wires hold a clock (SCK,
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/kernel/linux/linux-5.10/arch/arm/boot/dts/ |
D | ste-nomadik-nhk15.dts | 210 * As we're dealing with 3wire SPI, we only define SCK
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D | sun7i-a20-bananapi.dts | 210 "PMU-SCK", "PMU-SDA", "", "", "", "", "", "",
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D | pxa300-raumfeld-common.dtsi | 331 MFP_PIN_PXA300(95) MFP_AF0 /* SCK */
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/kernel/linux/linux-5.10/Documentation/translations/zh_CN/ |
D | gpio.txt | 409 从设备延迟 SCK 的上升沿,而 I2C 主设备相应地调整其信号传输速率。
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/kernel/linux/linux-5.10/Documentation/driver-api/gpio/ |
D | intro.rst | 123 delays the rising edge of SCK, and the I2C master adjusts its signaling rate
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D | drivers-on-gpio.rst | 54 of wires, at least SCK and optionally MISO, MOSI and chip select lines) using
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D | legacy.rst | 440 slower clock delays the rising edge of SCK, and the I2C master adjusts its
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/kernel/linux/linux-5.10/drivers/spi/ |
D | Kconfig | 365 interface to manage MOSI, MISO, SCK, and chipselect signals. SPI
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/ |
D | 0022_linux_drivers_i2c.patch | 2582 + * cause the SCK low level period less than 1.3us.
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/ |
D | 0009_linux_sound.patch | 10062 - * @extalclk: esai clock source to derive HCK, SCK and FS 10063 - * @fsysclk: system clock source to derive HCK, SCK and FS 10472 + * @extalclk: esai clock source to derive HCK, SCK and FS 10473 + * @fsysclk: system clock source to derive HCK, SCK and FS
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