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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ds3c2416.dtsi31 clocks: clock-controller@4c000000 { label
43 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
44 <&clocks SCLK_UART>;
54 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
55 <&clocks MUX_HSMMC0>;
65 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
66 <&clocks MUX_HSMMC1>;
73 clocks = <&clocks PCLK_I2C0>;
87 clocks = <&clocks PCLK_RTC>;
92 clocks = <&clocks PCLK_PWM>;
[all …]
Ds5pv210.dtsi82 clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
94 clocks: clock-controller@e0100000 { label
98 clocks = <&xxti>, <&xusbxti>;
125 clocks = <&clocks CLK_PDMA0>;
137 clocks = <&clocks CLK_PDMA1>;
149 clocks = <&clocks CLK_TSADC>;
163 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
179 clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
193 clocks = <&clocks CLK_KEYIF>;
203 clocks = <&clocks CLK_I2C0>;
[all …]
Domap24xx-clocks.dtsi11 clocks = <&func_96m_ck>, <&mcbsp_clks>;
19 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
25 clocks = <&func_96m_ck>, <&mcbsp_clks>;
33 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
77 clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
85 clocks = <&aplls_clkin_ck>;
93 clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
102 clocks = <&osc_ck>;
124 clocks = <&sys_ck>, <&sys_ck>;
131 clocks = <&sys_ck>;
[all …]
Domap3xxx-clocks.dtsi17clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck…
24 clocks = <&osc_sys_ck>;
34 clocks = <&osc_sys_ck>;
42 clocks = <&dpll3_ck>;
50 clocks = <&dpll3_m2_ck>;
58 clocks = <&dpll4_ck>;
66 clocks = <&dpll3_m2x2_ck>;
74 clocks = <&sys_ck>;
84 clocks = <&core_96m_fck>, <&mcbsp_clks>;
92 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
[all …]
Ds3c64xx.dtsi68 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
69 <&clocks SCLK_MMC0>;
79 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
80 <&clocks SCLK_MMC1>;
90 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
91 <&clocks SCLK_MMC2>;
101 clocks = <&clocks PCLK_WDT>;
110 clocks = <&clocks PCLK_IIC0>;
123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
124 <&clocks SCLK_UART>;
[all …]
Domap2430-clocks.dtsi12 clocks = <&func_96m_ck>, <&mcbsp_clks>;
19 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
25 clocks = <&func_96m_ck>, <&mcbsp_clks>;
33 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
39 clocks = <&func_96m_ck>, <&mcbsp_clks>;
47 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
55 clocks = <&dsp_fck>;
63 clocks = <&dsp_fck>;
73 clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
79 clocks = <&core_ck>;
[all …]
Dam43xx-clocks.dtsi11 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
19 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
27 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
35 clocks = <&sys_clkin_ck>;
43 clocks = <&sys_clkin_ck>;
51 clocks = <&sys_clkin_ck>;
59 clocks = <&sys_clkin_ck>;
67 clocks = <&sys_clkin_ck>;
75 clocks = <&sys_clkin_ck>;
83 clocks = <&sys_clkin_ck>;
[all …]
Domap54xx-clocks.dtsi17 clocks = <&pad_clks_src_ck>;
37 clocks = <&slimbus_src_clk>;
105 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
112 clocks = <&dpll_abe_ck>;
118 clocks = <&dpll_abe_x2_ck>;
127 clocks = <&dpll_abe_m2x2_ck>;
135 clocks = <&dpll_abe_m2x2_ck>;
144 clocks = <&aess_fclk>;
153 clocks = <&dpll_abe_m2x2_ck>;
161 clocks = <&dpll_abe_x2_ck>;
[all …]
Domap2420-clocks.dtsi12 clocks = <&core_ck>;
20 clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
28 clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
34 clocks = <&sys_clkout2_src>;
44 clocks = <&dsp_fck>;
52 clocks = <&dsp_fck>;
62 clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
68 clocks = <&core_ck>;
76 clocks = <&core_ck>;
85 clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
[all …]
Domap34xx-omap36xx-clocks.dtsi11 clocks = <&l4_ick>;
19 clocks = <&security_l4_ick2>;
27 clocks = <&security_l4_ick2>;
35 clocks = <&security_l4_ick2>;
43 clocks = <&security_l4_ick2>;
51 clocks = <&dpll4_m5x2_ck>;
60 clocks = <&l4_ick>;
68 clocks = <&core_96m_fck>;
76 clocks = <&l3_ick>;
84 clocks = <&security_l3_ick>;
[all …]
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi11 clocks = <&corex2_fck>;
19 clocks = <&corex2_fck>;
28 clocks = <&sys_ck>, <&sys_ck>;
37 clocks = <&dpll5_ck>;
46 clocks = <&core_ck>;
54 clocks = <&core_ck>;
62 clocks = <&core_ck>;
70 clocks = <&core_ck>;
78 clocks = <&dpll4_m2x2_ck>;
86 clocks = <&core_ck>;
[all …]
Ddra7xx-clocks.dtsi11 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
17 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
23 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
29 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
107 clocks = <&sys_clkin1>;
199 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
206 clocks = <&dpll_abe_ck>;
212 clocks = <&dpll_abe_x2_ck>;
223 clocks = <&dpll_abe_m2x2_ck>;
232 clocks = <&dpll_abe_ck>;
[all …]
Dam33xx-clocks.dtsi11 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
19 clocks = <&sys_clkin_ck>;
27 clocks = <&sys_clkin_ck>;
35 clocks = <&sys_clkin_ck>;
43 clocks = <&sys_clkin_ck>;
51 clocks = <&sys_clkin_ck>;
59 clocks = <&sys_clkin_ck>;
67 clocks = <&sys_clkin_ck>;
75 clocks = <&sys_clkin_ck>;
83 clocks = <&sys_clkin_ck>;
[all …]
Dste-nomadik-stn8815.dtsi40 clocks = <&timclk>, <&pclk>;
49 clocks = <&timclk>, <&pclk>;
64 clocks = <&pclk>;
78 clocks = <&pclk>;
92 clocks = <&pclk>;
107 clocks = <&pclk>;
215 clocks = <&mxtal>;
223 clocks = <&mxtal>;
230 clocks = <&pll1>;
238 clocks = <&hclk>;
[all …]
Domap3430es1-clocks.dtsi11 clocks = <&l3_ick>;
19 clocks = <&l3_ick>;
28 clocks = <&gfx_l3_ck>;
36 clocks = <&gfx_l3_fck>;
44 clocks = <&gfx_l3_fck>;
52 clocks = <&sys_ck>;
60 clocks = <&core_48m_fck>;
68 clocks = <&corex2_fck>;
76 clocks = <&corex2_fck>;
85 clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
[all …]
Domap44xx-clocks.dtsi23 clocks = <&pad_clks_src_ck>;
49 clocks = <&slimbus_src_clk>;
135 clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
142 clocks = <&dpll_abe_ck>;
149 clocks = <&dpll_abe_x2_ck>;
160 clocks = <&dpll_abe_m2x2_ck>;
168 clocks = <&dpll_abe_m2x2_ck>;
178 clocks = <&dpll_abe_x2_ck>;
189 clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
197 clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
[all …]
Domap36xx-omap3430es2plus-clocks.dtsi11 clocks = <&corex2_fck>;
19 clocks = <&corex2_fck>;
28 clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
34 clocks = <&ssi_ssr_fck>;
42 clocks = <&core_l3_ick>;
50 clocks = <&l4_ick>;
58 clocks = <&ssi_l4_ick>;
66 clocks = <&omap_96m_fck>;
74 clocks = <&sys_ck>;
82 clocks = <&omap_96m_fck>;
[all …]
Dsocfpga.dtsi85 clocks = <&l4_main_clk>;
104 clocks = <&can0_clk>;
113 clocks = <&can1_clk>;
122 clocks {
151 clocks = <&osc1>;
157 clocks = <&main_pll>;
165 clocks = <&main_pll>;
173 clocks = <&main_pll>, <&osc1>;
181 clocks = <&main_pll>;
188 clocks = <&main_pll>;
[all …]
Dwm8750.dtsi75 clocks {
94 clocks = <&ref25>;
101 clocks = <&ref25>;
108 clocks = <&ref25>;
115 clocks = <&ref25>;
122 clocks = <&ref25>;
129 clocks = <&plla>;
136 clocks = <&pllb>;
143 clocks = <&pllb>;
150 clocks = <&plld>;
[all …]
Dsh73a0.dtsi27 clocks = <&cpg_clocks SH73A0_CLK_Z>;
36 clocks = <&cpg_clocks SH73A0_CLK_Z>;
46 clocks = <&periph_clk>;
53 clocks = <&periph_clk>;
105 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
128 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
150 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
172 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
194 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
208 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
[all …]
Ddm816x-clocks.dtsi8 clocks = <&sys_clkin_ck &sys_clkin_ck>;
24 clocks = <&sys_clkin_ck &sys_clkin_ck>;
36 clocks = <&sys_clkin_ck &sys_clkin_ck>;
47 clocks = <&main_fapll 7>, < &sys_clkin_ck>;
88 clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
96 clocks = <&clkout_pre_ck>;
105 clocks = <&clkout_div_ck>;
110 /* CM_DPLL clocks p1795 */
114 clocks = <&main_fapll 1>;
122 clocks = <&main_fapll 2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/xilinx/
Dzynqmp-clk-ccf.dtsi44 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
48 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
52 clocks = <&zynqmp_clk ACPU>;
56 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
60 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
64 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
68 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
72 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
76 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
80 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
[all …]
/kernel/linux/linux-5.10/tools/testing/selftests/timens/
Dtimens.c39 static struct test_clock clocks[] = { variable
96 if (check_skip(clocks[clock_index].id)) in test_gettime()
99 switch (clocks[clock_index].id) { in test_gettime()
109 if (_gettime(clocks[clock_index].id, &parent_ts_old, raw_syscall)) in test_gettime()
118 if (_gettime(clocks[clock_index].id, &cur_ts, raw_syscall)) in test_gettime()
124 clocks[clock_index].name, entry, parent_ts_old.tv_sec, in test_gettime()
132 if (_gettime(clocks[clock_index].id, &cur_ts, raw_syscall)) in test_gettime()
138 clocks[clock_index].name, entry, parent_ts_old.tv_sec, in test_gettime()
141 clock_settime(clocks[clock_index].id, &cur_ts); in test_gettime()
146 clocks[clock_index].name, entry); in test_gettime()
[all …]
/kernel/linux/linux-5.10/drivers/clk/mediatek/
DKconfig20 This driver supports MediaTek MT2701 basic clocks.
26 This driver supports MediaTek MT2701 mmsys clocks.
32 This driver supports MediaTek MT2701 imgsys clocks.
38 This driver supports MediaTek MT2701 vdecsys clocks.
44 This driver supports MediaTek MT2701 hifsys clocks.
50 This driver supports MediaTek MT2701 ethsys clocks.
56 This driver supports MediaTek MT2701 bdpsys clocks.
62 This driver supports Mediatek MT2701 audsys clocks.
68 This driver supports MediaTek MT2701 g3dsys clocks.
76 This driver supports MediaTek MT2712 basic clocks.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dexynos5433-clock.txt10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
11 domains and bus clocks.
13 which generates clocks for LLI (Low Latency Interface) IP.
15 which generates clocks for DRAM Memory Controller domain.
17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
23 which generates clocks for G2D/MDMA IPs.
25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
27 which generates clocks for Cortex-A5/BUS/AUDIO clocks.
[all …]

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