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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_rlc.c39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
73 adev->gfx.rlc.funcs->unset_safe_mode(adev); in amdgpu_gfx_rlc_exit_safe_mode()
74 adev->gfx.rlc.in_safe_mode = false; in amdgpu_gfx_rlc_exit_safe_mode()
97 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
98 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
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Damdgpu_gfx.c43 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
44 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
45 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
54 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
55 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
56 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
57 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
58 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
66 adev->gfx.mec.queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
74 bit += me * adev->gfx.me.num_pipe_per_me in amdgpu_gfx_me_queue_to_bit()
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Dgfx_v6_0.c341 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
344 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v6_0_init_microcode()
347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
348 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
349 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
352 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
355 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v6_0_init_microcode()
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
359 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
360 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
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Dgfx_v7_0.c930 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
933 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
938 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
941 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
946 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
949 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
954 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
957 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
963 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
966 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
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Dgfx_v8_0.c831 adev->gfx.scratch.num_reg = 8; in gfx_v8_0_scratch_init()
832 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v8_0_scratch_init()
833 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v8_0_scratch_init()
932 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
933 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
934 release_firmware(adev->gfx.me_fw); in gfx_v8_0_free_microcode()
935 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
936 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
937 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
938 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
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Dgfx_v9_0.c937 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
1000 adev->gfx.scratch.num_reg = 8; in gfx_v9_0_scratch_init()
1001 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_scratch_init()
1002 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v9_0_scratch_init()
1135 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1136 adev->gfx.pfp_fw = NULL; in gfx_v9_0_free_microcode()
1137 release_firmware(adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1138 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
1139 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1140 adev->gfx.ce_fw = NULL; in gfx_v9_0_free_microcode()
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Damdgpu_discovery.c395 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); in amdgpu_discovery_get_gfx_info()
396 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
398 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
399 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
400 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
401 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
402 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); in amdgpu_discovery_get_gfx_info()
403 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); in amdgpu_discovery_get_gfx_info()
404 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); in amdgpu_discovery_get_gfx_info()
405 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); in amdgpu_discovery_get_gfx_info()
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Dgfx_v10_0.c3335 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
3410 adev->gfx.scratch.num_reg = 8; in gfx_v10_0_scratch_init()
3411 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_scratch_init()
3412 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v10_0_scratch_init()
3551 release_firmware(adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
3552 adev->gfx.pfp_fw = NULL; in gfx_v10_0_free_microcode()
3553 release_firmware(adev->gfx.me_fw); in gfx_v10_0_free_microcode()
3554 adev->gfx.me_fw = NULL; in gfx_v10_0_free_microcode()
3555 release_firmware(adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
3556 adev->gfx.ce_fw = NULL; in gfx_v10_0_free_microcode()
[all …]
Damdgpu_kms.c243 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
244 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
247 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
248 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
251 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
252 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
255 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
256 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
259 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
260 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
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Damdgpu_amdkfd.c122 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
123 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
136 adev->gfx.mec.queue_bitmap, in amdgpu_amdkfd_device_init()
143 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
144 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
365 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
368 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
371 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
374 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
377 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
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Damdgpu_amdkfd_gfx_v9.c74 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
75 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
83 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
178 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_init_interrupts()
179 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_init_interrupts()
319 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_gfx_v9_hiq_mqd_load()
328 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_hiq_mqd_load()
329 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_hiq_mqd_load()
334 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
361 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
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Damdgpu_ucode.c420 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
421 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
422 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
423 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
424 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
425 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
426 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
427 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
428 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
550 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; in amdgpu_ucode_init_single_fw()
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Damdgpu_atomfirmware.c477 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; in amdgpu_atomfirmware_get_gfx_info()
478 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
479 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
480 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
481 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; in amdgpu_atomfirmware_get_gfx_info()
482 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
483 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
484 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; in amdgpu_atomfirmware_get_gfx_info()
485 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
487 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
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Damdgpu_debugfs.c243 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
244 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_process_reg_op()
709 config[no_regs++] = adev->gfx.config.max_shader_engines; in amdgpu_debugfs_gca_config_read()
710 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
711 config[no_regs++] = adev->gfx.config.max_cu_per_sh; in amdgpu_debugfs_gca_config_read()
712 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
713 config[no_regs++] = adev->gfx.config.max_backends_per_se; in amdgpu_debugfs_gca_config_read()
714 config[no_regs++] = adev->gfx.config.max_texture_channel_caches; in amdgpu_debugfs_gca_config_read()
715 config[no_regs++] = adev->gfx.config.max_gprs; in amdgpu_debugfs_gca_config_read()
716 config[no_regs++] = adev->gfx.config.max_gs_threads; in amdgpu_debugfs_gca_config_read()
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Damdgpu_amdkfd_gfx_v10_3.c69 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
70 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
78 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
128 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v10_3()
129 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v10_3()
211 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hqd_load_v10_3()
212 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hqd_load_v10_3()
295 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v10_3()
304 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hiq_mqd_load_v10_3()
305 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hiq_mqd_load_v10_3()
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Damdgpu_virt.c63 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_virt_kiq_reg_write_reg_wait()
492 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
493 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
494 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
495 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
496 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
497 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
498 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
499 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
500 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
Damdgpu_amdkfd_gfx_v10.c70 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
71 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
79 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
160 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_init_interrupts()
161 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_init_interrupts()
310 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_hiq_mqd_load()
319 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_hiq_mqd_load()
320 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_hiq_mqd_load()
325 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
352 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
Damdgpu_cgs.c173 fw_version = adev->gfx.ce_fw_version; in amdgpu_get_firmware_version()
176 fw_version = adev->gfx.pfp_fw_version; in amdgpu_get_firmware_version()
179 fw_version = adev->gfx.me_fw_version; in amdgpu_get_firmware_version()
182 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
185 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
188 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
191 fw_version = adev->gfx.rlc_fw_version; in amdgpu_get_firmware_version()
Dvcn_v1_0.c344 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
346 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
348 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
350 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
352 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
354 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
356 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
358 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
360 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
362 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
[all …]
Damdgpu_device.c438 adev->gfx.rlc.funcs && in amdgpu_mm_wreg_mmio_rlc()
439 adev->gfx.rlc.funcs->is_rlcg_access_range) { in amdgpu_mm_wreg_mmio_rlc()
440 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) in amdgpu_mm_wreg_mmio_rlc()
441 return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v); in amdgpu_mm_wreg_mmio_rlc()
1859 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); in amdgpu_device_parse_gpu_info_fw()
1860 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); in amdgpu_device_parse_gpu_info_fw()
1861 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); in amdgpu_device_parse_gpu_info_fw()
1862 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); in amdgpu_device_parse_gpu_info_fw()
1863 adev->gfx.config.max_texture_channel_caches = in amdgpu_device_parse_gpu_info_fw()
1865 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); in amdgpu_device_parse_gpu_info_fw()
[all …]
Damdgpu_amdkfd_gfx_v8.c70 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
71 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
132 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_init_interrupts()
133 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_init_interrupts()
187 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_hqd_load()
188 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_hqd_load()
Damdgpu_gfx.h326 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
327 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se…
328 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((a…
329 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpu/
Daspeed-gfx.txt6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Daspeed-gfx.txt8 - compatible: "aspeed,ast2500-gfx", "syscon"
14 gfx: display@1e6e6000 {
15 compatible = "aspeed,ast2500-gfx", "syscon";
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Daspeed-bmc-intel-s2600wf.dts117 &gfx {
122 aspeed,external-nodes = <&gfx &lhc>;

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