| /kernel/linux/linux-5.10/drivers/net/ipa/ |
| D | ipa_interrupt.c | 46 static bool ipa_interrupt_uc(struct ipa_interrupt *interrupt, u32 irq_id) in ipa_interrupt_uc() argument
52 static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id) in ipa_interrupt_process() argument
54 bool uc_irq = ipa_interrupt_uc(interrupt, irq_id); in ipa_interrupt_process()
55 struct ipa *ipa = interrupt->ipa; in ipa_interrupt_process()
64 if (irq_id < IPA_IRQ_COUNT && interrupt->handler[irq_id]) in ipa_interrupt_process()
65 interrupt->handler[irq_id](interrupt->ipa, irq_id); in ipa_interrupt_process()
76 static void ipa_interrupt_process_all(struct ipa_interrupt *interrupt) in ipa_interrupt_process_all() argument
78 struct ipa *ipa = interrupt->ipa; in ipa_interrupt_process_all()
79 u32 enabled = interrupt->enabled; in ipa_interrupt_process_all()
93 ipa_interrupt_process(interrupt, irq_id); in ipa_interrupt_process_all()
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/loongson/ |
| D | ls7a-pch.dtsi | 13 pic: interrupt-controller@10000000 {
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
19 #interrupt-cells = <2>;
26 interrupt-parent = <&pic>;
36 interrupt-parent = <&pic>;
46 interrupt-parent = <&pic>;
56 interrupt-parent = <&pic>;
66 #interrupt-cells = <2>;
83 interrupt-parent = <&pic>;
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | fsp2.dts | 64 #interrupt-cells = <2>;
66 interrupt-controller;
76 #interrupt-cells = <2>;
79 interrupt-controller;
82 interrupt-parent = <&UIC0>;
90 #interrupt-cells = <2>;
93 interrupt-controller;
96 interrupt-parent = <&UIC0>;
104 #interrupt-cells = <2>;
107 interrupt-controller;
[all …]
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/brcm/ |
| D | bcm7358.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
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| D | bcm7346.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
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| D | bcm7360.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
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| D | bcm7125.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller;
[all …]
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| D | bcm7362.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
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| D | bcm7420.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller;
[all …]
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| D | bcm7425.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@41a400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
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| D | bcm7435.dtsi | 42 cpu_intc: interrupt-controller {
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
47 #interrupt-cells = <1>;
71 periph_intc: interrupt-controller@41b500 {
76 interrupt-controller;
77 #interrupt-cells = <1>;
79 interrupt-parent = <&cpu_intc>;
83 sun_l2_intc: interrupt-controller@403000 {
86 interrupt-controller;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,c64x+megamod-pic.txt | 6 The core interrupt controller provides 16 prioritized interrupts to the
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
14 - #interrupt-cells: <1>
18 Single cell specifying the core interrupt priority level (4-15) where
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
25 #interrupt-cells = <1>;
33 The megamodule PIC consists of four interrupt mupliplexers each of which
34 combine up to 32 interrupt inputs into a single interrupt output which
35 may be cascaded into the core interrupt controller. The megamodule PIC
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| D | marvell,orion-intc.txt | 1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
18 intc: interrupt-controller {
20 interrupt-controller;
21 #interrupt-cells = <1>;
26 * Bridge interrupt controller
[all …]
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| D | brcm,bcm7120-l2-intc.txt | 1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
12 directly output an interrupt signal towards the interrupt controller parent,
13 or if they will output an interrupt signal at this 2nd level interrupt
20 - not all bits within the interrupt controller actually map to an interrupt
24 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
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| D | samsung,exynos4210-combiner.txt | 3 Samsung's Exynos4 architecture includes a interrupt combiner controller which
4 can combine interrupt sources as a group and provide a single interrupt request
5 for the group. The interrupt request from each group are connected to a parent
6 interrupt controller, such as GIC in case of Exynos4210.
8 The interrupt combiner controller consists of multiple combiners. Up to eight
9 interrupt sources can be connected to a combiner. The combiner outputs one
10 combined interrupt for its eight interrupt sources. The combined interrupt
11 is usually connected to a parent interrupt controller.
13 A single node in the device tree is used to describe the interrupt combiner
15 interrupt controller module shares config/control registers with other
[all …]
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| D | sigma,smp8642-intc.txt | 1 Sigma Designs SMP86xx/SMP87xx secondary interrupt controller
7 - interrupt-controller: boolean
13 - interrupt-controller: boolean
14 - #interrupt-cells: should be <2>, interrupt index and flags per interrupts.txt
15 - interrupts: interrupt spec of primary interrupt controller
19 interrupt-controller@6e000 {
23 interrupt-parent = <&gic>;
24 interrupt-controller;
28 irq0: interrupt-controller@0 {
30 interrupt-controller;
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| D | snps,dw-apb-ictl.txt | 1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
15 Additional required property when it's used as secondary interrupt controller:
16 - interrupts: interrupt reference to primary interrupt controller
18 The interrupt sources map to the corresponding bits in the interrupt
27 /* dw_apb_ictl is used as secondary interrupt controller */
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| D | marvell,icu.txt | 5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
28 - #interrupt-cells: Specifies the number of cells needed to encode an
29 interrupt source. The value shall be 2.
31 The 1st cell is the index of the interrupt in the ICU unit.
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
36 - interrupt-controller: Identifies the node as an interrupt
48 icu: interrupt-controller@1e0000 {
52 CP110_LABEL(icu_nsr): interrupt-controller@10 {
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| D | interrupts.txt | 1 Specifying interrupt information for devices
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
26 to reference multiple interrupt parents or a different interrupt parent than
28 and the interrupt specifier.
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | exynos5410-pinctrl.dtsi | 16 interrupt-controller;
17 #interrupt-cells = <2>;
24 interrupt-controller;
25 #interrupt-cells = <2>;
32 interrupt-controller;
33 #interrupt-cells = <2>;
40 interrupt-controller;
41 #interrupt-cells = <2>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
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| D | arm-realview-pba8.dts | 45 interrupt-parent = <&intc>;
47 interrupt-affinity = <&cpu0>;
50 /* Primary GIC PL390 interrupt controller in the test chip */
51 intc: interrupt-controller@1e000000 {
53 #interrupt-cells = <3>;
55 interrupt-controller;
62 interrupt-parent = <&intc>;
67 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
29 - interrupt-controller
32 Definition: Specifies that this node is an interrupt
35 - #interrupt-cells
38 Definition: Shall be 2 or 4. A value of 2 means that interrupt
39 specifiers do not contain the interrupt-type or type-specific
52 the boot program has initialized all interrupt source
57 that any initialization related to interrupt sources shall
73 - last-interrupt-source
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | xilinx-pcie.txt | 6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
11 - interrupts: Should contain AXI PCIe interrupt
12 - interrupt-map-mask,
13 interrupt-map: standard PCI properties to define the mapping of the
14 PCI interface to interrupt numbers.
26 - interrupt-controller: identifies the node as an interrupt controller
29 - #interrupt-cells: specifies the number of cells needed to encode an
30 interrupt source. The value must be 1.
33 The core provides a single interrupt for both INTx/MSI messages. So,
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/img/ |
| D | boston.dts | 6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
46 #interrupt-cells = <1>;
48 interrupt-parent = <&gic>;
56 interrupt-map-mask = <0 0 0 7>;
57 interrupt-map = <0 0 0 1 &pci0_intc 1>,
62 pci0_intc: interrupt-controller {
63 interrupt-controller;
65 #interrupt-cells = <1>;
76 #interrupt-cells = <1>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/ |
| D | exynos7-pinctrl.dtsi | 19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
36 interrupt-controller;
37 interrupt-parent = <&gic>;
38 #interrupt-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
61 interrupt-controller;
62 #interrupt-cells = <2>;
[all …]
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