Searched refs:output_mask (Results 1 – 13 of 13) sorted by relevance
479 u16 output_mask = channel->output_mask; in idtcm_sync_pps_output() local509 qn = output_mask & 0x1; in idtcm_sync_pps_output()510 output_mask = output_mask >> 1; in idtcm_sync_pps_output()511 qn_plus_1 = output_mask & 0x1; in idtcm_sync_pps_output()512 output_mask = output_mask >> 1; in idtcm_sync_pps_output()515 qn = output_mask & 0x1; in idtcm_sync_pps_output()516 output_mask = output_mask >> 1; in idtcm_sync_pps_output()520 qn_plus_1 = output_mask & 0x1; in idtcm_sync_pps_output()521 output_mask = output_mask >> 1; in idtcm_sync_pps_output()523 qn = output_mask & 0x1; in idtcm_sync_pps_output()[all …]
489 idt82p33->channel[0].output_mask = val; in idt82p33_check_and_set_masks()492 idt82p33->channel[1].output_mask = val; in idt82p33_check_and_set_masks()511 i, idt82p33->channel[i].output_mask); in idt82p33_display_masks()573 mask = channel->output_mask; in idt82p33_pps_enable()813 channel->caps.n_per_out = hweight8(channel->output_mask); in idt82p33_enable_channel()923 idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0; in idt82p33_probe()924 idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1; in idt82p33_probe()
122 u16 output_mask; member
126 u8 output_mask; member
25 u8 output_mask; member
129 u64 output_mask; member
628 if (pt->output_mask != reg) { in pt_config_buffer()629 pt->output_mask = reg; in pt_config_buffer()950 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, pt->output_mask); in pt_read_offset()952 buf->output_off = pt->output_mask >> 32; in pt_read_offset()955 buf->cur_idx = (pt->output_mask & 0xffffff80) >> 7; in pt_read_offset()
219 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { in pwm_samsung_request()497 chip->variant.output_mask |= BIT(val); in pwm_samsung_parse_dt()562 if (chip->variant.output_mask & BIT(chan)) in pwm_samsung_probe()614 if (our_chip->variant.output_mask & BIT(i)) in pwm_samsung_resume()
179 s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; in s3c64xx_set_timer_source()180 s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); in s3c64xx_set_timer_source()
227 s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; in s3c24xx_set_timer_source()228 s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); in s3c24xx_set_timer_source()
378 mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1); in _samsung_pwm_clocksource_init()432 pwm.variant.output_mask |= 1 << val; in samsung_pwm_alloc()
60 u64 output_mask; member
1192 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); in pt_load_msr()1206 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); in pt_save_msr()2005 msr_info->data = vmx->pt_desc.guest.output_mask; in vmx_get_msr()2271 vmx->pt_desc.guest.output_mask = data; in vmx_set_msr()4504 vmx->pt_desc.guest.output_mask = 0x7F; in init_vmcs()