Searched refs:ADDR_TM_2D_TILED_THIN1 (Results 1 – 6 of 6) sorted by relevance
798 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()804 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()808 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()1065 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()1132 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()1152 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()1158 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()1392 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()1411 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()1463 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
181 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()1129 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()1252 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()1262 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()1386 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()2251 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()2510 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()3022 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()3048 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()3158 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
1423 UINT_32 pipe = ComputePipeFromCoord(x, y, 0, ADDR_TM_2D_TILED_THIN1, 0, FALSE, pTileInfo); in HwlComputeXmaskAddrFromCoord()3348 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOptimizeTileMode()3379 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()3422 pInOut->tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSetPrtTileMode()3459 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()3465 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()3485 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
184 ADDR_TM_2D_TILED_THIN1 = 4, ///< A set of macro tiles consist of 8x8 tiles enumerator
708 case ADDR_TM_2D_TILED_THIN1: in gfx6_compute_level()913 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) { in gfx6_surface_settings()1069 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1; in gfx6_compute_surface()1171 AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && surf->u.legacy.bankw && in gfx6_compute_surface()1193 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1); in gfx6_compute_surface()1296 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) { in gfx6_compute_surface()
2473 ADDR_TM_2D_TILED_THIN1, in HwlComputeXmaskAddrFromCoord()3790 tileMode = ADDR_TM_2D_TILED_THIN1; in DegradeLargeThickTile()