Searched refs:ADDR_TM_PRT_TILED_THIN1 (Results 1 – 6 of 6) sorted by relevance
800 tileMode == ADDR_TM_PRT_TILED_THIN1 || in HwlComputeFmaskInfo()949 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlOptimizeTileMode()975 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlOptimizeTileMode()1023 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlOverrideTileMode()1074 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlOverrideTileMode()1185 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlSelectTileMode()1231 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlSetPrtTileMode()1376 case ADDR_TM_PRT_TILED_THIN1: in HwlSetupTileInfo()1395 case ADDR_TM_PRT_TILED_THIN1: in HwlSetupTileInfo()1417 case ADDR_TM_PRT_TILED_THIN1: in HwlSetupTileInfo()[all …]
187 case ADDR_TM_PRT_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()1131 case ADDR_TM_PRT_TILED_THIN1: in ComputeSurfaceMipLevelTileMode()1392 case ADDR_TM_PRT_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()2257 case ADDR_TM_PRT_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
3378 case ADDR_TM_PRT_TILED_THIN1: in HwlOverrideTileMode()
199 ADDR_TM_PRT_TILED_THIN1 = 19, ///< No bank/pipe rotation or hashing beyond macrotile size enumerator
705 case ADDR_TM_PRT_TILED_THIN1: in gfx6_compute_level()1061 AddrSurfInfoIn.tileMode = ADDR_TM_PRT_TILED_THIN1; in gfx6_compute_surface()
3805 tileMode = ADDR_TM_PRT_TILED_THIN1; in DegradeLargeThickTile()