1 /*
2 * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS-Core(M) MPU API for Armv7-M MPU
21 */
22
23 #ifndef ARM_MPU_ARMV7_H
24 #define ARM_MPU_ARMV7_H
25
26 #if defined ( __ICCARM__ )
27 #pragma system_include /* treat file as system include file for MISRA check */
28 #elif defined (__clang__)
29 #pragma clang system_header /* treat file as system include file */
30 #endif
31
32 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
33 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
34 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
35 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
36 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
37 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
38 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
39 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
40 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
41 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
42 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
43 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
44 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
45 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
46 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
47 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
48 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
49 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
50 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
51 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
52 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
53 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
54 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
55 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
56 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
57 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
58 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
59 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
60
61 #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
62 #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
63 #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
64 #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
65 #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
66 #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
67
68 /** MPU Region Base Address Register Value
69 *
70 * \param Region The region to be configured, number 0 to 15.
71 * \param BaseAddress The base address for the region.
72 */
73 #define ARM_MPU_RBAR(Region, BaseAddress) \
74 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
75 ((Region) & MPU_RBAR_REGION_Msk) | \
76 (MPU_RBAR_VALID_Msk))
77
78 /**
79 * MPU Memory Access Attributes
80 *
81 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
82 * \param IsShareable Region is shareable between multiple bus masters.
83 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
84 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
85 */
86 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
87 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
88 (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
89 (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
90 (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
91
92 /**
93 * MPU Region Attribute and Size Register Value
94 *
95 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
96 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
97 * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
98 * \param SubRegionDisable Sub-region disable field.
99 * \param Size Region size of the region to be configured, for example 4K, 8K.
100 */
101 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
102 ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
103 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
104 (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
105 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
106 (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
107 (((MPU_RASR_ENABLE_Msk))))
108
109 /**
110 * MPU Region Attribute and Size Register Value
111 *
112 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
113 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
114 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
115 * \param IsShareable Region is shareable between multiple bus masters.
116 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
117 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
118 * \param SubRegionDisable Sub-region disable field.
119 * \param Size Region size of the region to be configured, for example 4K, 8K.
120 */
121 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
122 ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
123
124 /**
125 * MPU Memory Access Attribute for strongly ordered memory.
126 * - TEX: 000b
127 * - Shareable
128 * - Non-cacheable
129 * - Non-bufferable
130 */
131 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
132
133 /**
134 * MPU Memory Access Attribute for device memory.
135 * - TEX: 000b (if shareable) or 010b (if non-shareable)
136 * - Shareable or non-shareable
137 * - Non-cacheable
138 * - Bufferable (if shareable) or non-bufferable (if non-shareable)
139 *
140 * \param IsShareable Configures the device memory as shareable or non-shareable.
141 */
142 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
143
144 /**
145 * MPU Memory Access Attribute for normal memory.
146 * - TEX: 1BBb (reflecting outer cacheability rules)
147 * - Shareable or non-shareable
148 * - Cacheable or non-cacheable (reflecting inner cacheability rules)
149 * - Bufferable or non-bufferable (reflecting inner cacheability rules)
150 *
151 * \param OuterCp Configures the outer cache policy.
152 * \param InnerCp Configures the inner cache policy.
153 * \param IsShareable Configures the memory as shareable or non-shareable.
154 */
155 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
156
157 /**
158 * MPU Memory Access Attribute non-cacheable policy.
159 */
160 #define ARM_MPU_CACHEP_NOCACHE 0U
161
162 /**
163 * MPU Memory Access Attribute write-back, write and read allocate policy.
164 */
165 #define ARM_MPU_CACHEP_WB_WRA 1U
166
167 /**
168 * MPU Memory Access Attribute write-through, no write allocate policy.
169 */
170 #define ARM_MPU_CACHEP_WT_NWA 2U
171
172 /**
173 * MPU Memory Access Attribute write-back, no write allocate policy.
174 */
175 #define ARM_MPU_CACHEP_WB_NWA 3U
176
177
178 /**
179 * Struct for a single MPU Region
180 */
181 typedef struct {
182 uint32_t RBAR; //!< The region base address register value (RBAR)
183 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
184 } ARM_MPU_Region_t;
185
186 /** Enable the MPU.
187 * \param MPU_Control Default access permissions for unconfigured regions.
188 */
ARM_MPU_Enable(uint32_t MPU_Control)189 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
190 {
191 __DMB();
192 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
193 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
194 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
195 #endif
196 __DSB();
197 __ISB();
198 }
199
200 /** Disable the MPU.
201 */
ARM_MPU_Disable(void)202 __STATIC_INLINE void ARM_MPU_Disable(void)
203 {
204 __DMB();
205 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
206 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
207 #endif
208 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
209 __DSB();
210 __ISB();
211 }
212
213 /** Clear and disable the given MPU region.
214 * \param rnr Region number to be cleared.
215 */
ARM_MPU_ClrRegion(uint32_t rnr)216 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
217 {
218 MPU->RNR = rnr;
219 MPU->RASR = 0U;
220 }
221
222 /** Configure an MPU region.
223 * \param rbar Value for RBAR register.
224 * \param rasr Value for RASR register.
225 */
ARM_MPU_SetRegion(uint32_t rbar,uint32_t rasr)226 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
227 {
228 MPU->RBAR = rbar;
229 MPU->RASR = rasr;
230 }
231
232 /** Configure the given MPU region.
233 * \param rnr Region number to be configured.
234 * \param rbar Value for RBAR register.
235 * \param rasr Value for RASR register.
236 */
ARM_MPU_SetRegionEx(uint32_t rnr,uint32_t rbar,uint32_t rasr)237 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
238 {
239 MPU->RNR = rnr;
240 MPU->RBAR = rbar;
241 MPU->RASR = rasr;
242 }
243
244 /** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
245 * \param dst Destination data is copied to.
246 * \param src Source data is copied from.
247 * \param len Amount of data words to be copied.
248 */
ARM_MPU_OrderedMemcpy(volatile uint32_t * dst,const uint32_t * __RESTRICT src,uint32_t len)249 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
250 {
251 uint32_t i;
252 for (i = 0U; i < len; ++i)
253 {
254 dst[i] = src[i];
255 }
256 }
257
258 /** Load the given number of MPU regions from a table.
259 * \param table Pointer to the MPU configuration table.
260 * \param cnt Amount of regions to be configured.
261 */
ARM_MPU_Load(ARM_MPU_Region_t const * table,uint32_t cnt)262 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
263 {
264 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
265 while (cnt > MPU_TYPE_RALIASES) {
266 ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
267 table += MPU_TYPE_RALIASES;
268 cnt -= MPU_TYPE_RALIASES;
269 }
270 ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
271 }
272
273 #endif
274