/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | Thumb2InstrInfo.cpp | 479 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in rewriteT2FrameIndex() local 488 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2? in rewriteT2FrameIndex() 559 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) in rewriteT2FrameIndex() 565 if (AddrMode == ARMII::AddrModeT2_so) { in rewriteT2FrameIndex() 575 AddrMode = ARMII::AddrModeT2_i12; in rewriteT2FrameIndex() 580 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) { in rewriteT2FrameIndex() 594 } else if (AddrMode == ARMII::AddrMode5) { in rewriteT2FrameIndex() 608 } else if (AddrMode == ARMII::AddrMode5FP16) { in rewriteT2FrameIndex() 622 } else if (AddrMode == ARMII::AddrModeT2_i7s4 || in rewriteT2FrameIndex() 623 AddrMode == ARMII::AddrModeT2_i7s2 || in rewriteT2FrameIndex() [all …]
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D | ARMInstrFormats.td | 90 class AddrMode<bits<5> val> { 93 def AddrModeNone : AddrMode<0>; 94 def AddrMode1 : AddrMode<1>; 95 def AddrMode2 : AddrMode<2>; 96 def AddrMode3 : AddrMode<3>; 97 def AddrMode4 : AddrMode<4>; 98 def AddrMode5 : AddrMode<5>; 99 def AddrMode6 : AddrMode<6>; 100 def AddrModeT1_1 : AddrMode<7>; 101 def AddrModeT1_2 : AddrMode<8>; [all …]
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D | ARMBaseRegisterInfo.cpp | 500 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in getFrameIndexInstrOffset() local 504 switch (AddrMode) { in getFrameIndexInstrOffset() 686 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in isFrameOffsetLegal() local 692 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) in isFrameOffsetLegal() 698 switch (AddrMode) { in isFrameOffsetLegal()
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D | ARMISelLowering.h | 369 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 377 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, 380 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 384 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
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D | ARMInstrNEON.td | 623 class VLD1D<bits<4> op7_4, string Dt, Operand AddrMode> 625 (ins AddrMode:$Rn), IIC_VLD1, 631 class VLD1Q<bits<4> op7_4, string Dt, Operand AddrMode> 633 (ins AddrMode:$Rn), IIC_VLD1x2, 651 multiclass VLD1DWB<bits<4> op7_4, string Dt, Operand AddrMode> { 653 (ins AddrMode:$Rn), IIC_VLD1u, 661 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u, 668 multiclass VLD1QWB<bits<4> op7_4, string Dt, Operand AddrMode> { 670 (ins AddrMode:$Rn), IIC_VLD1x2u, 678 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u, [all …]
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D | ThumbRegisterInfo.cpp | 371 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in rewriteFrameIndex() local 382 if (AddrMode != ARMII::AddrModeT1_s) in rewriteFrameIndex()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
D | CodeGenPrepare.cpp | 2179 struct ExtAddrMode : public TargetLowering::AddrMode { 2865 ExtAddrMode &AddrMode; member in __anone2ed542f0711::AddressingModeMatcher 2898 MemoryInst(MI), AddrMode(AM), InsertedInsts(InsertedInsts), in AddressingModeMatcher() 3606 if (AddrMode.Scale != 0 && AddrMode.ScaledReg != ScaleReg) in matchScaledValue() 3609 ExtAddrMode TestAddrMode = AddrMode; in matchScaledValue() 3621 AddrMode = TestAddrMode; in matchScaledValue() 3637 AddrMode = TestAddrMode; in matchScaledValue() 4193 ExtAddrMode BackupAddrMode = AddrMode; in matchOperationAddr() 4202 AddrMode.InBounds = false; in matchOperationAddr() 4208 AddrMode = BackupAddrMode; in matchOperationAddr() [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/ |
D | MSP430Disassembler.cpp | 142 enum AddrMode { enum 154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode() 181 static AddrMode DecodeSrcAddrModeI(unsigned Insn) { in DecodeSrcAddrModeI() 187 static AddrMode DecodeSrcAddrModeII(unsigned Insn) { in DecodeSrcAddrModeII() 193 static AddrMode DecodeDstAddrMode(unsigned Insn) { in DecodeDstAddrMode() 205 static const uint8_t *getDecoderTable(AddrMode SrcAM, unsigned Words) { in getDecoderTable() 234 AddrMode SrcAM = DecodeSrcAddrModeI(Insn); in getInstructionI() 235 AddrMode DstAM = DecodeDstAddrMode(Insn); in getInstructionI() 289 AddrMode SrcAM = DecodeSrcAddrModeII(Insn); in getInstructionII()
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/third_party/vixl/src/aarch32/ |
D | operands-aarch32.h | 637 explicit MemOperand(Register rn, AddrMode addrmode = Offset) 654 MemOperand(Register rn, int32_t offset, AddrMode addrmode = Offset) 664 MemOperand(Register rn, Sign sign, int32_t offset, AddrMode addrmode = Offset) 681 MemOperand(Register rn, Sign sign, Register rm, AddrMode addrmode = Offset) 695 MemOperand(Register rn, Register rm, AddrMode addrmode = Offset) 715 AddrMode addrmode = Offset) 731 MemOperand(Register rn, Register rm, Shift shift, AddrMode addrmode = Offset) 754 AddrMode addrmode = Offset) 775 AddrMode addrmode = Offset) 799 AddrMode GetAddrMode() const { in GetAddrMode() [all …]
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D | macro-assembler-aarch32.cc | 317 AddrMode addrmode) { in GetOffsetMask() 1733 AddrMode addrmode = operand.GetAddrMode(); in Delegate() 1818 AddrMode addrmode = operand.GetAddrMode(); in Delegate() 1955 AddrMode addrmode = operand.GetAddrMode(); in Delegate() 2046 AddrMode addrmode = operand.GetAddrMode(); in Delegate() 2123 AddrMode addrmode = operand.GetAddrMode(); in Delegate() 2196 AddrMode addrmode = operand.GetAddrMode(); in Delegate()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMBaseInfo.h | 185 enum AddrMode { enum 210 inline static const char *AddrModeToString(AddrMode addrmode) { in AddrModeToString()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIISelLowering.h | 184 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 185 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 238 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 239 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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/third_party/vixl/src/aarch64/ |
D | operands-aarch64.h | 396 AddrMode addrmode = Offset); 405 MemOperand(Register base, const Operand& offset, AddrMode addrmode = Offset); 417 AddrMode GetAddrMode() const { return addrmode_; } in GetAddrMode() 471 AddrMode addrmode_;
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D | operands-aarch64.cc | 236 MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode) in MemOperand() 285 MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode) in MemOperand()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
D | HexagonBaseInfo.h | 35 enum AddrMode { enum
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
D | ARCISelLowering.h | 73 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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D | ARCInstrFormats.td | 70 class AddrMode<bits<2> mode, string instSfx, string asmSfx> { 89 def NoAM : AddrMode<0b00, "", "">; 90 def PreIncAM : AddrMode<0b01, "_AW", ".aw">; 91 def PostIncAM : AddrMode<0b10, "_AB", ".ab">; 109 AddrMode AA = NoAM;
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/third_party/node/deps/v8/src/codegen/arm/ |
D | assembler-arm.h | 197 explicit MemOperand(Register rn, int32_t offset = 0, AddrMode am = Offset); 202 explicit MemOperand(Register rn, Register rm, AddrMode am = Offset); 208 AddrMode am = Offset); 211 AddrMode am = Offset) { 228 AddrMode am() const { return am_; } in am() 240 AddrMode am_; // bits P, U, and W 251 explicit NeonMemOperand(Register rn, AddrMode am = Offset, int align = 0);
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyISelLowering.h | 67 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
D | IceInstARM32.h | 88 enum AddrMode { enum 107 AddrMode Mode = Offset) { 115 AddrMode Mode = Offset) { 124 AddrMode getAddrMode() const { return Mode; } in getAddrMode() 152 ConstantInteger32 *ImmOffset, AddrMode Mode); 154 ShiftKind ShiftOp, uint16_t ShiftAmt, AddrMode Mode); 161 AddrMode Mode;
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D | IceInstMIPS32.h | 121 enum AddrMode { Offset }; enum 130 Operand *ImmOffset, AddrMode Mode = Offset) { 137 AddrMode getAddrMode() const { return Mode; } in getAddrMode() 172 AddrMode Mode); 176 const AddrMode Mode;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
D | AVRISelLowering.h | 91 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
D | XCoreISelLowering.h | 124 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVISelLowering.h | 68 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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/third_party/node/deps/v8/src/execution/arm64/ |
D | simulator-arm64.h | 1494 void LoadStoreHelper(Instruction* instr, int64_t offset, AddrMode addrmode); 1495 void LoadStorePairHelper(Instruction* instr, AddrMode addrmode); 1497 AddrMode addrmode); 1498 void LoadStoreWriteBack(unsigned addr_reg, int64_t offset, AddrMode addrmode); 1500 AddrMode addr_mode); 1502 AddrMode addr_mode);
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