| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/include/llvm/Support/ |
| D | Allocator.h | 243 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); in Allocate() local
244 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); in Allocate()
245 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
253 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); in Allocate() local
254 assert(AlignedAddr + Size <= (uintptr_t)End && in Allocate()
256 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | Allocator.h | 250 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); in Allocate() local
251 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); in Allocate()
252 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
260 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); in Allocate() local
261 assert(AlignedAddr + SizeToAllocate <= (uintptr_t)End && in Allocate()
263 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.h | 211 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
217 Value *AlignedAddr, Value *CmpVal,
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| D | RISCVISelLowering.cpp | 2813 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic() argument
2818 Type *Tys[] = {AlignedAddr->getType()}; in emitMaskedAtomicRMWIntrinsic()
2844 {AlignedAddr, Incr, Mask, SextShamt, Ordering}); in emitMaskedAtomicRMWIntrinsic()
2847 Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering}); in emitMaskedAtomicRMWIntrinsic()
2865 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, in emitMaskedAtomicCmpXchgIntrinsic() argument
2876 Type *Tys[] = {AlignedAddr->getType()}; in emitMaskedAtomicCmpXchgIntrinsic()
2880 MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering}); in emitMaskedAtomicCmpXchgIntrinsic()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | AtomicExpandPass.cpp | 615 Value *AlignedAddr; member
662 Ret.AlignedAddr = Builder.CreateIntToPtr( in createMaskInstrs()
767 insertRMWCmpXchgLoop(Builder, PMV.WordType, PMV.AlignedAddr, MemOpOrder, in expandPartwordAtomicRMW()
800 AtomicRMWInst *NewAI = Builder.CreateAtomicRMW(Op, PMV.AlignedAddr, in widenPartwordAtomicRMW()
879 LoadInst *InitLoaded = Builder.CreateLoad(PMV.WordType, PMV.AlignedAddr); in expandPartwordCmpXchg()
893 PMV.AlignedAddr, FullWord_Cmp, FullWord_NewVal, CI->getSuccessOrdering(), in expandPartwordCmpXchg()
966 Builder, AI, PMV.AlignedAddr, ValOperand_Shifted, PMV.Mask, PMV.ShiftAmt, in expandAtomicRMWToMaskedIntrinsic()
988 Builder, CI, PMV.AlignedAddr, CmpVal_Shifted, NewVal_Shifted, PMV.Mask, in expandAtomicCmpXchgToMaskedIntrinsic()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1664 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicBinaryPartword() local
1783 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) in emitAtomicBinaryPartword()
1810 .addReg(AlignedAddr) in emitAtomicBinaryPartword()
1913 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicCmpSwapPartword() local
1970 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) in emitAtomicCmpSwapPartword()
2002 .addReg(AlignedAddr) in emitAtomicCmpSwapPartword()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 1732 Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic() argument
1742 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, in emitMaskedAtomicCmpXchgIntrinsic() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 3852 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, in lowerATOMIC_LOAD_OP() local
3881 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
3968 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, in lowerATOMIC_CMP_SWAP() local
3984 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift, in lowerATOMIC_CMP_SWAP()
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