Searched refs:AndOpc (Results 1 – 5 of 5) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SILowerControlFlow.cpp | 86 unsigned AndOpc; member in __anon86f0e7a80111::SILowerControlFlow
226 BuildMI(MBB, I, DL, TII->get(AndOpc), Tmp) in emitIf()
312 BuildMI(MBB, ElsePt, DL, TII->get(AndOpc), DstReg) in emitElse()
376 And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), AndReg) in emitIfBreak()
508 AndOpc = AMDGPU::S_AND_B32; in runOnMachineFunction()
517 AndOpc = AMDGPU::S_AND_B64; in runOnMachineFunction()
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| D | SIOptimizeExecMaskingPreRA.cpp | 196 const unsigned AndOpc = Wave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64; in optimizeVcndVcmpPair() local
210 if (!And || And->getOpcode() != AndOpc || in optimizeVcndVcmpPair()
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| D | AMDGPUInstructionSelector.cpp | 124 unsigned AndOpc = TRI.isSGPRClass(SrcRC) ? in selectCOPY() local
126 BuildMI(*BB, &I, DL, TII.get(AndOpc), MaskedReg) in selectCOPY()
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| D | SIInstrInfo.cpp | 4339 unsigned AndOpc = in emitLoadSRsrcFromVGPRLoop() local
4389 BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndCond) in emitLoadSRsrcFromVGPRLoop()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 849 unsigned AndOpc; in selectZext() local
851 AndOpc = X86::AND8ri; in selectZext()
853 AndOpc = X86::AND16ri8; in selectZext()
855 AndOpc = X86::AND32ri8; in selectZext()
857 AndOpc = X86::AND64ri8; in selectZext()
872 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg) in selectZext()
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