| /third_party/mesa3d/src/freedreno/afuc/ |
| D | emu-ui.c | 515 BITSET_FOREACH_SET (i, emu->gpr_regs.written, EMU_NUM_GPR_REGS) { in emu_dump_state_change()
519 BITSET_FOREACH_SET (i, emu->gpu_regs.written, EMU_NUM_GPU_REGS) { in emu_dump_state_change()
523 BITSET_FOREACH_SET (i, emu->pipe_regs.written, EMU_NUM_PIPE_REGS) { in emu_dump_state_change()
527 BITSET_FOREACH_SET (i, emu->control_regs.written, EMU_NUM_CONTROL_REGS) { in emu_dump_state_change()
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| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_compiler_nir_liveness.c | 242 BITSET_FOREACH_SET(i, block->live_in, state.num_defs) in etna_live_defs()
245 BITSET_FOREACH_SET(i, block->live_out, state.num_defs) in etna_live_defs()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_nir_opt_outputs.c | 131 BITSET_FOREACH_SET(p, outputs_optimized, current) { in ac_eliminate_duplicated_output()
315 BITSET_FOREACH_SET(i, outputs_optimized, NUM_TOTAL_VARYING_SLOTS) { in ac_nir_optimize_outputs()
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| /third_party/mesa3d/src/gallium/drivers/lima/ir/gp/ |
| D | regalloc.c | 176 BITSET_FOREACH_SET(live_reg, ctx->live, ctx->comp->cur_reg) { in add_all_interferences()
189 BITSET_FOREACH_SET(live_idx, live_reg, ctx->comp->cur_reg) { in print_liveness()
367 BITSET_FOREACH_SET(reg_idx, block->live_out, ctx->comp->cur_reg) { in assign_regs()
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| /third_party/mesa3d/src/gallium/drivers/lima/ir/pp/ |
| D | regalloc.c | 525 BITSET_FOREACH_SET(i, liveness, comp->reg_num) { in ppir_all_interference()
526 BITSET_FOREACH_SET(j, liveness, comp->reg_num) { in ppir_all_interference()
555 BITSET_FOREACH_SET(i, instr->live_internal, comp->reg_num) { in ppir_regalloc_prog_try()
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| /third_party/mesa3d/src/gallium/drivers/freedreno/ |
| D | .clang-format | 25 - BITSET_FOREACH_SET
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| /third_party/mesa3d/src/freedreno/ |
| D | .clang-format | 25 - BITSET_FOREACH_SET
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| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3_liveness.c | 103 BITSET_FOREACH_SET (name, tmp_live, live->definitions_count) { in compute_block_liveness()
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| D | ir3_spill.c | 1610 BITSET_FOREACH_SET (name, ctx->live->live_in[block->index], in spill_single_pred_live_in()
1689 BITSET_FOREACH_SET (name, state->live_out, ctx->live->definitions_count) { in reload_live_outs()
1797 BITSET_FOREACH_SET (name, ctx->live->live_in[block->index], in handle_block()
1822 BITSET_FOREACH_SET (name, ctx->live->live_in[block->index], in handle_block()
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| D | ir3_ra.c | 2253 BITSET_FOREACH_SET (name, ctx->live->live_in[block->index], in handle_block()
2311 BITSET_FOREACH_SET (name, ctx->live->live_out[block->index], in handle_block()
2426 BITSET_FOREACH_SET (name, live->live_in[block->index], in calc_min_limit_pressure()
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| /third_party/mesa3d/src/compiler/nir/ |
| D | nir_phi_builder.c | 135 BITSET_FOREACH_SET(i, defs, pb->num_blocks) { in nir_phi_builder_add_value()
|
| /third_party/mesa3d/src/util/ |
| D | register_allocate.c | 208 BITSET_FOREACH_SET(c, reg->conflicts, regs->count) { in ra_make_reg_conflicts_transitive()
333 BITSET_FOREACH_SET(rc, regs->classes[c]->regs, regs->count) { in ra_set_finalize()
360 BITSET_FOREACH_SET(rc, regs->classes[c]->regs, regs->count) { in ra_set_finalize()
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| D | bitset.h | 368 #define BITSET_FOREACH_SET(__i, __set, __size) \ macro
|
| /third_party/mesa3d/src/panfrost/midgard/ |
| D | mir_promote_uniforms.c | 107 BITSET_FOREACH_SET(vec4, block->uses, MAX_UBO_QWORDS) { in mir_pick_ubo()
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| D | midgard_schedule.c | 332 BITSET_FOREACH_SET(i, done->dependents, count) { in mir_update_worklist()
691 BITSET_FOREACH_SET(i, worklist, count) { in mir_choose_instruction()
695 BITSET_FOREACH_SET(i, worklist, count) { in mir_choose_instruction()
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| /third_party/mesa3d/src/panfrost/bifrost/ |
| D | bi_opt_push_ubo.c | 198 BITSET_FOREACH_SET(neighbour, adjacency[node].row, PAN_MAX_PUSH) { in bi_find_component()
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| D | bi_schedule.c | 485 BITSET_FOREACH_SET(i, st.dependents[idx], st.count) { in bi_update_worklist()
1184 BITSET_FOREACH_SET(i, st.worklist, st.count) { in bi_choose_index()
1946 BITSET_FOREACH_SET(i, st.worklist, st.count) { in bi_schedule_block()
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| /third_party/mesa3d/src/mesa/main/ |
| D | performance_monitor.c | 114 BITSET_FOREACH_SET(cid, m->ActiveCounters[gid], g->NumCounters) { in init_perf_monitor()
948 BITSET_FOREACH_SET(counter, m->ActiveCounters[group], g->NumCounters) { in perf_monitor_result_size()
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| /third_party/mesa3d/src/gallium/drivers/panfrost/ |
| D | pan_job.c | 43 BITSET_FOREACH_SET(idx, ctx->batches.active, PAN_MAX_BATCHES)
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| /third_party/mesa3d/src/gallium/drivers/asahi/ |
| D | agx_pipe.c | 531 BITSET_FOREACH_SET(handle, batch->bo_list, sizeof(batch->bo_list) * 8) { in agx_flush()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | test_eu_validate.cpp | 358 BITSET_FOREACH_SET(e, invalid_encodings, num_encodings) { in TEST_P()
436 BITSET_FOREACH_SET(e, invalid_encodings, num_encodings) { in TEST_P()
528 BITSET_FOREACH_SET(e, invalid_encodings, num_encodings) { in TEST_P()
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| /third_party/mesa3d/src/mesa/program/ |
| D | prog_to_nir.c | 920 BITSET_FOREACH_SET(i, c->prog->info.system_values_read, SYSTEM_VALUE_MAX) { in setup_registers_and_variables()
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| /third_party/mesa3d/src/panfrost/vulkan/ |
| D | panvk_vX_pipeline.c | 803 BITSET_FOREACH_SET(loc, pipeline->varyings.active, VARYING_SLOT_MAX) { in panvk_pipeline_builder_collect_varyings()
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| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_from_nir.cpp | 994 BITSET_FOREACH_SET(i, nir->info.system_values_read, SYSTEM_VALUE_MAX) { in assignSlots()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 20.0.0.rst | 2519 - util: Explain BITSET_FOREACH_SET params
2520 - util: Remove tmp argument from BITSET_FOREACH_SET macro
|